);
- }
-
- irq_exit();
- set_irq_regs(old_regs);
+ __handle_domain_irq(NULL, irq, false, regs);
}
The only thing that's missing is a pr_warn_ratelimited(). Do we still
need it? We could add it to ack_bad_irq() though.
Either way:
Acked-by: Catalin Marinas catalin.mari
On Tue, Aug 26, 2014 at 11:03:40AM +0100, Marc Zyngier wrote:
All the arm64 irqchip drivers have been converted to handle_domain_irq,
making it possible to remove the handle_IRQ stub entierely.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
Acked-by: Catalin Marinas catalin.mari...@arm.com
On Mon, Nov 25, 2013 at 07:44:08PM +, Santosh Shilimkar wrote:
On Monday 25 November 2013 12:28 PM, Catalin Marinas wrote:
On Mon, Nov 25, 2013 at 04:59:16PM +, Santosh Shilimkar wrote:
What I am saying is the platforms like OMAP5 already support PM in
mainline kernel and we can't
On Mon, Nov 25, 2013 at 04:59:16PM +, Santosh Shilimkar wrote:
On Monday 25 November 2013 11:33 AM, Christoffer Dall wrote:
On 25 November 2013 08:28, Santosh Shilimkar santosh.shilim...@ti.com
wrote:
On Monday 25 November 2013 10:09 AM, Christoffer Dall wrote:
On 23 November 2013
: Simon Horman ho...@verge.net.au
Cc: Magnus Damm magnus.d...@gmail.com
Cc: Catalin Marinas catalin.mari...@arm.com
Cc: Will Deacon will.dea...@arm.com
Cc: John Stultz john.stu...@linaro.org
Cc: Thomas Gleixner t...@linutronix.de
Cc: linux-samsung-...@vger.kernel.org
Cc: linux-omap
On Mon, Mar 25, 2013 at 09:28:10PM +, Rob Herring wrote:
On 03/25/2013 12:26 PM, Russell King - ARM Linux wrote:
On Thu, Mar 21, 2013 at 11:06:47AM +, Mark Rutland wrote:
On TC2 this series leads to using the vexpress 24MHz clock as the sched
clock
in preference to the
On Sat, Jan 26, 2013 at 12:31:58AM +, Christoffer Dall wrote:
When using LPAE the call to alloc_init_pte is passed then end address
for the entire 1st level page table region, and the code unluckily ends
up going over the bounds of the single allocated PTE, which is sad.
This caused LPAE
On 16 November 2012 18:39, Russell King - ARM Linux
li...@arm.linux.org.uk wrote:
On Fri, Nov 16, 2012 at 06:09:28PM +, Catalin Marinas wrote:
On Fri, Nov 16, 2012 at 09:59:21AM +, Russell King - ARM Linux wrote:
On Thu, Nov 15, 2012 at 08:31:33AM -0600, Rob Herring wrote:
So we
On Fri, Nov 16, 2012 at 09:59:21AM +, Russell King - ARM Linux wrote:
On Thu, Nov 15, 2012 at 08:31:33AM -0600, Rob Herring wrote:
So we should make all these work-arounds depend on !MULTI_PLATFORM then.
No, because some of the work-arounds don't require setting bits in magic
registers.
On Thu, Nov 15, 2012 at 12:54:48AM +, Rob Herring wrote:
On 11/14/2012 04:21 PM, Tony Lindgren wrote:
* Rob Herring robherri...@gmail.com [121114 13:59]:
On 11/14/2012 02:32 PM, Tony Lindgren wrote:
Checking for the bit already set should work in this case, I'll post
a patch for
On Thu, Nov 15, 2012 at 12:41:43PM +, Siarhei Siamashka wrote:
On Thu, Nov 15, 2012 at 1:01 PM, Catalin Marinas
catalin.mari...@arm.com wrote:
On Thu, Nov 15, 2012 at 12:54:48AM +, Rob Herring wrote:
On 11/14/2012 04:21 PM, Tony Lindgren wrote:
* Rob Herring robherri...@gmail.com
On Thu, Nov 15, 2012 at 02:31:33PM +, Rob Herring wrote:
On 11/15/2012 05:01 AM, Catalin Marinas wrote:
On Thu, Nov 15, 2012 at 12:54:48AM +, Rob Herring wrote:
On 11/14/2012 04:21 PM, Tony Lindgren wrote:
* Rob Herring robherri...@gmail.com [121114 13:59]:
On 11/14/2012 02:32 PM
On Thu, Nov 15, 2012 at 03:37:08PM +, Rob Herring wrote:
On 11/15/2012 08:37 AM, Catalin Marinas wrote:
On Thu, Nov 15, 2012 at 02:31:33PM +, Rob Herring wrote:
Does that work for Versatile Express CA9? It needs ARM_ERRATA_751472.
On VE Linux runs in secure mode, so it's fine
On Wed, Sep 12, 2012 at 01:46:18PM +0100, Cyril Chemparathy wrote:
On 9/12/2012 1:50 AM, R Sricharan wrote:
Even if CONFIG_DMA_ADDR_64BIT_T is enabled by the defconfig,
the feature is not getting selected.
Adding a string description in the Kconfig resolves this.
But not sure if this is
On Wed, Sep 12, 2012 at 01:57:26PM +0100, Shilimkar, Santosh wrote:
On Wed, Sep 12, 2012 at 6:16 PM, Cyril Chemparathy cy...@ti.com wrote:
On 9/12/2012 1:50 AM, R Sricharan wrote:
Even if CONFIG_DMA_ADDR_64BIT_T is enabled by the defconfig,
the feature is not getting selected.
Adding
On Wed, May 09, 2012 at 09:50:28AM +0100, Shilimkar, Santosh wrote:
On Wed, May 9, 2012 at 3:25 AM, Russell King - ARM Linux
li...@arm.linux.org.uk wrote:
On Tue, May 08, 2012 at 07:31:57PM +0530, Shilimkar, Santosh wrote:
Ok. Assuming you mean it's _not_ cleaner to have two domains where
regions but since the
decompressor code is generic, there might be many exceptions
for the devices used like debug console etc.
Signed-off-by: R Sricharan r.sricha...@ti.com
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
Cc: Russell King li...@arm.linux.org.uk
Cc: Catalin Marinas
: Catalin Marinas catalin.mari...@arm.com
---
arch/arm/boot/compressed/head.S | 10 --
1 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index dc7e8ce..a2602b8 100644
--- a/arch/arm/boot/compressed/head.S
+++ b
On Tue, May 08, 2012 at 03:20:43PM +0100, Santosh Shilimkar wrote:
On Tuesday 08 May 2012 07:46 PM, Catalin Marinas wrote:
On Tue, May 08, 2012 at 03:01:57PM +0100, Shilimkar, Santosh wrote:
From b906ef372f0e2dfa7e1fbc3c87406b1c303d8975 Mon Sep 17 00:00:00 2001
From: R Sricharan r.sricha
(sorry, I'm slow at replying, attending some internal ARM conference)
On 31 January 2012 18:09, Nicolas Pitre n...@fluxnic.net wrote:
On Tue, 31 Jan 2012, Catalin Marinas wrote:
Maybe we could factor out the CPU-specific settings from proc-v*.S
into a separate arch/arm/boot/preload directory
On 2 February 2012 14:49, Russell King - ARM Linux
li...@arm.linux.org.uk wrote:
On Thu, Feb 02, 2012 at 02:32:03PM +, Catalin Marinas wrote:
We could do the same and move the bit enabling to separate repository :).
We must certainly could do but that doesn't get around the errata
issues
On 31 January 2012 07:38, Shilimkar, Santosh santosh.shilim...@ti.com wrote:
On Tue, Jan 31, 2012 at 1:01 PM, Catalin Marinas
catalin.mari...@arm.com wrote:
On 31 January 2012 05:21, Aneesh V ane...@ti.com wrote:
On Friday 27 January 2012 11:00 PM, Catalin Marinas wrote:
On Fri, Jan 20, 2012
On 31 January 2012 09:05, Shilimkar, Santosh santosh.shilim...@ti.com wrote:
On Tue, Jan 31, 2012 at 2:24 PM, Catalin Marinas
catalin.mari...@arm.com wrote:
On 31 January 2012 07:38, Shilimkar, Santosh santosh.shilim...@ti.com
wrote:
On Tue, Jan 31, 2012 at 1:01 PM, Catalin Marinas
On 31 January 2012 10:10, Russell King - ARM Linux
li...@arm.linux.org.uk wrote:
On Tue, Jan 31, 2012 at 09:53:25AM +, Catalin Marinas wrote:
Maybe we could factor out the CPU-specific settings from proc-v*.S
into a separate arch/arm/boot/preload directory. We keep proc-v*.S
entirely
On 31 January 2012 05:21, Aneesh V ane...@ti.com wrote:
On Friday 27 January 2012 11:00 PM, Catalin Marinas wrote:
On Fri, Jan 20, 2012 at 08:57:11AM +, Joe Woodward wrote:
So I re-iterate that we need to have solution to this problem.
... I don't want to be a pain, but it seems to me
On Fri, Jan 20, 2012 at 08:57:11AM +, Joe Woodward wrote:
So I re-iterate that we need to have solution to this problem.
... I don't want to be a pain, but it seems to me that this dicussion
didn't reach a full conclussion?
Probably not, because it depends on many variables. See below
On Tue, Jan 17, 2012 at 08:54:44AM +, Joe Woodward wrote:
So, is the upshot of this that the kernel isn't going to be in a
position to enable the L2/outer cache on OMAP3 (due to the need for
hacky/unmaintainable code)?
Hence the bootloader/uBoot had better leave it enabled...
It could
On Tue, Jan 17, 2012 at 12:40:54PM +, Shilimkar, Santosh wrote:
On Tue, Jan 17, 2012 at 1:27 PM, Aneesh V ane...@ti.com wrote:
Hi Catalin,
On Tuesday 17 January 2012 05:41 PM, Catalin Marinas wrote:
On Tue, Jan 17, 2012 at 08:54:44AM +, Joe Woodward wrote:
So
On Tue, Jan 17, 2012 at 12:27:25PM +, Aneesh V wrote:
Hi Catalin,
On Tuesday 17 January 2012 05:41 PM, Catalin Marinas wrote:
On Tue, Jan 17, 2012 at 08:54:44AM +, Joe Woodward wrote:
So, is the upshot of this that the kernel isn't going to be in a
position to enable the L2/outer
On Tue, Jan 17, 2012 at 01:58:18PM +, Shilimkar, Santosh wrote:
On Tue, Jan 17, 2012 at 2:39 PM, Catalin Marinas
catalin.mari...@arm.com wrote:
On Tue, Jan 17, 2012 at 12:40:54PM +, Shilimkar, Santosh wrote:
On A15 infact there are other CP15 registers which needs to be set
before
On 7 September 2011 17:19, Russell King - ARM Linux
li...@arm.linux.org.uk wrote:
On Wed, Sep 07, 2011 at 04:41:32PM +0100, Catalin Marinas wrote:
On 1 September 2011 13:49, Russell King - ARM Linux
li...@arm.linux.org.uk wrote:
Add a dsb after the isb to ensure that the previous writes
On 7 September 2011 17:19, Russell King - ARM Linux
li...@arm.linux.org.uk wrote:
On Wed, Sep 07, 2011 at 04:41:32PM +0100, Catalin Marinas wrote:
On 1 September 2011 13:49, Russell King - ARM Linux
li...@arm.linux.org.uk wrote:
Add a dsb after the isb to ensure that the previous writes
On 16 May 2011 18:26, Russell King - ARM Linux li...@arm.linux.org.uk wrote:
--- a/arch/arm/mach-omap1/time.c
+++ b/arch/arm/mach-omap1/time.c
...
static inline unsigned long notrace omap_mpu_timer_read(int nr)
{
- volatile omap_mpu_timer_regs_t* timer = omap_mpu_timer_base(nr);
-
: Catalin Marinas catalin.mari...@arm.com
Cc: Will Deacon will.dea...@arm.com
---
Rebased on top of Will Deacon's ARM: gic: use handle_fasteoi_irq for SPIs
patch and boot tested on OMAP4430.
arch/arm/common/gic.c | 50 +---
1 files changed, 26
On Wed, 2011-04-06 at 00:19 +0100, Linus Walleij wrote:
2011/4/1 Linus Torvalds torva...@linux-foundation.org:
If you have discoverable hardware, use it.
But by discoverable hardware I mean something like PCI config
cycles. IOW, real hardware features.
The ARM AMBA architecture
On Tue, 2011-04-05 at 08:45 +0100, Russell King - ARM Linux wrote:
On Tue, Apr 05, 2011 at 12:10:24PM +0530, Santosh Shilimkar wrote:
The only issue I see is the clock-events implemented using
local timers capabilities in low power modes. The local timers
won't be able wakeup CPU from
On Mon, 2011-04-04 at 01:59 +0100, Arnd Bergmann wrote:
On Sunday 03 April 2011, Russell King - ARM Linux wrote:
Then there's those which change the cs-read function pointer at runtime,
...
and those which share that pointer with their sched_clock() implementation.
Abstracting
On Fri, 2011-04-01 at 10:32 +0100, Santosh Shilimkar wrote:
The GIC register accesses today make use of readl()/writel()
which prove to be very expensive when used along with mandatory
barriers. This mandatory barriers also introduces an un-necessary
and expensive l2x0_sync() operation. On
On Friday, 1 April 2011, Arnd Bergmann a...@arndb.de wrote:
On Friday 01 April 2011 23:10:04 Kevin Hilman wrote:
Arnd Bergmann a...@arndb.de writes:
On Friday 01 April 2011, Detlef Vollmann wrote:
On 04/01/11 15:54, Arnd Bergmann wrote:
9. All interesting work is going into a handful
On Thu, 2011-03-31 at 11:50 +0100, Russell King - ARM Linux wrote:
Given this thread, I've lost the motivation to continue with it because
it's just going to cause more 'pointless churn' and end up annoying
Linus even more.
I don't think the criticism was directed at the core ARM code that you
On Thu, 2011-03-31 at 13:55 +0100, Santosh Shilimkar wrote:
diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c
index f70ec7d..e013f65 100644
--- a/arch/arm/common/gic.c
+++ b/arch/arm/common/gic.c
@@ -89,7 +89,9 @@ static void gic_ack_irq(struct irq_data *d)
(Debug Control Register)
This patch also removes any OMAP dependency on PL310 Errata's
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
Acked-by: Catalin Marinas catalin.mari...@arm.com
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message
On 15 February 2011 07:14, Santosh Shilimkar santosh.shilim...@ti.com wrote:
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1140,7 +1140,7 @@ config ARM_ERRATA_742231
config PL310_ERRATA_588369
bool Clean Invalidate maintenance operations do not invalidate
clean lines
-
On Thu, 2011-02-10 at 13:04 +, Russell King - ARM Linux wrote:
On Wed, Feb 09, 2011 at 10:01:33AM +, Catalin Marinas wrote:
Could we make the domains usage a run-time feature based on the
architecture version? For ARMv7, we need to have the vectors page
read-only anyway if the SWP
On 8 February 2011 16:47, Russell King - ARM Linux
li...@arm.linux.org.uk wrote:
On Tue, Feb 08, 2011 at 10:06:20PM +0530, Santosh Shilimkar wrote:
Have tested this series on OMAP4430 and OMAP3430.
Don't know if it helps to push some of these patches to be part
of rc cycles. At least the SMP
On Thu, 2011-01-27 at 18:59 +, Russell King - ARM Linux wrote:
On Thu, Jan 27, 2011 at 06:14:56PM +, Catalin Marinas wrote:
On 17 January 2011 19:24, Russell King - ARM Linux
li...@arm.linux.org.uk wrote:
Rather than turning off CPU domain switching when the build architecture
On Fri, 2011-01-28 at 09:59 +, Russell King - ARM Linux wrote:
On Fri, Jan 28, 2011 at 09:46:06AM +, Catalin Marinas wrote:
My point is that we may want SWP_EMULATE disabled (or depending on !
CPU_USE_DOMAINS). With domains enabled every read-only user page is
writeable
On Fri, 2011-01-28 at 11:06 +, Russell King - ARM Linux wrote:
On Fri, Jan 28, 2011 at 10:46:51AM +, Catalin Marinas wrote:
On Fri, 2011-01-28 at 09:59 +, Russell King - ARM Linux wrote:
On Fri, Jan 28, 2011 at 09:46:06AM +, Catalin Marinas wrote:
My point is that we may
On Fri, 2011-01-28 at 13:05 +, Russell King - ARM Linux wrote:
On Fri, Jan 28, 2011 at 12:25:18PM +, Catalin Marinas wrote:
With your latest patches, do we use the TLS emulation on ARMv7 (UP) if
v6 is compiled in? If that's the case, we may have a problem - I talked
to the toolchain
On Fri, 2011-01-28 at 13:21 +, Russell King - ARM Linux wrote:
On Fri, Jan 28, 2011 at 12:25:18PM +, Catalin Marinas wrote:
With your latest patches, do we use the TLS emulation on ARMv7 (UP) if
v6 is compiled in? If that's the case, we may have a problem - I talked
to the toolchain
On 17 January 2011 19:24, Russell King - ARM Linux
li...@arm.linux.org.uk wrote:
Rather than turning off CPU domain switching when the build architecture
includes ARMv6K, thereby causing problems for ARMv6-supporting kernels,
turn it on when it's required to support a CPU architecture.
(sorry,
On 18 January 2011 06:00, Nicolas Pitre n...@fluxnic.net wrote:
On Mon, 17 Jan 2011, Russell King - ARM Linux wrote:
Add additional instructions to our assembly bitops functions to ensure
that they only operate on word-aligned pointers. This will be necessary
when we switch these operations
On 15 January 2011 16:11, Russell King - ARM Linux
li...@arm.linux.org.uk wrote:
SMP requires at least the ARMv6K extensions to be present, so if we're
running on SMP, the WFE and SEV instructions must be available.
However, when we run on UP, the v6K extensions may not be available,
and so
On Mon, 2011-01-17 at 10:37 +, Russell King - ARM Linux wrote:
On Mon, Jan 17, 2011 at 10:15:25AM +, Catalin Marinas wrote:
On 15 January 2011 16:11, Russell King - ARM Linux
li...@arm.linux.org.uk wrote:
SMP requires at least the ARMv6K extensions to be present, so if we're
On 17 January 2011 10:53, Russell King - ARM Linux
li...@arm.linux.org.uk wrote:
On Mon, Jan 17, 2011 at 10:37:39AM +, Russell King - ARM Linux wrote:
3. Do we always need a dsb prior to a sev? Maybe the SPEAR patches need
another review to determine how they're using sev()?
FYI, this is
On 13 December 2010 16:29, Russell King - ARM Linux
li...@arm.linux.org.uk wrote:
On Mon, Dec 13, 2010 at 03:52:20PM +, Catalin Marinas wrote:
On 10 December 2010 17:03, Russell King - ARM Linux
li...@arm.linux.org.uk wrote:
On Fri, Dec 10, 2010 at 12:03:07PM +0100, Janusz Krzysztofik
On 10 December 2010 17:03, Russell King - ARM Linux
li...@arm.linux.org.uk wrote:
On Fri, Dec 10, 2010 at 12:03:07PM +0100, Janusz Krzysztofik wrote:
void __init omap1_camera_init(void *info)
{
struct platform_device *dev = omap1_camera_device;
+ dma_addr_t paddr =
On 5 December 2010 23:04, Russell King - ARM Linux
li...@arm.linux.org.uk wrote:
On Sun, Dec 05, 2010 at 10:18:27PM +, Catalin Marinas wrote:
On 5 December 2010 11:43, Russell King - ARM Linux
li...@arm.linux.org.uk wrote:
diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel
On 6 December 2010 17:35, Dave Martin dave.mar...@linaro.org wrote:
* Explicitly build a few parts of sleep34xx.S as ARM.
* lock_scratchpad_sem is kept as ARM because of the need to
synchronise with hardware (?) using the SWP instruction.
* save_secure_ram_context and
On 5 December 2010 11:34, Russell King - ARM Linux
li...@arm.linux.org.uk wrote:
Provide gic_init() which initializes the GIC distributor and current
CPU's GIC interface for the boot (or single) CPU.
Signed-off-by: Russell King rmk+ker...@arm.linux.org.uk
Reviewed-by: Catalin Marinas
.
Get rid of this argument, and rename to gic_secondary_init().
Signed-off-by: Russell King rmk+ker...@arm.linux.org.uk
Reviewed-by: Catalin Marinas catalin.mari...@arm.com
(minor issue, maybe a comment for gic_secondary_init just in case
anyone things about primary and secondary GICs
-by: Russell King rmk+ker...@arm.linux.org.uk
Reviewed-by: Catalin Marinas catalin.mari...@arm.com
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
On 5 December 2010 11:35, Russell King - ARM Linux
li...@arm.linux.org.uk wrote:
This avoids writing unnecessarily to gic_data[] from other CPUs,
making this a mostly read-only variable.
Signed-off-by: Russell King rmk+ker...@arm.linux.org.uk
Reviewed-by: Catalin Marinas catalin.mari
HAVE_GET_IRQNR_PREAMBLE.
Signed-off-by: Russell King rmk+ker...@arm.linux.org.uk
Reviewed-by: Catalin Marinas catalin.mari...@arm.com
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org
On 5 December 2010 11:43, Russell King - ARM Linux
li...@arm.linux.org.uk wrote:
As our SMP implementation uses MESI protocols. Grouping together data
which is mostly only read together means that we avoid unnecessary
cache line bouncing when this code shares a cache line with other data.
In
On 1 December 2010 00:25, Russell King - ARM Linux
li...@arm.linux.org.uk wrote:
On Tue, Nov 30, 2010 at 11:32:04PM +, Russell King - ARM Linux wrote:
Note that I'll go with factoring this out into arch/arm/kernel/smp_scu.c
for the time being, but I'm not convinced about the other parts
On 30 November 2010 22:16, Russell King - ARM Linux
li...@arm.linux.org.uk wrote:
On Tue, Nov 30, 2010 at 08:31:05PM +0300, Anton Vorontsov wrote:
This greatly reduces amount of platform-specific code, and thus
makes it easier to add local timers for new platforms.
Technically, it's not very
On Thu, 2010-12-02 at 15:24 +, Russell King - ARM Linux wrote:
On Thu, Dec 02, 2010 at 03:19:05PM +, Catalin Marinas wrote:
On 1 December 2010 00:25, Russell King - ARM Linux
li...@arm.linux.org.uk wrote:
On Tue, Nov 30, 2010 at 11:32:04PM +, Russell King - ARM Linux wrote
On Thu, 2010-12-02 at 17:38 +, Russell King - ARM Linux wrote:
On Thu, Dec 02, 2010 at 04:28:40PM +, Catalin Marinas wrote:
The SCU is part of the core TRM, so I don't expect it to be the same
across various MP cores (and A15 is an example).
You may want to consolidate functions
...@ti.com
Cc: Catalin Marinas catalin.mari...@arm.com
Acked-by: Catalin Marinas catalin.mari...@arm.com
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Peter Zijlstra pet...@infradead.org wrote:
On Mon, 2010-10-18 at 14:35 +0100, Russell King - ARM Linux wrote:
In any case, Linux's spinlock API (or more accurately, the ARM exclusive
access instructions) relies upon hardware coherency support (a piece of
hardware called an exclusive monitor)
Peter Zijlstra pet...@infradead.org wrote:
On Mon, 2010-10-18 at 16:27 +0100, Catalin Marinas wrote:
Peter Zijlstra pet...@infradead.org wrote:
On Mon, 2010-10-18 at 14:35 +0100, Russell King - ARM Linux wrote:
In any case, Linux's spinlock API (or more accurately, the ARM exclusive
access
Hi Santosh,
Santosh Shilimkar santosh.shilim...@ti.com wrote:
This patch populates the L1 entries for MT_MEMORY and MT_MEMORY_NONCACHED
types so that at boot-up, we can map memories outside system memory
at page level granularity
Previously the mapping was limiting to section level, which
On Mon, 2010-08-30 at 13:30 -0700, Paul E. McKenney wrote:
On Fri, Aug 27, 2010 at 09:12:24AM +0300, Hiroshi DOYU wrote:
+static struct kmemleak_object *find_and_get_object(unsigned long ptr,
int alias)
+{
+ struct kmemleak_object *object;
+
+ rcu_read_lock();
+ object =
On Tue, 2010-08-10 at 18:49 +0300, Hiroshi DOYU wrote:
Now there's not much difference with the attached patch, a new version
of alias.
/ # modprobe kmemleak-special-test use_alias=0
/ # time echo scan /sys/kernel/debug/kmemleak
real0m 2.30s
user0m 0.00s
sys 0m 2.30s
/ #
I've contributed:
Signed-off-by: Tony Lindgren t...@atomide.com
Anybody else care to ack?
Acked-by: Catalin Marinas catalin.mari...@arm.com
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http
On Wed, 2010-09-08 at 08:34 +0100, Shilimkar, Santosh wrote:
Can you also include the patch by Per Fransson I sent off to
Thomas and the list just a few days ago with the subject
[PATCH] ARM: ux500 specific L2 cache code
in this patch series?
Basically I plan to push all these patches
On Wed, 2010-09-08 at 16:09 +0100, Shilimkar, Santosh wrote:
On Wed, 2010-09-08 at 08:34 +0100, Shilimkar, Santosh wrote:
Can you also include the patch by Per Fransson I sent off to
Thomas and the list just a few days ago with the subject
[PATCH] ARM: ux500 specific L2 cache code
On Wed, 2010-09-08 at 16:46 +0100, Shilimkar, Santosh wrote:
Here is the updated branch including Per Fransson patch.
http://dev.omapzoom.org/?p=santosh/kernel-omap4-base.git;a=shortlog;h=refs/heads/l2x0-pull-rmk
It looks fine to me.
--
Catalin
--
To unsubscribe from this list: send the line
On Thu, 2010-09-02 at 17:16 +0100, Tony Lindgren wrote:
* Russell King - ARM Linux li...@arm.linux.org.uk [100902 06:29]:
On Mon, Aug 30, 2010 at 03:55:27PM -0700, Tony Lindgren wrote:
* Tony Lindgren t...@atomide.com [100820 04:59]:
* Russell King - ARM Linux li...@arm.linux.org.uk
On Sat, 2010-07-31 at 23:14 +0530, Santosh Shilimkar wrote:
Replace tab with space after #define to be consisten with other
define in the file. Also move the bit mask below the register offsets.
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
Cc: Catalin Marinas catalin.mari
On Sat, 2010-07-31 at 23:16 +0530, Santosh Shilimkar wrote:
The cache size is needed for to optimise range based
maintainance operations
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
Cc: Catalin Marinas catalin.mari...@arm.com
Acked-by: Catalin Marinas catalin.mari...@arm.com
santosh.shilim...@ti.com
Cc: Catalin Marinas catalin.mari...@arm.com
---
arch/arm/mm/cache-l2x0.c | 95
--
1 files changed, 58 insertions(+), 37 deletions(-)
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index b2938d4..c0d6108
Russell,
I can see you posted another version while writing this e-mail. But I
think most comments still apply.
On Fri, 2010-09-03 at 10:10 +0100, Russell King - ARM Linux wrote:
diff --git a/arch/arm/include/asm/assembler.h
b/arch/arm/include/asm/assembler.h
index 6e8f05c..55974d2 100644
Russell,
On Mon, 2010-09-06 at 11:44 +0100, Russell King - ARM Linux wrote:
+#ifdef CONFIG_SMP_ON_UP
+__fixup_smp:
+ mov r7, #0x0007
+ orr r6, r7, #0xff00 @ mask 0xff07
+ orr r7, r7, #0x4100 @ val 0x4107
+ and r0, r9, r6
+
On Mon, 2010-09-06 at 16:34 +0100, Russell King - ARM Linux wrote:
On Mon, Sep 06, 2010 at 12:46:34PM +0100, Catalin Marinas wrote:
Would this work with Thumb-2 kernel builds? Maybe you can add a W(instr)
in the SMP/UP macros to make sure that the instruction is always 32-bit
wide
On Mon, 2010-09-06 at 17:36 +0100, Russell King - ARM Linux wrote:
On Mon, Sep 06, 2010 at 04:53:47PM +0100, Catalin Marinas wrote:
On Mon, 2010-09-06 at 16:34 +0100, Russell King - ARM Linux wrote:
On Mon, Sep 06, 2010 at 12:46:34PM +0100, Catalin Marinas wrote:
Would this work
Hi,
(and sorry for the delay)
On Fri, 2010-06-18 at 07:04 +0100, Hiroshi DOYU wrote:
This is another version of kmemleak: Fix false positive, which
introduces another alias tree to keep track of all alias address of
each objects, based on the discussion(*1)
You can also find the previous
.
Otherwise VFPFMRX and VFPFMXR access fails and we get:
Internal error: Oops - undefined instruction: 0 [#1]
PC is at no_old_VFP_process+0x8/0x3c
LR is at __und_svc+0x48/0x80
...
Signed-off-by: Tony Lindgren t...@atomide.com
The new version looks fine to me.
Acked-by: Catalin Marinas
On Mon, 2010-06-21 at 14:51 +0100, Tony Lindgren wrote:
diff --git a/arch/arm/vfp/vfpmodule.c b/arch/arm/vfp/vfpmodule.c
index 315a540..19ba626 100644
--- a/arch/arm/vfp/vfpmodule.c
+++ b/arch/arm/vfp/vfpmodule.c
@@ -549,10 +549,14 @@ static int __init vfp_init(void)
/*
Hi,
Sorry for the delay, I eventually got the time to look at your patches.
On Tue, 2010-06-01 at 11:25 +0100, Hiroshi DOYU wrote:
There is a false positive case that a pointer is calculated by other
methods than the usual container_of macro. kmemleak_ignore can cover
such a false positive,
On Wed, 2010-06-02 at 12:34 +0100, Hiroshi DOYU wrote:
From: ext Catalin Marinas catalin.mari...@arm.com
Can we not add a new prio tree (or just use the existing one) for
pointer aliases? The advantage is that you only have a single function
to call, something like kmemleak_add_alias
@vger.kernel.org;
Catalin Marinas
Subject: Re: [PATCH v2] ARMv7: Use the Inner Shareable I-cache on MP
Santosh Shilimkar santosh.shilim...@ti.com wrote:
This patch fixes the flush_cache_all for ARMv7 SMP. It was
missing from commit b8349b569aae661dea9d59d7d2ee587ccea3336c
Signed
On Wed, 2010-03-17 at 19:11 +, Tony Lindgren wrote:
* Catalin Marinas catalin.mari...@arm.com [100317 11:04]:
On Wed, 2010-03-17 at 17:57 +, Tony Lindgren wrote:
Here's an updated version of this patch with more details.
Looks like VFPv3 is only available on V7:
http
On Wed, 2010-03-17 at 17:57 +, Tony Lindgren wrote:
Here's an updated version of this patch with more details.
Looks like VFPv3 is only available on V7:
http://www.arm.com/products/processors/technologies/vector-floating-point.php
But does it cause any problem if the feature is enabled
of Catalin's below series
- [PATCH v3 0/4] ARM mandatory barriers
- http://permalink.gmane.org/gmane.linux.ports.arm.kernel/75425
CC: Catalin Marinas catalin.mari...@arm.com
CC: Tony Lindgren t...@atomide.com
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
If Russell's ok
On Thu, 2010-01-28 at 18:33 +, Jamie Lokier wrote:
Catalin Marinas wrote:
Hmm, but then we can't compile in SMP for single core systems and
keep it bootable on single core v6?
Not with the current kernel since it hardcodes the shareability bit in
the page tables and the LDREX
On Thu, 2010-01-28 at 17:47 +, Tony Lindgren wrote:
* Catalin Marinas catalin.mari...@arm.com [100128 02:58]:
On Tue, 2010-01-26 at 19:37 +, Tony Lindgren wrote:
Otherwise the kernel built with both CPU_V6 and CPU_V7 will not
boot on omap2.
Signed-off-by: Tony Lindgren t
On Fri, 2010-01-29 at 11:46 +, Santosh Shilimkar wrote:
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -28,6 +28,7 @@
#include plat/control.h
#include plat/timer-gp.h
#include asm/hardware/gic.h
+#include asm/hardware/cache-l2x0.h
static
On Tue, 2010-01-26 at 19:37 +, Tony Lindgren wrote:
Otherwise the kernel built with both CPU_V6 and CPU_V7 will not
boot on omap2.
Signed-off-by: Tony Lindgren t...@atomide.com
---
arch/arm/mm/Kconfig |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git
1 - 100 of 112 matches
Mail list logo
