Shifting thread to linux-omap mailing list.
Regards,
Nishanth Menon
From: pandabo...@googlegroups.com [pandabo...@googlegroups.com] on behalf of
Sukumar Ghorai [ghorai.suku...@gmail.com]
Sent: Friday, December 21, 2012 10:33
To: pandabo...@googlegroups.com
On Fri, Jun 15, 2012 at 6:28 AM, Jean Pihet jean.pi...@newoldbits.com wrote:
1. The while loops need optimization. - This can definitely be
simplified and made non-risky; this also needs some more error
handling
If you are interested using something like the following
static int
Minor nitpick:
On Mon, Jun 11, 2012 at 10:26 AM, Tero Kristo t-kri...@ti.com wrote:
+/**
+ * _omap4_get_context_lost - get context loss counter for a hwmod
Documentation missing for oh
btw, you might be interested in using http://www.omappedia.org/wiki/Kmake
to provide list of kerneldoc errors
On Thu, Jun 14, 2012 at 10:05 AM, Jean Pihet jean.pi...@newoldbits.com wrote:
Minor comment follows:
[...]
+/**
+ * _pwrdm_wakeuplat_update_pwrst - Update power domain power state if needed
+ * @pwrdm: struct powerdomain * to which requesting device belongs to.
+ * @min_latency: the allowed
On Wed, Jun 20, 2012 at 5:41 AM, Rajendra Nayak rna...@ti.com wrote:
+ /* Look for the platform device for the constraint target device
*/
+ pdev = to_platform_device(dev_pm_qos_req-dev);
+
+ /* Try to catch non platform devices */
+ if (pdev-name == NULL) {
Is
On Thu, Jul 19, 2012 at 4:49 AM, Tero Kristo t-kri...@ti.com wrote:
Zero doesn't mean no context loss. If counter was previous MAX_INT, if
it goes to zero it is still a context loss, as the counter value
differs. Drivers do check against diff in the context loss counter, and
if there is one,
On Thu, Jun 14, 2012 at 10:05 AM, Jean Pihet jean.pi...@newoldbits.com
wrote:
+static int _pwrdm_wakeuplat_update_pwrst(struct powerdomain *pwrdm,
+long min_latency)
+{
+ int ret = 0, state, new_state = PWRDM_FUNC_PWRST_ON;
+
+ if
On Wed, Jul 18, 2012 at 4:15 AM, Tero Kristo t-kri...@ti.com wrote:
On Tue, 2012-07-17 at 02:59 -0500, Menon, Nishanth wrote:
Couple of minor comments:
On Mon, Jun 11, 2012 at 10:26 AM, Tero Kristo t-kri...@ti.com wrote:
[...]
/**
+ * _omap4_update_context_lost - increment hwmod
Couple of minor comments:
On Mon, Jun 11, 2012 at 10:26 AM, Tero Kristo t-kri...@ti.com wrote:
[...]
/**
+ * _omap4_update_context_lost - increment hwmod context loss counter if
+ * hwmod context was lost, and clear hardware context loss reg
+ * @oh: hwmod to check for context loss
+ *
+ *
On Mon, Jun 11, 2012 at 10:26 AM, Tero Kristo t-kri...@ti.com wrote:
On OMAP4 most modules/hwmods support module level context status. On
OMAP3 and earlier, we relied on the power domain level context status.
Identify all modules that don't support 'context_offs' by marking the
offset as
On Fri, Jul 13, 2012 at 2:07 AM, Jean Pihet jean.pi...@newoldbits.com wrote:
my Crib about the above apis are lack of logic power state handling :(
which forces code like cpuidle to use different apis for logic
power state and force them to use these apis just for pwrst.
Please look at the
On Fri, Jul 13, 2012 at 2:18 AM, Jean Pihet jean.pi...@newoldbits.com wrote:
[..]
Santosh pointed me to the thread offline. This is indeed a much better
approach IMHO than having 3 conflicting options inside powerdomain
framework.
After looking at the code and having sent my comments, I like
On Thursday 05 July 2012, Rajendra Nayak wrote:
[..]
From 5f5e4eb342110286bf719c7d9d7c1959f53e34f9 Mon Sep 17 00:00:00 2001
From: Rajendra Nayak rna...@ti.com
Date: Thu, 5 Jul 2012 17:33:28 +0530
Subject: [RFC] ARM: OMAP: Powerdomain: control memory and logic bits
internally
Powerdomain
On Fri, Jul 13, 2012 at 3:38 AM, Peter Ujfalusi peter.ujfal...@ti.com wrote:
On OMAP4 the i2c1 bus is dedicated for the PMIC and audio related devices.
Manufacturers can opt to use different codec than twl6040 and also can add
audio related IC to the bus (external amplifier for example on
On Fri, Jul 13, 2012 at 12:26 AM, Rajendra Nayak rna...@ti.com wrote:
On Friday 13 July 2012 08:31 AM, Menon, Nishanth wrote:
my Crib about the above apis are lack of logic power state handling:(
which forces code like cpuidle to use different apis for logic
power state and force them to use
On Fri, Jun 1, 2012 at 2:03 AM, Igor Grinberg grinb...@compulab.co.il wrote:
On 06/01/12 02:15, Kevin Hilman wrote:
Nishanth Menon n...@ti.com writes:
Commit 9fa2df6b90786301b175e264f5fa9846aba81a65
(ARM: OMAP2+: OPP: allow OPP enumeration to continue if device is not
present)
makes the
On Wed, Apr 25, 2012 at 2:17 AM, Govindraj.R govindraj.r...@ti.com wrote:
[...]
--- a/arch/arm/mach-omap2/prm2xxx_3xxx.h
+++ b/arch/arm/mach-omap2/prm2xxx_3xxx.h
@@ -289,6 +289,13 @@ static inline int omap2_prm_deassert_hardreset(s16
prm_mod, u8 rst_shift,
not suppose to be
On Thu, May 31, 2012 at 8:28 AM, Tero Kristo t-kri...@ti.com wrote:
minor comment:
+void pwrdm_clkdm_enable(struct powerdomain *pwrdm)
snip
+void pwrdm_clkdm_disable(struct powerdomain *pwrdm)
I know the understand that rest of the code lacks kernel-doc, but at
least can we ensure that the new
On Thu, May 31, 2012 at 8:55 AM, Tero Kristo t-kri...@ti.com wrote:
+ case PWRDM_POWER_RET:
Apologies on hijacking this thread, but I do think we need to revisit
this series after rebase
on top of Jean's series - it otherwise results a mess of different
sets of macros.
IMHO though, it
Regards,
Nishanth Menon
On Fri, Jun 1, 2012 at 4:03 PM, Kevin Hilman khil...@ti.com wrote:
Nishanth Menon n...@ti.com writes:
From: Wenbiao Wang ww...@ti.com
Voltage Processor state machine transition to disable need to
occur from IDLE state. When we transition OPP in a functioning
On Wed, May 30, 2012 at 3:32 AM, Tero Kristo t-kri...@ti.com wrote:
On Tue, 2012-05-29 at 15:10 -0500, Menon, Nishanth wrote:
On Mon, May 14, 2012 at 5:18 AM, Tero Kristo t-kri...@ti.com wrote:
Added similar PM errata flag support as omap3 has. A few errata flags
will be added in subsequent
On Mon, May 21, 2012 at 5:40 AM, Shilimkar, Santosh
santosh.shilim...@ti.com wrote:
Not sure what you mean wakeup issue on GP device.
IIUC, the issue is:
Wakeup from device OFF, hardware releases the reset for both CPUs,
This is special case and applicable only for device OFF. The reason
On Wed, May 30, 2012 at 12:59 PM, Kevin Hilman khil...@ti.com wrote:
Menon, Nishanth n...@ti.com writes:
On Thu, May 17, 2012 at 3:52 AM, Shilimkar, Santosh
santosh.shilim...@ti.com wrote:
On Thu, May 17, 2012 at 12:34 PM, Shilimkar, Santosh
santosh.shilim...@ti.com wrote:
On Thu, May 17
On Mon, May 14, 2012 at 5:18 AM, Tero Kristo t-kri...@ti.com wrote:
Currently device off does not have any counters / timers of its own
and it is impossible to track the time spent in this state. In device
off, MPU / CORE powerdomains enter OSWR, so normally the RETENTION
state times / counts
On Mon, May 14, 2012 at 5:03 AM, Tero Kristo t-kri...@ti.com wrote:
[...]
+/**
* _enable - enable an omap_hwmod
* @oh: struct omap_hwmod *
*
@@ -1599,6 +1629,8 @@ static int _enable(struct omap_hwmod *oh)
_enable_clocks(oh);
_enable_module(oh);
+
On Thu, May 17, 2012 at 3:52 AM, Shilimkar, Santosh
santosh.shilim...@ti.com wrote:
On Thu, May 17, 2012 at 12:34 PM, Shilimkar, Santosh
santosh.shilim...@ti.com wrote:
On Thu, May 17, 2012 at 4:12 AM, Kevin Hilman khil...@ti.com wrote:
Tero Kristo t-kri...@ti.com writes:
[...]
- Rather than
On Mon, May 14, 2012 at 5:18 AM, Tero Kristo t-kri...@ti.com wrote:
Added similar PM errata flag support as omap3 has. A few errata flags
will be added in subsequent patches.
Considering that we might have erratas for future SoCs as well,
should'nt we just
set up a common errata flag for all
On Tue, May 29, 2012 at 3:15 PM, Kevin Hilman khil...@ti.com wrote:
Tero Kristo t-kri...@ti.com writes:
On Wed, 2012-05-16 at 17:06 -0700, Kevin Hilman wrote:
+Benoit
Tero Kristo t-kri...@ti.com writes:
save_secure_all needs l3_main_3_ick and l4_secure_clkdm enabled,
otherwise the
On Thu, May 24, 2012 at 2:49 AM, Paul Walmsley p...@pwsan.com wrote:
Hi Nishanth
On Fri, 18 May 2012, Nishanth Menon wrote:
From: Vikram Pandita vikram.pand...@ti.com
If the dpll is already locked, code can be optimized
to return much earlier than doing redundent set of lock mode
and wait
On Thu, May 24, 2012 at 9:57 AM, Paul Walmsley p...@pwsan.com wrote:
Okay. As I understand it, the maintainers above me would like
Signed-off-by:s from the entire submission patch, even if there are no
contributions to the patch itself. So please let me know if it's okay for
me to add your
On Wed, May 9, 2012 at 1:29 PM, Kevin Hilman khil...@ti.com wrote:
Woodruff, Richard r-woodru...@ti.com writes:
From: Hilman, Kevin
Sent: Tuesday, May 08, 2012 5:17 PM
A basic OMAP AVS driver has been in mainline for a long time, yet we
have not seen support submitted for all of these
Sat, May 19, 2012 at 4:52 AM, Eduardo Valentin eduardo.valen...@ti.com
wrote:
I guess it is time to properly document this increasing busy loop delay..
As it is getting closer to ms scale..
Does the following sound good?
/* Maximum time for Voltage Processor to enter or exit idle */
Regards,
On Mon, May 21, 2012 at 9:51 AM, Eduardo Valentin
eduardo.valen...@ti.com wrote:
On Mon, May 21, 2012 at 08:36:35AM -0500, ext Nishanth Menon wrote:
Sat, May 19, 2012 at 4:52 AM, Eduardo Valentin eduardo.valen...@ti.com
wrote:
I guess it is time to properly document this increasing
On Mon, May 7, 2012 at 2:38 AM, Tero Kristo t-kri...@ti.com wrote:
One more point to consider is that with this - we *should* disable
VCORE3 and VMEM else we can have weird behavior such as those seen
by pandaboard-ES early adopters.
In what case are we seeing such? If the regulators should
On Wed, May 2, 2012 at 6:40 AM, Bedia, Vaibhav vaibhav.be...@ti.com wrote:
On Wed, May 02, 2012 at 16:30:26, Shilimkar, Santosh wrote:
[...]
How ?
SRAM is sower memory than DDR so I don't see how it
will reduce latency.
I am just guessing if that's indeed the case ;)
On Fri, Apr 6, 2012 at 14:19, Andrew Morton a...@linux-foundation.org wrote:
I rewrote your acked-by to Signed-off-by, because you were on the
delivery path of the patch. Documentation/SubmittingPatches has details.
Is this OK?
sure, thanks.
Regards,
Nishanth Menon
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Kevin,
[...]
Nishanth, can you collect the acks/tested-bys and repost and official
patch.
I'll queue this up.
Thanks. This is already done:
http://marc.info/?l=linux-omapm=133191481703750w=2
Regards,
Nishanth Menon
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On Fri, Mar 16, 2012 at 10:47, Maximilian Schwerin
maximilian.schwe...@tigris.de wrote:
sorry my fault! This was not what I was thinking of as generic. Works as
expected!
Can i take it as an acked-by?
Regards,
Nishanth Menon
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On Wed, Mar 14, 2012 at 16:15, Kevin Hilman khil...@ti.com wrote:
Maximilian Schwerin m...@tigris.de writes:
From: Steve Sakoman st...@sakoman.com
Don't try to add IVA OPPs for OMAP3 versions not containing an IVA
subsystem, as this would make omap_init_opp_table fail.
Signed-off-by: Steve
On Tue, Mar 13, 2012 at 05:26, jean.pi...@newoldbits.com wrote:
diff --git a/arch/arm/mach-omap2/smartreflex.c
b/arch/arm/mach-omap2/smartreflex.c
index 7977018..dfe8075 100644
--- a/arch/arm/mach-omap2/smartreflex.c
+++ b/arch/arm/mach-omap2/smartreflex.c
...
+ switch (sr-ip_type) {
On Tue, Mar 6, 2012 at 12:36, Shilimkar, Santosh
santosh.shilim...@ti.com wrote:
Change-Id: I0ee22e60555e1cfd6cc3dea7ee44d0584ce182b6
You don't need above gerrit change id in commit message.
yow.. thanks for catching it, my bad.. thought i fixed it..
Regards,
Nishanth Menon
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On Wed, Feb 29, 2012 at 22:23, Paul Walmsley p...@pwsan.com wrote:
b/arch/arm/mach-omap2/powerdomain.c
index 8a18d1b..89000d3 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -339,8 +339,8 @@ int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct
On Thu, Feb 23, 2012 at 03:08, Tero Kristo t-kri...@ti.com wrote:
On Wed, 2012-02-22 at 19:37 -0600, Menon, Nishanth wrote:
On Tue, Feb 21, 2012 at 08:04, Tero Kristo t-kri...@ti.com wrote:
[...]
diff --git a/arch/arm/mach-omap2/voltage.h b/arch/arm/mach-omap2/voltage.h
index 949938d
On Tue, Feb 21, 2012 at 08:04, Tero Kristo t-kri...@ti.com wrote:
[...]
diff --git a/arch/arm/mach-omap2/voltage.h b/arch/arm/mach-omap2/voltage.h
index 949938d..940a0d6 100644
--- a/arch/arm/mach-omap2/voltage.h
+++ b/arch/arm/mach-omap2/voltage.h
[...]
@@ -171,6 +169,18 @@ struct
On Tue, Feb 21, 2012 at 08:04, Tero Kristo t-kri...@ti.com wrote:
These are now called vddmin and vddmax, as these fields will be used
globally for selecting voltage ranges for a pmic channel, and not
only for voltage processor.
NAK. I think we need to setup voltage for SoC limits as well. the
On Tue, Feb 21, 2012 at 08:04, Tero Kristo t-kri...@ti.com wrote:
This contains startup and shutdown times for the oscillator. By default
use ULONG_MAX. Oscillator setup is used for calculating and setting up
latencies for sleep modes that disable oscillator.
Signed-off-by: Tero Kristo
Regards,
Nishanth Menon
On Fri, Feb 17, 2012 at 05:06, Tero Kristo t-kri...@ti.com wrote:
On Thu, 2012-02-16 at 12:23 -0600, Menon, Nishanth wrote:
On Thu, Feb 16, 2012 at 04:27, Tero Kristo t-kri...@ti.com wrote:
VDD1 and VDD2 are the core voltage regulators on OMAP3. VDD1 is used
On Wed, Feb 15, 2012 at 09:20, Kevin Hilman khil...@ti.com wrote:
Tero Kristo t-kri...@ti.com writes:
On Tue, 2012-02-14 at 15:52 -0800, Tony Lindgren wrote:
* Kevin Hilman khil...@ti.com [120214 14:28]:
Tony Lindgren t...@atomide.com writes:
* Tero Kristo t-kri...@ti.com [120214
On Thu, Feb 16, 2012 at 11:35, Kevin Hilman khil...@ti.com wrote:
IMO, the one thing we're still missing is the ability to take register
snapshots (like immediately before and after WFI) and somehow feed those
to omapconf for deciphering.
Something like this perhaps?
On Thu, Feb 16, 2012 at 04:27, Tero Kristo t-kri...@ti.com wrote:
VDD1 and VDD2 are the core voltage regulators on OMAP3. VDD1 is used
to control MPU/IVA voltage, and VDD2 is used for CORE. These regulators
are needed by DVFS.
Voltage ranges for VDD1 and VDD2 are taken from twl4030/twl5030
On Thu, Feb 9, 2012 at 23:58, Shubhrajyoti D shubhrajy...@ti.com wrote:
Currently the memory region is not released the folowing error is
observed.
/testsuites # insmod omap-serial.ko
[ 130.746917] omap_uart omap_uart.0: memory region already claimed
[ 130.753143] omap_uart: probe of
On Wed, Jan 25, 2012 at 12:49, Kevin Hilman khil...@ti.com wrote:
Cousson, Benoit b-cous...@ti.com writes:
On 1/25/2012 7:13 PM, Jean Pihet wrote:
[...]
I guess that path #3 and #5 should just be removed.
I am ok with both options (keeping or removing the 2 commits), please
let me know
On Wed, Nov 30, 2011 at 03:45, Tero Kristo t-kri...@ti.com wrote:
On Tue, 2011-11-29 at 12:30 -0600, Menon, Nishanth wrote:
On Fri, Nov 25, 2011 at 09:49, Tero Kristo t-kri...@ti.com wrote:
Both startup and shutdown take 500us at maximum, value taken from
TWL6030 data manual.
Might
On Wed, Nov 30, 2011 at 04:07, Tero Kristo t-kri...@ti.com wrote:
On Tue, 2011-11-29 at 12:26 -0600, Menon, Nishanth wrote:
On Fri, Nov 25, 2011 at 09:49, Tero Kristo t-kri...@ti.com wrote:
more snip
diff --git a/arch/arm/mach-omap2/opp3xxx_data.c
b/arch/arm/mach-omap2/opp3xxx_data.c
On Fri, Nov 25, 2011 at 09:49, Tero Kristo t-kri...@ti.com wrote:
Introduced two new voltage domain specific parameter structures,
omap_vp_param and omap_vc_param. These are used to describe the minimum
and maximum voltages for the voltagedomains, and also the sleep voltage
levels. Existing
On Fri, Nov 25, 2011 at 09:49, Tero Kristo t-kri...@ti.com wrote:
Both startup and shutdown take 500us at maximum, value taken from
TWL6030 data manual.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/mach-omap2/omap_twl.c | 2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
On Fri, Nov 25, 2011 at 09:49, Tero Kristo t-kri...@ti.com wrote:
Now we select the vddmin and vddmax values based on both pmic and
voltage processor data, this allows usage of different power ICs.
Signed-off-by: Tero Kristo t-kri...@ti.com
Acked-by: Nishanth Menon n...@ti.com
Regards,
On Wed, Nov 16, 2011 at 18:02, Kevin Hilman khil...@ti.com wrote:
Felipe Balbi ba...@ti.com writes:
From: Nishanth Menon n...@ti.com
SmartReflex should be disabled while entering low power mode due to
the following reasons:
[...]
Nishanth, in the end, didn't you decide to drop this patch?
On Thu, Sep 1, 2011 at 06:48, Cousson, Benoit b-cous...@ti.com wrote:
Nishanth,
Do you have any objection to replace that API with omap_hwmod_name_get_pdev?
None.
Regards,
Nishanth Menon
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On Fri, Aug 12, 2011 at 16:30, Todd Poynor toddpoy...@google.com wrote:
On Fri, Aug 12, 2011 at 12:20:21PM +0530, Munegowda, Keshava wrote:
On Wed, Aug 10, 2011 at 10:01 PM, Todd Poynor toddpoy...@google.com wrote:
@@ -913,12 +598,15 @@ static int usbhs_enable(struct device *dev)
here is my quick feedback:
On Wed, Aug 3, 2011 at 10:29, Tero Kristo t-kri...@ti.com wrote:
This patch separates board specific voltage and oscillator ramp / setup
times from the core code. Things changed:
- on/sleep/ret/off voltage setup moved from common twl code to
VC / VP data
On Fri, Jul 1, 2011 at 21:30, Rajendra Nayak rna...@ti.com wrote:
[...]
+static void __init omap4_check_features(void)
+{
+ u32 si_type;
+
+ if (cpu_is_omap443x())
+ omap_features |= OMAP4_HAS_MPU_1GHZ;
+
+
+ if (cpu_is_omap446x()) {
+
On Fri, Jul 29, 2011 at 09:05, Felipe Balbi ba...@ti.com wrote:
+}
+EXPORT_SYMBOL(omap_hwmod_name_get_odev);
maybe EXPORT_SYMBOL_GPL() ?? Not sure we want non-GPL code to access
this ;-)
Sure.. but is this the way we want to go? if yes, I can post the
series in a formal way to the list.
On Thu, Jul 28, 2011 at 07:57, Cousson, Benoit b-cous...@ti.com wrote:
[...]
diff --git a/arch/arm/mach-omap2/omap_hwmod.c
b/arch/arm/mach-omap2/omap_hwmod.c
index 293fa6c..77d01a2 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -142,6 +142,7 @@
On Mon, Jul 25, 2011 at 03:42, Felipe Balbi ba...@ti.com wrote:
Hi,
On Sun, Jul 24, 2011 at 11:52:37AM -0500, Nishanth Menon wrote:
SmartReflex should be disabled while entering low power mode due to
the following reasons:
a) SmartReflex values are not defined for retention voltage.
b) With
On Mon, Jul 25, 2011 at 12:13, Felipe Balbi ba...@ti.com wrote:
[..]
while at that, SR's IRQ is never freed on exit path, could fix it while
you're already there ?
This is not really related to this patch is it? IMHO IRQ handling is
I didn't say to put it on the same patch ;-) I meant that
On Fri, Jul 22, 2011 at 04:13, Felipe Balbi ba...@ti.com wrote:
Hi,
On Fri, Jul 22, 2011 at 12:55:53AM -0500, Nishanth Menon wrote:
Suspend and Resume paths are safe enough to do it in
the standard LDM suspend/resume handlers where one can
sleep. Add suspend/resume handlers for SmartReflex.
On Tue, Jul 5, 2011 at 17:01, Kevin Hilman khil...@ti.com wrote:
Shubhrajyoti D shubhrajy...@ti.com writes:
Currently the fifo depth is set to zero for OMAP4 which disables
the FIFO usage. This patch enables the FIFO usage for I2C transactions
on OMAP4 also.
Tested on omap4430 and
On Sat, Jul 2, 2011 at 07:20, Vishwanath BS vishwanath...@ti.com wrote:
Add OMAP4460 OPP definitions for voltage and frequencies based on
OMAP4460 ES1.0 DM Operating Condition Addendum Version 0.1
The following exceptions are present:
* Smartreflex support is still on experimental mode: the
On Thu, Jun 16, 2011 at 15:45, Kevin Hilman khil...@ti.com wrote:
Nice!
A reference to where these voltages values came from would be good to
have in the code as well.
these are just conversions of the existing values - :( I think we need
a seperate patch updating from each of OMAP DMs..
On Thu, Jun 16, 2011 at 15:47, Kevin Hilman khil...@ti.com wrote:
Nishanth Menon n...@ti.com writes:
OPP functions as described in Documentation/power/opp.txt
should be accessed under rcu_locks.
Signed-off-by: Nishanth Menon n...@ti.com
This looks like a fix needed in mainline.
Please
On Tue, Jun 14, 2011 at 08:03, Santosh Shilimkar
santosh.shilim...@ti.com wrote:
With RCU debug options enabled, below warning is observed.
===
[ INFO: suspicious rcu_dereference_check() usage. ]
On Mon, Jun 13, 2011 at 22:24, Stephen Boyd sb...@codeaurora.org wrote:
On 06/10/2011 03:19 PM, Menon, Nishanth wrote:
On Thu, May 12, 2011 at 01:42, Santosh Shilimkar
santosh.shilim...@ti.com wrote:
It's a well known problem if the udelay() is based of global lpj.
You can read more here [1
On Fri, Jun 10, 2011 at 11:08, Premi, Sanjeev pr...@ti.com wrote:
-Original Message-
From: linux-omap-ow...@vger.kernel.org
[mailto:linux-omap-ow...@vger.kernel.org] On Behalf Of Menon, Nishanth
Sent: Friday, June 10, 2011 8:45 PM
To: linux-omap
Cc: Tony; linux-arm; Balbi, Felipe
On Thu, May 12, 2011 at 01:42, Santosh Shilimkar
santosh.shilim...@ti.com wrote:
On 5/5/2011 12:23 PM, Saquib wrote:
Can anyone please help me to understand and fix this issue?
When CPU frequency is 1008MHz, duration of delay was close to
theoretical value, however, when 300MHz, it was close
On Wed, Jun 8, 2011 at 13:51, Kevin Hilman khil...@ti.com wrote:
[..]
the issue is as follows:
currently we dont do voltage transitions. when we do that
eventually(and my current code has an forked implementation of dvfs,
the following steps happen):
late_initcall(omap2_common_pm_late_init);
On Tue, Jun 7, 2011 at 03:15, Santosh Shilimkar
santosh.shilim...@ti.com wrote:
On 6/7/2011 7:35 AM, Nishanth Menon wrote:
Since we do module_init, cpufreq initializes before power late_init
where many of the required data structures are registered. Move
cpufreq init to late_initcall instead.
On Tue, Jun 7, 2011 at 16:49, Kevin Hilman khil...@ti.com wrote:
Nishanth Menon n...@ti.com writes:
Since we do module_init, cpufreq initializes before power late_init
where many of the required data structures are registered.
What exactly are the dependencies here? The only thing I see is
On Tue, Jun 7, 2011 at 20:12, Colin Cross ccr...@google.com wrote:
Bootloaders should in theory setup a frequency which is enabled in
OPP table. However, there can be mismatches, and we should try
both going lower in addition to the going higher to find
a match if bootloader boots up at a OPP
On Tue, Jun 7, 2011 at 20:41, Menon, Nishanth n...@ti.com wrote:
On Tue, Jun 7, 2011 at 20:12, Colin Cross ccr...@google.com wrote:
Bootloaders should in theory setup a frequency which is enabled in
OPP table. However, there can be mismatches, and we should try
both going lower in addition
On Fri, Jun 3, 2011 at 07:16, Santosh Shilimkar
santosh.shilim...@ti.com wrote:
Current OMAP2PLUS CPUfreq tagret() functions returns when all
the CPU's are not online. This breaks CPUfreq when secondary CPUs
are offlined on SMP system.
The intention of that check was just avoid CPU frequency
On Thu, Jun 2, 2011 at 17:45, Kevin Hilman khil...@ti.com wrote:
Nishanth Menon n...@ti.com writes:
OMAP2 is the only family using clk_[init|exit]_cpufreq_table, however,
the cpufreq code has does not use clk_init_cpufreq_table. As a result,
it is unusuable for OMAP2 and only usable only on
On Thu, Jun 2, 2011 at 18:45, Kevin Hilman khil...@ti.com wrote:
Nishanth Menon n...@ti.com writes:
Due to a TRM bug, the current code assumes that channel0(core) is the default
channel. With the additional explanation provided by the hardware team, it is
clear that PRM_VC_CFG_CHANNEL
On Thu, Jun 2, 2011 at 19:10, Kevin Hilman khil...@ti.com wrote:
Menon, Nishanth n...@ti.com writes:
On Thu, Jun 2, 2011 at 18:45, Kevin Hilman khil...@ti.com wrote:
Nishanth Menon n...@ti.com writes:
Due to a TRM bug, the current code assumes that channel0(core) is the
default
channel
On Thu, Jun 2, 2011 at 09:51, Santosh Shilimkar
santosh.shilim...@ti.com wrote:
Current OMAP2PLUS CPUfreq tagret() functions returns when all
the CPU's are not online. This will break DVFS when secondary
CPUs are offlined.
The intention of that check was just avoid CPU frequency change
On Mon, May 30, 2011 at 08:44, Santosh Shilimkar
santosh.shilim...@ti.com wrote:
On 5/30/2011 7:06 PM, Sergei Shtylyov wrote:
Hello.
Santosh Shilimkar wrote:
The commit '99aa18278e' removed the boot messege for OMAP3. Do the same
Please specify that commit's summary in parens -- for the
On Fri, May 27, 2011 at 14:38, Kevin Hilman khil...@ti.com wrote:
Cousson, Benoit b-cous...@ti.com writes:
[...]
In general we do not want to reset nor idle an IP that was potentially
already properly configured by bootloader or early Linux boot code.
Actually, the opposite is true.
On Thu, May 26, 2011 at 22:06, Santosh Shilimkar
santosh.shilim...@ti.com wrote:
On 5/26/2011 11:40 PM, Kevin Hilman wrote:
So here's a dumb question, being rather ignorant of CPUfreq on SMP.
Should we be running a CPUfreq instance on both CPUs when they cannot be
scaled independently?
On Thu, May 26, 2011 at 10:11, Kevin Hilman khil...@ti.com wrote:
When you're talking about potentially concurrent modification of data,
that make sense. Here you're implementing a plugin for an existing
framework, and you can (and have to) make assumptions about when the
callbacks are used.
On Thu, May 26, 2011 at 10:38, Kevin Hilman khil...@ti.com wrote:
I'd prefer to see this even cleaner by dropping the clk_* versions all
together. Then, for those who want OMAP2 support (currently not working
or validated anyways), all that's needed is to add a function simlilar
to
On Thu, May 26, 2011 at 11:10, Kevin Hilman khil...@ti.com wrote:
So here's a dumb question, being rather ignorant of CPUfreq on SMP.
Should we be running a CPUfreq instance on both CPUs when they cannot be
scaled independently?
What is being scaled here is actually the cluster (the MPU SS
On Thu, May 26, 2011 at 11:35, Menon, Nishanth n...@ti.com wrote:
On Thu, May 26, 2011 at 10:38, Kevin Hilman khil...@ti.com wrote:
I'd prefer to see this even cleaner by dropping the clk_* versions all
together. Then, for those who want OMAP2 support (currently not working
or validated
On Thu, May 26, 2011 at 16:15, Kevin Hilman khil...@ti.com wrote:
Nishanth Menon n...@ti.com writes:
On 14:03-20110526, Premi, Sanjeev wrote:
-Original Message-
From: linux-omap-ow...@vger.kernel.org
[mailto:linux-omap-ow...@vger.kernel.org] On Behalf Of Menon, Nishanth
Sent
On Thu, May 26, 2011 at 16:24, Kevin Hilman khil...@ti.com wrote:
Nishanth Menon n...@ti.com writes:
From: Moiz Sonasath m-sonas...@ti.com
For OMAP4460, GPIO-7 of bank1 is used for controling
the TPS modes, hence GPIO1 should not be reset
during init as reset will cause the TPS voltage to
On Tue, May 24, 2011 at 17:01, Kevin Hilman khil...@ti.com wrote:
Menon, Nishanth n...@ti.com writes:
On Thu, May 19, 2011 at 08:12, Kevin Hilman khil...@ti.com wrote:
Nishanth Menon n...@ti.com writes:
OMAP2 does not use OPP tables at the moment for DVFS. Currently,
we depend on opp table
On Wed, May 25, 2011 at 11:17, Kevin Hilman khil...@ti.com wrote:
Menon, Nishanth n...@ti.com writes:
On Wed, May 18, 2011 at 03:53, Kevin Hilman khil...@ti.com wrote:
Nishanth Menon n...@ti.com writes:
Patch OMAP2+: voltage: split voltage controller (VC) code into dedicated
layer
splits
On Wed, May 25, 2011 at 17:16, Kevin Hilman khil...@ti.com wrote:
Nishanth Menon n...@ti.com writes:
Since we have multiple CPUs, the cpuinit call for CPU1 causes
freq_table of CPU0 to be overwritten. Instead, we maintain
a counter to keep track of cpus who use the cpufreq table
On Wed, May 25, 2011 at 17:18, Kevin Hilman khil...@ti.com wrote:
Nishanth Menon n...@ti.com writes:
Minor file header updates to reflect 2011 for omap2-cpufreq code
and remove misleading OMAP3 reference in omap1 cpufreq code.
Should probably be squashed to:
OMAP: cpufreq: Split OMAP1 and
On Wed, May 25, 2011 at 17:51, Todd Poynor toddpoy...@google.com wrote:
+ if (!freq_table) {
+ dev_err(mpu_dev, %s: cpu%d: no freq table!\n, __func__,
+ policy-cpu);
Just a minor comment: suggest dev_dbg() or WARN_ONCE() for some of
these
On Wed, May 25, 2011 at 17:53, ym cheng yongmingch...@hotmail.com wrote:
OK,I wil test on s3c2440 board,and share test data.
The series was meant for OMAP, if you meant:
http://www.samsung.com/global/business/semiconductor/productInfo.do?fmly_id=836partnum=S3C2440
as far as I see, this platform
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