On Wed, Apr 15, 2015 at 12:47 PM, Michael Welling mwell...@ieee.org wrote:
On Wed, Apr 15, 2015 at 09:43:30PM +0300, Tero Kristo wrote:
On 04/15/2015 05:09 PM, Michael Welling wrote:
On Wed, Apr 15, 2015 at 09:34:48AM +0300, Tero Kristo wrote:
On 04/15/2015 12:17 AM, Michael Welling wrote:
Quoting Tero Kristo (2015-02-25 11:04:18)
There is a case where NULL can be a valid return value for
ti_clk_get_reg_addr, specifically the case where both the provider index
and register offsets are zero. In this case, the current error checking
against a NULL pointer will fail. Thus, change
Quoting Stephen Boyd (2015-02-06 11:30:18)
On 02/06/15 05:39, Russell King - ARM Linux wrote:
On Thu, Feb 05, 2015 at 05:35:28PM -0800, Stephen Boyd wrote:
From what I can tell this code is
now broken because we made all clk getting functions (there's quite a
few...) return unique
On Tue, Feb 3, 2015 at 11:04 AM, Tony Lindgren t...@atomide.com wrote:
* Arnd Bergmann a...@arndb.de [150203 09:03]:
On Thursday 08 January 2015, Tony Lindgren wrote:
Great, hopefully this will finally allow Mike to make the
generic struct clk private to drivers/clk :)
Seems to boot
Quoting Tero Kristo (2015-02-02 11:32:01)
On 02/01/2015 11:24 PM, Mike Turquette wrote:
Quoting Tomeu Vizoso (2015-01-23 03:03:30)
Moves clock state to struct clk_core, but takes care to change as little
API as
possible.
struct clk_hw still has a pointer to a struct clk, which
Quoting Tony Lindgren (2015-02-02 12:44:02)
* Tero Kristo t-kri...@ti.com [150202 11:35]:
On 02/01/2015 11:24 PM, Mike Turquette wrote:
Quoting Tomeu Vizoso (2015-01-23 03:03:30)
AFAICT this doesn't break anything, but booting on OMAP3+ results in
noisy WARNs.
I think the correct
Quoting Stephen Boyd (2015-02-02 14:35:59)
On 02/02/15 13:31, Julia Lawall wrote:
On Mon, 2 Feb 2015, Stephen Boyd wrote:
Julia,
Is there a way we can write a coccinelle script to check for this? The
goal being to find all drivers that are comparing struct clk pointers or
Quoting Tony Lindgren (2015-02-02 08:12:37)
* Geert Uytterhoeven ge...@linux-m68k.org [150202 00:03]:
On Sun, Feb 1, 2015 at 11:18 PM, Mike Turquette mturque...@linaro.org
wrote:
Quoting Tomeu Vizoso (2015-01-31 10:36:22)
On 31 January 2015 at 02:31, Stephen Boyd sb...@codeaurora.org
Quoting Tony Lindgren (2015-01-30 17:04:44)
Hi all,
Looks like commit cb75a8fcd14e (clk: Add rate constraints to clocks)
causes a regression on at least omaps where the serial console either
does not show anything, or just prints garbage.
Reverting cb75a8fcd14e makes things work again on
Quoting Tomeu Vizoso (2015-01-31 10:36:22)
On 31 January 2015 at 02:31, Stephen Boyd sb...@codeaurora.org wrote:
On 01/29, Stephen Boyd wrote:
On 01/29/15 05:31, Geert Uytterhoeven wrote:
Hi Tomeu, Mike,
On Fri, Jan 23, 2015 at 12:03 PM, Tomeu Vizoso
tomeu.viz...@collabora.com
Quoting Tomeu Vizoso (2015-01-23 03:03:30)
Moves clock state to struct clk_core, but takes care to change as little API
as
possible.
struct clk_hw still has a pointer to a struct clk, which is the
implementation's per-user clk instance, for backwards compatibility.
The struct clk that
Quoting Tero Kristo (2015-01-30 07:20:36)
On 01/30/2015 02:42 AM, Mike Turquette wrote:
Quoting Tero Kristo (2015-01-29 12:19:29)
On 01/08/2015 01:00 AM, Tony Lindgren wrote:
* Tero Kristo t-kri...@ti.com [141216 08:22]:
Hi,
These patches move the legacy clock data for omap3 under
Quoting Tero Kristo (2015-01-29 12:19:29)
On 01/08/2015 01:00 AM, Tony Lindgren wrote:
* Tero Kristo t-kri...@ti.com [141216 08:22]:
Hi,
These patches move the legacy clock data for omap3 under drivers/clk/ti.
After these patches are applied, it should be possible to get rid of
Quoting Mike Turquette (2015-01-14 14:06:49)
Quoting Tony Lindgren (2015-01-13 14:51:26)
Hi all,
Here's a minimal support for the FAPLL (Flying Adder PLL) on dm816x
which is a omap variant.
Tony,
Patches look fine to me. I'll give it a few days for Paul or Tero to
comment
Quoting Tony Lindgren (2015-01-13 14:51:26)
Hi all,
Here's a minimal support for the FAPLL (Flying Adder PLL) on dm816x
which is a omap variant.
Tony,
Patches look fine to me. I'll give it a few days for Paul or Tero to
comment if they have any concerns.
Also, flying adder pll is a pretty
Quoting Paul Walmsley (2014-12-18 11:23:07)
On Wed, 17 Dec 2014, Lucas Stach wrote:
Maybe I'm thinking about this too lightly, but I think we already have
the right abstractions in place.
The clock tree in Linux is always modeled along the flow of reference
clocks. So typically the
Quoting Tero Kristo (2014-09-29 09:13:09)
Hi Mike,
The following changes since commit 7d1311b93e58ed55f3a31cc8f94c4b8fe988a2b9:
Linux 3.17-rc1 (2014-08-16 10:40:26 -0600)
are available in the git repository at:
g...@github.com:t-kristo/linux-pm.git for-v3.18/ti-clk-driver
for
Quoting Tero Kristo (2014-09-29 01:09:24)
On 09/27/2014 02:24 AM, Mike Turquette wrote:
Quoting Tero Kristo (2014-09-26 00:18:55)
On 09/26/2014 04:35 AM, Stephen Boyd wrote:
On 09/23/14 06:38, Tero Kristo wrote:
On 09/22/2014 10:18 PM, Stephen Boyd wrote:
On 08/21, Tero Kristo wrote
Quoting Tero Kristo (2014-09-30 01:48:49)
On 09/30/2014 10:07 AM, Mike Turquette wrote:
Quoting Tero Kristo (2014-09-29 01:09:24)
On 09/27/2014 02:24 AM, Mike Turquette wrote:
Quoting Tero Kristo (2014-09-26 00:18:55)
On 09/26/2014 04:35 AM, Stephen Boyd wrote:
On 09/23/14 06:38, Tero
Quoting Tero Kristo (2014-09-26 00:18:55)
On 09/26/2014 04:35 AM, Stephen Boyd wrote:
On 09/23/14 06:38, Tero Kristo wrote:
On 09/22/2014 10:18 PM, Stephen Boyd wrote:
On 08/21, Tero Kristo wrote:
/* Skip children who will be reparented to another clock */
if
Quoting Jyri Sarha (2014-09-11 01:44:24)
On 09/10/2014 01:14 AM, Mike Turquette wrote:
Quoting Jyri Sarha (2014-09-05 05:21:34)
The added gpio-gate-clock is a basic clock that can be enabled and
disabled trough a gpio output. The DT binding document for the clock
is also added
Quoting Tomi Valkeinen (2014-09-19 06:25:48)
On 19/09/14 16:12, Nishanth Menon wrote:
On 09/19/2014 08:07 AM, Tomi Valkeinen wrote:
On 16/09/14 23:40, Jyri Sarha wrote:
The added ti,gpio-gate-clock is a basic clock that can be enabled and
disabled trough a gpio output. The DT binding
Quoting Kiran Padwal (2014-09-24 02:45:29)
There is no need to init .owner field.
Based on the patch from Peter Griffin peter.grif...@linaro.org
mmc: remove .owner field for drivers using module_platform_driver
This patch removes the superflous .owner field for drivers which
use the
through my archives and found a post from January. You Cc'd
me as mturque...@linaro.org. Note that the address is wrapped in
chevrons but there is no name string (e.g. Mike Turquette).
My mailer doesn't parse this well it was not flagged as to:me in my
filters. Maybe other mailers handle this better
/gmane.linux.ports.arm.kernel/349180 for details.
Signed-off-by: Tero Kristo t-kri...@ti.com
To: Mike Turquette mturque...@linaro.org
Reported-by: Nishanth Menon n...@ti.com
Applied to clk-fixes.
Thanks!
Mike
---
drivers/clk/clk.c |7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff
Quoting Tero Kristo (2014-08-04 05:36:19)
On 08/04/2014 02:37 PM, Peter Ujfalusi wrote:
On 08/01/2014 04:15 PM, Tero Kristo wrote:
Hi,
This patch adds possibility to register external clocks (outside the main
SoC) on TI boards through device tree. Clock sources as such include for
Quoting Tero Kristo (2014-07-30 05:27:07)
On 07/30/2014 08:53 AM, Peter Ujfalusi wrote:
On 07/29/2014 07:12 PM, Mike Turquette wrote:
Oh yea, seems this got lost into the myriad of branches I have. I can push
this on top of my for-v3.17/ti-clk-drv if you like.
That is the easiest thing
Quoting Peter Ujfalusi (2014-07-14 03:10:28)
On 05/06/2014 04:39 PM, Peter Ujfalusi wrote:
Tero: can I have your ack for this patch or do you have further concerns?
Yea looks good to me, except for the fact that there is some work on
getting
default rate/parent support through DT. I
On Tue, Jul 29, 2014 at 1:23 AM, Tero Kristo t-kri...@ti.com wrote:
On 07/29/2014 09:27 AM, Mike Turquette wrote:
Quoting Peter Ujfalusi (2014-07-14 03:10:28)
On 05/06/2014 04:39 PM, Peter Ujfalusi wrote:
Tero: can I have your ack for this patch or do you have further
concerns?
Yea
functionality. The basic idea of this set is to
introduce clk_features struct which contains any SoC specific data / flags
within it, and this is used runtime instead of the current cpu_is_? checks.
Reviewed-by: Mike Turquette mturque...@linaro.org
There are also a couple of bug fixes
Quoting Tero Kristo (2014-07-03 00:41:22)
On 07/01/2014 10:48 PM, Felipe Balbi wrote:
Hi,
On Thu, Jun 19, 2014 at 02:33:14PM +0300, Tero Kristo wrote:
On 06/17/2014 11:04 AM, Tomi Valkeinen wrote:
When setting the rate of a clock, by default the clock framework will
change the parent
Quoting Paul Walmsley (2014-06-13 12:53:06)
Furthermore, as a general interface principle, allowing clk_set_rate() to
silently round rates could lead to unexpected behavior, since the set of
rates that clk_set_rate() can round to may change between the call to
clk_round_rate() and the call
Quoting Peter Ujfalusi (2014-06-29 22:56:55)
Hi Javier,
On 06/27/2014 09:23 PM, Javier Martinez Canillas wrote:
Hello Peter,
On Fri, Jun 27, 2014 at 8:01 AM, Peter Ujfalusi peter.ujfal...@ti.com
wrote:
Palmas class of devices can provide 32K clock(s) to be used by other
devices
Quoting Peter Ujfalusi (2014-06-26 23:01:09)
Hi Mike,
This is a resend of the v2 version of the palmas clock driver which seamingly
missed the 3.16 merge window. I have added Nishanth's Reviewed-by tag to the
patches.
Thanks for the resend. Applied to clk-next.
Regards,
Mike
Changes
Quoting Paul Walmsley (2014-06-17 01:15:09)
On Tue, 17 Jun 2014, Tomi Valkeinen wrote:
When setting the rate of a clock, by default the clock framework will
change the parent of the clock to the most suitable one in
__clk_mux_determine_rate() (most suitable by looking at the clock rate).
Quoting Tero Kristo (2014-06-17 01:23:31)
On 06/17/2014 11:19 AM, Paul Walmsley wrote:
On Tue, 17 Jun 2014, Tero Kristo wrote:
I am fine with this approach, as it seems pretty much all the other
mux-clock
users are setting this flag also. The TI clocks have had this way of using
mux
Quoting Tomi Valkeinen (2014-05-15 05:25:37)
On 15/05/14 09:08, Mike Turquette wrote:
Quoting Tomi Valkeinen (2014-05-12 05:13:51)
On 12/05/14 15:02, Tero Kristo wrote:
On 05/08/2014 12:06 PM, Tomi Valkeinen wrote:
The current DPLL code does not try to round the clock rate, and instead
On Mon, May 19, 2014 at 6:20 AM, Tero Kristo t-kri...@ti.com wrote:
On 05/05/2014 10:49 AM, Tero Kristo wrote:
On 05/01/2014 10:00 PM, Mike Turquette wrote:
Quoting Tero Kristo (2014-04-29 07:51:14)
On 04/29/2014 05:15 PM, Sourav Poddar wrote:
We need tbclk clock data for the functioning
Quoting Nishanth Menon (2014-05-15 05:33:13)
On 05/15/2014 07:18 AM, Kishon Vijay Abraham I wrote:
Hi,
On Thursday 15 May 2014 05:42 PM, Nishanth Menon wrote:
On Thu, May 15, 2014 at 6:59 AM, Kishon Vijay Abraham I kis...@ti.com
wrote:
Hi Nishant,
On Thursday 15 May 2014 05:16
Quoting Nishanth Menon (2014-05-16 03:45:57)
Hi,
This patch series has been carried over in vendor kernel for quiet
few years now.
Unfortunately, it was very recently re-discovered and upstream kernel
is noticed to be broken for OMAP5 1.5GHz - at least we are operating
DPLL at frequency
Quoting Sourav Poddar (2014-04-29 01:34:20)
tbclk does not need to be a composite clock, we can simply
use gate clock for this purpose.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
Looks good.
Regards,
Mike
---
v1-v2:
change compatible string according to mainline.
Quoting Peter Ujfalusi (2014-05-07 03:20:47)
Audio Tracking Logic is designed to be used by HD Radio applications to
synchronize the audio output clocks to the baseband clock. ATL can be also
used to track errors between two reference clocks (BWS, AWS) and generate a
modulated
clock output
Quoting Tomi Valkeinen (2014-05-12 05:13:51)
On 12/05/14 15:02, Tero Kristo wrote:
On 05/08/2014 12:06 PM, Tomi Valkeinen wrote:
The current DPLL code does not try to round the clock rate, and instead
returns an error if the requested clock rate cannot be produced exactly
by the DPLL.
Quoting Tero Kristo (2014-04-29 07:51:14)
On 04/29/2014 05:15 PM, Sourav Poddar wrote:
We need tbclk clock data for the functioning of ehrpwm
module. Hence, populating the required clock information
in clock dts file.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
Acked-by: Tero
Quoting Tero Kristo (2014-03-05 05:10:17)
Ping.
Mike, any feedback on this?
Hi Tero,
Have you seen Sylwester's approach[1]? I prefer it since it is more
device-oriented and less centralized. The clock consumer enumerates
the default parent or rate of a consumed clock. This can be made to
Quoting Nishanth Menon (2014-03-10 12:25:43)
On 03/10/2014 01:01 PM, Mark Brown wrote:
On Mon, Mar 10, 2014 at 12:41:05PM -0500, Nishanth Menon wrote:
The only other options are:
a) Abstract it at a higher level at user drivers, since they are
aware of the sequencing needs - but this
Quoting Tomi Valkeinen (2014-03-17 05:53:03)
On 27/02/14 04:25, Mike Turquette wrote:
Quoting Tero Kristo (2014-02-14 05:45:22)
On 02/13/2014 12:03 PM, Tomi Valkeinen wrote:
clk-divider.c does not calculate the rates consistently at the moment.
As an example, on OMAP3 we have a clock
Quoting Florian Vaussard (2014-02-26 02:38:08)
When arch/arm/mach-omap2/gpmc.c calls clk_get(..., fck), it will
get a dummy clock and try to use it. As the rate is configured to zero,
this will result in several divisions by zero, and misconfigured
timings, with devices on the bus being lost
Quoting Roger Quadros (2014-02-25 01:32:19)
Hi Mike,
On 02/25/2014 10:43 AM, Mike Turquette wrote:
Quoting Roger Quadros (2014-02-20 03:40:01)
The OMAP USB Host MFD driver no longer expects these non-existing
clocks from the OMAP3 platform, so get rid of them.
Looks good to me
behavior which fixes the
inconsistency:
14400 - 14400
14399 - 123428572
123428572 - 123428572
123428571 - 10800
Signed-off-by: Tomi Valkeinen tomi.valkei...@ti.com
Cc: Mike Turquette mturque...@linaro.org
---
drivers/clk/clk-divider.c | 10 +-
1 file
Quoting Nishanth Menon (2014-02-26 18:34:55)
+/**
+ * pm_runtime_get_rate() - Returns the device operational frequency
+ * @dev: Device to handle
+ * @rate: Returns rate in Hz.
+ *
+ * Returns appropriate error value in case of error conditions, else
+ * returns 0 and rate is
Quoting Nishanth Menon (2014-01-29 10:19:16)
cpu0 clock node has no functionality, since cpufreq-cpu0 is already
capable of picking up the clock from dts.
Signed-off-by: Nishanth Menon n...@ti.com
Taken into clk-next!
Regards,
Mike
---
drivers/clk/ti/clk-33xx.c |1 -
1 file
Quoting Roger Quadros (2014-02-20 03:40:01)
The OMAP USB Host MFD driver no longer expects these non-existing
clocks from the OMAP3 platform, so get rid of them.
Looks good to me.
Regards,
Mike
CC: Tero Kristo t-kri...@ti.com
CC: Mike Turquette mturque...@linaro.org
Signed-off-by: Roger
Quoting Nishanth Menon (2014-02-18 12:32:18)
From: Mike Turquette mturque...@linaro.org
This patch provides helper functions for drivers that wish to scale
voltage through the clock rate-change notifiers. The approach taken
is that the user-driver(cpufreq/devfreq) do not care about
On Sat, Jan 18, 2014 at 9:50 AM, Tony Lindgren t...@atomide.com wrote:
* Mike Turquette mturque...@linaro.org [140117 13:39]:
Quoting Tero Kristo (2014-01-17 12:25:37)
Hi,
Quick emergency band-aid for the build breakages introduced in clk-next
by Mike. I didn't have time to test this out
Quoting Tero Kristo (2014-01-17 10:11:06)
On 01/17/2014 07:53 PM, Tony Lindgren wrote:
* Kevin Hilman khil...@linaro.org [140117 09:48]:
Mike Turquette mturque...@linaro.org writes:
[...]
I took Tony's advice and fast-forwarded clk-next to -rc7 and applied
Tero's series
Quoting Tero Kristo (2014-01-17 12:25:37)
Hi,
Quick emergency band-aid for the build breakages introduced in clk-next
by Mike. I didn't have time to test this out (Nishanth will provide some
logs) and I will leave the decision whether/how to use these patches or not
to Tony + Mike.
I
Quoting Felipe Balbi (2014-01-14 18:04:21)
Hi,
On Tue, Jan 14, 2014 at 02:36:13PM -0600, Felipe Balbi wrote:
Felipe, care to run your randconfig magic for this?
This branch builds just fine so far, I still have omap5 multiplaform and
uniplatform builds, but since that was working
Quoting Mike Turquette (2014-01-14 19:16:32)
Quoting Felipe Balbi (2014-01-14 18:04:21)
Hi,
On Tue, Jan 14, 2014 at 02:36:13PM -0600, Felipe Balbi wrote:
Felipe, care to run your randconfig magic for this?
This branch builds just fine so far, I still have omap5 multiplaform
Quoting Tero Kristo (2014-01-09 06:00:11)
Hi,
So, bad luck number release for this, as v12 wasn't sufficient still.
Changes compared to previous version:
- Dropped any changes to generic clock drivers, as it seems impossible
to agree anything in short term, this means the patch set
Quoting Tero Kristo (2013-12-16 00:13:08)
On 12/15/2013 06:23 AM, Mike Turquette wrote:
Quoting Tero Kristo (2013-11-26 00:05:51)
Some OMAP clocks require knowledge about their parent clockdomain for
book keeping purposes. This patch creates a new DT binding for TI
clockdomains, which act
Quoting Tero Kristo (2013-11-26 00:05:42)
Current clock wrappers assume simple and direct mapped hardware register
access. Improve this support by adding functionality for registering
platform specific clock I/O wrappers, which can be used to support
various features needed like endianess
Quoting Tero Kristo (2013-11-26 00:05:41)
Hi,
Changes compared to v9:
- rebased on top of 3.13-rc1
- modified the low level clk register API to provide SoC specific clk_readl
and clk_writel support which can be registered during boot, TI SoC variant
uses regmap on low level
- dropped
Quoting Rajendra Nayak (2013-12-12 03:38:29)
With support to parse clock data from DT, move all main and optional
clock information from hwmod to DT.
We still retain clocks in hwmod for devices which do not have a DT node.
Signed-off-by: Rajendra Nayak rna...@ti.com
Reviewed-by: Mike
Quoting Tero Kristo (2013-11-26 00:05:51)
Some OMAP clocks require knowledge about their parent clockdomain for
book keeping purposes. This patch creates a new DT binding for TI
clockdomains, which act as a collection of device clocks.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
Quoting Tero Kristo (2013-11-26 00:05:41)
Hi,
Hi Tero,
Thanks for your long suffering patience on this series. The clock
patches look very good to me with exception of a few small comments. Let
me know how I can help with the hierarchal DT stuff since I think that
has been the gating factor
Quoting Paul Walmsley (2013-10-19 10:16:50)
On Fri, 11 Oct 2013, Tero Kristo wrote:
Some drivers require direct access to the autoidle functionality of the
interface clocks. Added clock APIs for these, so that the drivers do not
need to access CM registers directly.
Signed-off-by:
Quoting Paul Walmsley (2013-10-07 01:21:16)
On Tue, 10 Sep 2013, Tero Kristo wrote:
In theory, DPLLs can also be used in their bypass mode to feed customer
nodes
clocks. I just think the check in the clkoutx2_recalc is wrong, and should
be
enhanced to actually check what is the
Quoting Tero Kristo (2013-09-25 01:48:26)
+
+static const struct clk_ops apll_ck_ops = {
+ .enable = dra7_apll_enable,
+ .disable= dra7_apll_disable,
Looks like .is_enabled is missing?
Also have you thought about using .prepare or .unprepare for these PLLs
which
Quoting Tero Kristo (2013-09-25 01:48:06)
Hi all,
Version 7 contains following high level changes:
- Dropped support for basic bindings from Mike Turquette, instead using
vendor specific bindings for all clocks
- Mux clock + divider clock vendor specific bindings get rid of use
Quoting Archit Taneja (2013-09-17 00:06:28)
HDMI PLL is a block common to DSS in OMAP4, OMAP5 and DRA7x. Move the
existing PLL functions from ti_hdmi_4xxx_ip.c and hdmi.c to a separate file.
These funcs are called directly from the hdmi driver rather than hdmi_ip_ops
function pointer calls.
On Tue, Sep 17, 2013 at 3:02 AM, Tomi Valkeinen tomi.valkei...@ti.com wrote:
On 17/09/13 12:38, Mike Turquette wrote:
Quoting Archit Taneja (2013-09-17 00:06:28)
HDMI PLL is a block common to DSS in OMAP4, OMAP5 and DRA7x. Move the
existing PLL functions from ti_hdmi_4xxx_ip.c and hdmi.c
Quoting Tero Kristo (2013-09-13 04:34:54)
On 09/13/2013 10:51 AM, Stefan Roese wrote:
On 11.09.2013 09:21, Tomi Valkeinen wrote:
On 10/09/13 16:17, Tero Kristo wrote:
In theory, DPLLs can also be used in their bypass mode to feed customer
nodes clocks. I just think the check in the
Quoting Tero Kristo (2013-09-10 06:17:45)
On 09/10/2013 03:40 PM, Tomi Valkeinen wrote:
On 10/09/13 15:24, Tero Kristo wrote:
On 09/10/2013 03:19 PM, Tomi Valkeinen wrote:
On 10/09/13 15:12, Tero Kristo wrote:
If it claims it is not locked, it means the DPLL itself is disabled. You
Quoting Tero Kristo (2013-08-29 06:15:53)
The OMAP clock driver now supports DPLL clock type. This patch also
adds support for DT DPLL nodes.
Signed-off-by: Tero Kristo t-kri...@ti.com
Tero,
Overall this patch is really great. Some minor comments below.
diff --git
On Tue, Sep 10, 2013 at 2:17 PM, Mike Turquette mturque...@linaro.org wrote:
Quoting Tero Kristo (2013-09-10 06:17:45)
On 09/10/2013 03:40 PM, Tomi Valkeinen wrote:
On 10/09/13 15:24, Tero Kristo wrote:
On 09/10/2013 03:19 PM, Tomi Valkeinen wrote:
On 10/09/13 15:12, Tero Kristo wrote
Quoting Tero Kristo (2013-08-19 10:06:39)
On 08/19/2013 07:24 PM, Mark Rutland wrote:
On Mon, Aug 19, 2013 at 04:09:37PM +0100, Tero Kristo wrote:
On 08/19/2013 05:18 PM, Mark Rutland wrote:
On Mon, Aug 19, 2013 at 02:34:45PM +0100, Tero Kristo wrote:
On 08/13/2013 01:50 PM, Mark Rutland
Quoting Rajendra Nayak (2013-08-08 03:14:11)
On OMAP4 we have clk_set_rate()s being done for a few
DPLL clock nodes, as part of the clock init code, since
the bootloaders no longer locks these DPLLs.
...
Signed-off-by: Rajendra Nayak rna...@ti.com
Taken into clk-next. Thanks for the fix.
Quoting Luciano Coelho (2013-07-30 06:04:34)
+static const struct of_device_id wlcore_sdio_of_clk_match_table[] = {
+ { .compatible = ti,wilink-clock },
+};
+
static struct wl12xx_platform_data *wlcore_get_pdata_from_of(struct device
*dev)
{
struct wl12xx_platform_data
On Tue, Jul 16, 2013 at 6:10 AM, Eduardo Valentin
eduardo.valen...@ti.com wrote:
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA256
Hi,
Adding Mike's correct address.
On 16-07-2013 08:37, Felipe Balbi wrote:
Hi,
trying to get USB host verified on OMAP5 uEVM with v3.11-rc1. The
.
+ *
+ * Paul Walmsley (p...@pwsan.com)
+ * Rajendra Nayak (rna...@ti.com)
+ * Benoit Cousson (b-cous...@ti.com)
+ * Mike Turquette (mturque...@linaro.org)
+ * Tero Kristo (t-kri...@ti.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU
Walmsley (p...@pwsan.com)
+ * Rajendra Nayak (rna...@ti.com)
+ * Benoit Cousson (b-cous...@ti.com)
+ * Mike Turquette (mturque...@linaro.org)
+ * Tero Kristo (t-kri...@ti.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General
On Wed, Jun 19, 2013 at 6:18 AM, Tero Kristo t-kri...@ti.com wrote:
of_property_read_u8 does not work properly because of endianess problem
with its current implementation, and this causes it to always return
0 with little endian architectures. Instead, use property_read_u32
until this is
On Mon, Jun 3, 2013 at 11:27 PM, Ambresh K ambr...@ti.com wrote:
clksel is an omap-centric term. How about:
clk_mux_get_parent should return an error if the value read from the
register is erroneous.
Make sense, will fix it.
The general approach looks good to me. Can you submit a V2
A Fernandes joelag...@ti.com
Cc: Nishanth Menon n...@ti.com
Cc: Paul Walmsley p...@pwsan.com
Cc: Tony Lindgren t...@atomide.com
Signed-off-by: Mike Turquette mturque...@linaro.org
---
arch/arm/mach-omap2/cclock44xx_data.c | 54 ---
1 file changed, 6 insertions(+), 48 deletions
to see what others think of this approach.
Cc: Benoit Cousson b-cous...@ti.com
Cc: Rajendra Nayak rna...@ti.com
Cc: Joel A Fernandes joelag...@ti.com
Cc: Nishanth Menon n...@ti.com
Cc: Paul Walmsley p...@pwsan.com
Cc: Tony Lindgren t...@atomide.com
Signed-off-by: Mike Turquette mturque
: Rajendra Nayak rna...@ti.com
Cc: Joel A Fernandes joelag...@ti.com
Cc: Nishanth Menon n...@ti.com
Cc: Paul Walmsley p...@pwsan.com
Cc: Tony Lindgren t...@atomide.com
Signed-off-by: Mike Turquette mturque...@linaro.org
---
This driver simply matches the basic bindings (so far). Eventually it
would
-clock, divider-clock, fixed-clock, fixed-factor and
(unpublished) gate-clock bindings in my local repo, but it is not
currently booting. I wanted to get this early preview out regardless.
[1] http://article.gmane.org/gmane.linux.kernel/1501216
Mike Turquette (3):
clk: omap: introduce clock driver
-by: Mike Turquette mturque...@linaro.org
Index: b/arch/arm/mach-omap2/clock36xx.c
===
--- a/arch/arm/mach-omap2/clock36xx.c
+++ b/arch/arm/mach-omap2/clock36xx.c
@@ -39,30 +39,25 @@
*/
int
Quoting Jean-Philippe Francois (2013-05-17 08:51:26)
omap36xx_pwrdn_clk_enable_with_hsdiv_restore expects the parent hw of the
clock
to be a clk_hw_omap. However, looking at cclock3xxx_data.c, all concerned
clock
have parent defined as clk_divider.
Fix the function to use clk_divider.
khil...@deeprootsystems.com
Cc: Mike Turquette mturque...@linaro.org
Cc: Paul Walmsley p...@pwsan.com
[t...@atomide.com: co-developed]
Signed-off-by: Tony Lindgren t...@atomide.com
Signed-off-by: Nishanth Menon n...@ti.com
---
Changes in this version:
- review comments incorporated
by of_clk_get.
Based on discussion contributions from Roger Quadros, Grygorii Strashko
and others.
Cc: Kevin Hilman khil...@deeprootsystems.com
Cc: Mike Turquette mturque...@linaro.org
Cc: Paul Walmsley p...@pwsan.com
[t...@atomide.com: co-developed]
Signed-off-by: Tony Lindgren t
Quoting Andrii Tseglytskyi (2013-04-16 05:40:44)
On 04/16/2013 12:53 AM, Kevin Hilman wrote:
In addition to Mike's comments (which I completely agree with), it would
be very helfpul to see how this is actually used. e.g, how the
regulators are chained together, how the proper ordering is
Quoting Andrii Tseglytskyi (2013-04-15 06:28:10)
Cc: Mike Turquette mturque...@linaro.org
Signed-off-by: Andrii.Tseglytskyi andrii.tseglyts...@ti.com
Signed-off-by: Mike Turquette mturque...@linaro.org
It is very strange to Cc me and include my Signed-off-by. Go ahead and
drop my SoB. I'll
Quoting Nishanth Menon (2013-04-10 10:39:21)
diff --git a/drivers/clk/omap/clk.c b/drivers/clk/omap/clk.c
new file mode 100644
index 000..63a4cce
--- /dev/null
+++ b/drivers/clk/omap/clk.c
@@ -0,0 +1,94 @@
+/*
+ * Texas Instruments OMAP Clock driver
+ *
+ * Copyright (C) 2013 Texas
Quoting Nishanth Menon (2013-04-09 13:49:00)
On 10:43-20130409, Tony Lindgren wrote:
* Tony Lindgren t...@atomide.com [130409 09:54]:
* Roger Quadros rog...@ti.com [130409 03:00]:
On 04/05/2013 06:58 PM, Tony Lindgren wrote:
Can't you just use the clock name there to get it?
Quoting Nishanth Menon (2013-04-02 19:00:02)
On 20:35-20130402, Andrii Tseglytskyi wrote:
On 04/02/2013 08:16 PM, Mike Turquette wrote:
Quoting Nishanth Menon (2013-04-01 20:35:45)
On 17:05-20130401, Mike Turquette wrote:
OK, so we're in agreement on what The Future looks like. What does
Andrii,
Sorry to nitpick further but this your replies look very non-standard.
Typically a right chevron and a space is used to indent replies instead
of a tab. Something like this:
https://wiki.openstack.org/wiki/MailingListEtiquette#Reply_Level_Indication
Quoting Andrii Tseglytskyi
On Sat, Mar 30, 2013 at 7:35 PM, Paul Walmsley p...@pwsan.com wrote:
Hi Mike, Kevin,
On Wed, 3 Oct 2012, Mike Turquette wrote:
From: Mike Turquette mturque...@linaro.org
This series creates a new callback for struct voltagedomain,
.get_voltage. This fetches the voltage from hardware
Quoting Rajendra Nayak (2013-03-28 03:59:41)
omap3_noncore_dpll_set_rate() attempts an enable of bypass clk as well
as ref clk for every .set_rate attempt on a noncore DPLL, regardless of
whether the .set_rate results in the DPLL being locked or put in bypass.
Early at boot, while some of
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