[PATCH] arm: dts: dra7-evm: remove interrupt binding.
The qspi node defines crossbar number as its interrupt number. But, the crossbar dts patches are not yet there, this causes a warning during boot. So interrupts = property should be removed from DT and added later by crossbar series. Reported-by: Sricharan R r.sricha...@ti.com Signed-off-by: Sourav Poddar sourav.pod...@ti.com --- arch/arm/boot/dts/dra7.dtsi |1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index c29945e..eda7e84 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -773,7 +773,6 @@ clocks = qspi_gfclk_div; clock-names = fck; num-cs = 4; - interrupts = 0 343 0x4; status = disabled; }; -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCHv2 1/5] drivers: w1: omap_hdq: cleanup and bug fixes.
The patch adds the following to the omap hdq driver.
1. HDQ Device reset call in probe.
2. Enabling '1 wire mode' and checking for presence pulse bit.
3. Proper disabling and enabling of interrupts during read path.
4. Add re-initialization code during SKIP ROM command execution.
5. Miscellaneous cleanup(formatting, return error checks).
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
drivers/w1/masters/omap_hdq.c | 84 -
1 file changed, 67 insertions(+), 17 deletions(-)
diff --git a/drivers/w1/masters/omap_hdq.c b/drivers/w1/masters/omap_hdq.c
index 9900e8e..ca3623c 100644
--- a/drivers/w1/masters/omap_hdq.c
+++ b/drivers/w1/masters/omap_hdq.c
@@ -27,21 +27,22 @@
#define OMAP_HDQ_TX_DATA 0x04
#define OMAP_HDQ_RX_DATA 0x08
#define OMAP_HDQ_CTRL_STATUS 0x0c
-#define OMAP_HDQ_CTRL_STATUS_INTERRUPTMASK (16)
-#define OMAP_HDQ_CTRL_STATUS_CLOCKENABLE (15)
-#define OMAP_HDQ_CTRL_STATUS_GO(14)
-#define OMAP_HDQ_CTRL_STATUS_INITIALIZATION(12)
-#define OMAP_HDQ_CTRL_STATUS_DIR (11)
-#define OMAP_HDQ_CTRL_STATUS_MODE (10)
+#define OMAP_HDQ_CTRL_STATUS_INTERRUPTMASK (1 6)
+#define OMAP_HDQ_CTRL_STATUS_CLOCKENABLE (1 5)
+#define OMAP_HDQ_CTRL_STATUS_PRESENCE (1 3)
+#define OMAP_HDQ_CTRL_STATUS_GO (1 4)
+#define OMAP_HDQ_CTRL_STATUS_INITIALIZATION(1 2)
+#define OMAP_HDQ_CTRL_STATUS_DIR (1 1)
+#define OMAP_HDQ_CTRL_STATUS_MODE (1 0)
#define OMAP_HDQ_INT_STATUS0x10
-#define OMAP_HDQ_INT_STATUS_TXCOMPLETE (12)
-#define OMAP_HDQ_INT_STATUS_RXCOMPLETE (11)
-#define OMAP_HDQ_INT_STATUS_TIMEOUT(10)
+#define OMAP_HDQ_INT_STATUS_TXCOMPLETE (1 2)
+#define OMAP_HDQ_INT_STATUS_RXCOMPLETE (1 1)
+#define OMAP_HDQ_INT_STATUS_TIMEOUT(1 0)
#define OMAP_HDQ_SYSCONFIG 0x14
-#define OMAP_HDQ_SYSCONFIG_SOFTRESET (11)
-#define OMAP_HDQ_SYSCONFIG_AUTOIDLE(10)
+#define OMAP_HDQ_SYSCONFIG_SOFTRESET (1 1)
+#define OMAP_HDQ_SYSCONFIG_AUTOIDLE(1 0)
#define OMAP_HDQ_SYSSTATUS 0x18
-#define OMAP_HDQ_SYSSTATUS_RESETDONE (10)
+#define OMAP_HDQ_SYSSTATUS_RESETDONE (1 0)
#define OMAP_HDQ_FLAG_CLEAR0
#define OMAP_HDQ_FLAG_SET 1
@@ -115,6 +116,15 @@ static inline u8 hdq_reg_merge(struct hdq_data *hdq_data,
u32 offset,
return new_val;
}
+static void hdq_disable_interrupt(struct hdq_data *hdq_data)
+{
+ u32 ie;
+
+ ie = readl(hdq_data-hdq_base + OMAP_HDQ_CTRL_STATUS);
+ writel(ie ~OMAP_HDQ_CTRL_STATUS_INTERRUPTMASK,
+ hdq_data-hdq_base + OMAP_HDQ_CTRL_STATUS);
+}
+
/*
* Wait for one or more bits in flag change.
* HDQ_FLAG_SET: wait until any bit in the flag is set.
@@ -263,8 +273,7 @@ static int _omap_hdq_reset(struct hdq_data *hdq_data)
* interrupt.
*/
hdq_reg_out(hdq_data, OMAP_HDQ_CTRL_STATUS,
- OMAP_HDQ_CTRL_STATUS_CLOCKENABLE |
- OMAP_HDQ_CTRL_STATUS_INTERRUPTMASK);
+ OMAP_HDQ_CTRL_STATUS_CLOCKENABLE);
/* wait for reset to complete */
ret = hdq_wait_for_flag(hdq_data, OMAP_HDQ_SYSSTATUS,
@@ -275,7 +284,8 @@ static int _omap_hdq_reset(struct hdq_data *hdq_data)
else {
hdq_reg_out(hdq_data, OMAP_HDQ_CTRL_STATUS,
OMAP_HDQ_CTRL_STATUS_CLOCKENABLE |
- OMAP_HDQ_CTRL_STATUS_INTERRUPTMASK);
+ OMAP_HDQ_CTRL_STATUS_INTERRUPTMASK |
+ OMAP_HDQ_CTRL_STATUS_MODE);
hdq_reg_out(hdq_data, OMAP_HDQ_SYSCONFIG,
OMAP_HDQ_SYSCONFIG_AUTOIDLE);
}
@@ -327,6 +337,18 @@ static int omap_hdq_break(struct hdq_data *hdq_data)
ret = -ETIMEDOUT;
goto out;
}
+
+ /*
+* check for the presence detect bit to get
+* set to show that the slave is responding
+*/
+ if (hdq_reg_in(hdq_data, OMAP_HDQ_CTRL_STATUS)
+ OMAP_HDQ_CTRL_STATUS_PRESENCE) {
+ dev_dbg(hdq_data-dev, Presence bit not set\n);
+ ret = -ETIMEDOUT;
+ goto out;
+ }
+
/*
* wait for both INIT and GO bits rerurn to zero.
* zero wait time expected for interrupt mode.
@@ -361,6 +383,8 @@ static int hdq_read_byte(struct hdq_data *hdq_data, u8 *val)
goto out;
}
+ hdq_data-hdq_irqstatus = 0;
+
if (!(hdq_data-hdq_irqstatus OMAP_HDQ_INT_STATUS_RXCOMPLETE)) {
hdq_reg_merge(hdq_data, OMAP_HDQ_CTRL_STATUS,
OMAP_HDQ_CTRL_STATUS_DIR | OMAP_HDQ_CTRL_STATUS_GO,
@@ -426,7 +450,8 @@ static int omap_hdq_get(struct hdq_data
[PATCHv2 2/5] w1: omap_hdq: Add compatible property for omap hdq driver.
Add compatible property for omap hdq driver.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
.../devicetree/bindings/hdq1w/omap_hdq.txt | 20
drivers/w1/masters/omap_hdq.c |8
2 files changed, 28 insertions(+)
create mode 100644 Documentation/devicetree/bindings/hdq1w/omap_hdq.txt
diff --git a/Documentation/devicetree/bindings/hdq1w/omap_hdq.txt
b/Documentation/devicetree/bindings/hdq1w/omap_hdq.txt
new file mode 100644
index 000..a7e011e
--- /dev/null
+++ b/Documentation/devicetree/bindings/hdq1w/omap_hdq.txt
@@ -0,0 +1,20 @@
+HDQ/1w for OMAP platforms
+
+Required properties :
+- compatible : Must be ti,am43xx-hdq.
+- ti,hwmods : Must be hdq1w.
+- reg: Should contain register location and length.
+- interrupts: Should contain interrupt.
+- clock: Clock input to HDQ1w controller.
+
+Example:
+
+ hdq: hdq@48347000 {
+ compatible = ti,am43xx-hdq;
+ reg = 0x48347000 0x1000;
+ interrupts = GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH;
+ clocks = func_12m_clk;
+ clock-names = fck;
+ ti,hwmods = hdq1w;
+ status = disabled;
+ };
diff --git a/drivers/w1/masters/omap_hdq.c b/drivers/w1/masters/omap_hdq.c
index ca3623c..97a8412 100644
--- a/drivers/w1/masters/omap_hdq.c
+++ b/drivers/w1/masters/omap_hdq.c
@@ -17,6 +17,7 @@
#include linux/io.h
#include linux/sched.h
#include linux/pm_runtime.h
+#include linux/of.h
#include ../w1.h
#include ../w1_int.h
@@ -73,11 +74,18 @@ struct hdq_data {
static int omap_hdq_probe(struct platform_device *pdev);
static int omap_hdq_remove(struct platform_device *pdev);
+static const struct of_device_id omap_hdq_dt_match[] = {
+ { .compatible = ti,am43xx-hdq},
+ {},
+};
+MODULE_DEVICE_TABLE(of, omap_hdq_dt_match);
+
static struct platform_driver omap_hdq_driver = {
.probe =omap_hdq_probe,
.remove = omap_hdq_remove,
.driver = {
.name = omap_hdq,
+ .of_match_table = of_match_ptr(omap_hdq_dt_match),
},
};
--
1.7.9.5
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[PATCHv2 0/5] AM437x: HDQ/1wire protocol
This series adds support for HDQ/1w protocol driver for am43x epos evm where it can be used for measuring the temperature of a slave device connected to a particular header. Tested the patch series on AM437x, hdq master and slave devices are getting registered and interrupts are getting triggered for break and tx conditions. v1-v2: cleaned up hdq_disable_interrupt api. Sourav Poddar (5): drivers: w1: omap_hdq: cleanup and bug fixes. w1: omap_hdq: Add compatible property for omap hdq driver. arm: mach-omap2: selective device build from the platform code. arm: dts: am4372: Add hdq device tree data. arm: hwmod: am437x: Add hwmod data for hdq1w. .../devicetree/bindings/hdq1w/omap_hdq.txt | 20 + arch/arm/boot/dts/am4372.dtsi | 10 +++ arch/arm/boot/dts/am43x-epos-evm.dts | 12 +++ arch/arm/mach-omap2/hdq1w.c|2 + arch/arm/mach-omap2/omap_hwmod_43xx_data.c | 36 arch/arm/mach-omap2/prcm43xx.h |1 + drivers/w1/masters/omap_hdq.c | 93 7 files changed, 157 insertions(+), 17 deletions(-) create mode 100644 Documentation/devicetree/bindings/hdq1w/omap_hdq.txt -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCHv2 4/5] arm: dts: am4372: Add hdq device tree data.
Add device tree nodes and pinmux for hdq/1wire on
am43x epos evm.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
arch/arm/boot/dts/am4372.dtsi| 10 ++
arch/arm/boot/dts/am43x-epos-evm.dts | 12
2 files changed, 22 insertions(+)
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index 36d523a..5f7c167 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -735,6 +735,16 @@
#size-cells = 1;
status = disabled;
};
+
+ hdq: hdq@48347000 {
+ compatible = ti,am43xx-hdq;
+ reg = 0x48347000 0x1000;
+ interrupts = GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH;
+ clocks = func_12m_clk;
+ clock-names = fck;
+ ti,hwmods = hdq1w;
+ status = disabled;
+ };
};
};
diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts
b/arch/arm/boot/dts/am43x-epos-evm.dts
index 167dbc8..e71ef1c 100644
--- a/arch/arm/boot/dts/am43x-epos-evm.dts
+++ b/arch/arm/boot/dts/am43x-epos-evm.dts
@@ -138,6 +138,12 @@
0x160 (PIN_INPUT | MUX_MODE7) /*
spi0_cs1.gpio0_6 */
;
};
+
+ hdq_pins: pinmux_hdq_pins {
+ pinctrl-single,pins =
+ 0x234 (PIN_INPUT_PULLUP | MUX_MODE1)/*
cam1_wen.hdq_gpio */
+ ;
+ };
};
matrix_keypad: matrix_keypad@0 {
@@ -367,3 +373,9 @@
pinctrl-0 = spi1_pins;
status = okay;
};
+
+hdq {
+ status = okay;
+ pinctrl-names = default;
+ pinctrl-0 = hdq_pins;
+};
--
1.7.9.5
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[PATCHv2 3/5] arm: omap2: skip device build from platform code for dt.
For SOCs with dt enabled, device should be build through device tree.
Prevent device build call from platform code, if device tree is
enabled.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
arch/arm/mach-omap2/hdq1w.c |2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/mach-omap2/hdq1w.c b/arch/arm/mach-omap2/hdq1w.c
index cbc8e3c..f78b4a1 100644
--- a/arch/arm/mach-omap2/hdq1w.c
+++ b/arch/arm/mach-omap2/hdq1w.c
@@ -76,6 +76,7 @@ int omap_hdq1w_reset(struct omap_hwmod *oh)
return 0;
}
+#ifndef CONFIG_OF
static int __init omap_init_hdq(void)
{
int id = -1;
@@ -95,3 +96,4 @@ static int __init omap_init_hdq(void)
return 0;
}
omap_arch_initcall(omap_init_hdq);
+#endif
--
1.7.9.5
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[PATCHv2 5/5] arm: hwmod: am437x: Add hwmod data for hdq1w.
These adds hwmod data for hdq/1w driver.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
arch/arm/mach-omap2/omap_hwmod_43xx_data.c | 36
arch/arm/mach-omap2/prcm43xx.h |1 +
2 files changed, 37 insertions(+)
diff --git a/arch/arm/mach-omap2/omap_hwmod_43xx_data.c
b/arch/arm/mach-omap2/omap_hwmod_43xx_data.c
index 5c2cc80..3a8ca96 100644
--- a/arch/arm/mach-omap2/omap_hwmod_43xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_43xx_data.c
@@ -19,6 +19,7 @@
#include omap_hwmod.h
#include omap_hwmod_33xx_43xx_common_data.h
#include prcm43xx.h
+#include hdq1w.h
/* IP blocks */
static struct omap_hwmod am43xx_l4_hs_hwmod = {
@@ -415,6 +416,32 @@ static struct omap_hwmod am43xx_qspi_hwmod = {
},
};
+static struct omap_hwmod_class_sysconfig am43xx_hdq1w_sysc = {
+ .rev_offs = 0x,
+ .sysc_offs = 0x0014,
+ .syss_offs = 0x0018,
+ .sysc_flags = (SYSC_HAS_SOFTRESET),
+ .sysc_fields= omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class am43xx_hdq1w_hwmod_class = {
+ .name = hdq1w,
+ .sysc = am43xx_hdq1w_sysc,
+ .reset = omap_hdq1w_reset,
+};
+
+static struct omap_hwmod am43xx_hdq1w_hwmod = {
+ .name = hdq1w,
+ .class = am43xx_hdq1w_hwmod_class,
+ .clkdm_name = l4ls_clkdm,
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM43XX_CM_PER_HDQ1W_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
/* Interfaces */
static struct omap_hwmod_ocp_if am43xx_l3_main__l4_hs = {
.master = am33xx_l3_main_hwmod,
@@ -654,6 +681,14 @@ static struct omap_hwmod_ocp_if am43xx_l3_s__qspi = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
+/* l4_per - hdq1w */
+static struct omap_hwmod_ocp_if am43xx_l4_ls__hdq1w = {
+ .master = am33xx_l4_ls_hwmod,
+ .slave = am43xx_hdq1w_hwmod,
+ .clk= l4ls_gclk,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = {
am33xx_l4_wkup__synctimer,
am43xx_l4_ls__timer8,
@@ -748,6 +783,7 @@ static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[]
__initdata = {
am43xx_l4_ls__ocp2scp1,
am43xx_l3_s__usbotgss0,
am43xx_l3_s__usbotgss1,
+ am43xx_l4_ls__hdq1w,
NULL,
};
diff --git a/arch/arm/mach-omap2/prcm43xx.h b/arch/arm/mach-omap2/prcm43xx.h
index 7785be9..cabff53 100644
--- a/arch/arm/mach-omap2/prcm43xx.h
+++ b/arch/arm/mach-omap2/prcm43xx.h
@@ -142,5 +142,6 @@
#define AM43XX_CM_PER_USBPHYOCP2SCP0_CLKCTRL_OFFSET0x05B8
#define AM43XX_CM_PER_USB_OTG_SS1_CLKCTRL_OFFSET0x0268
#define AM43XX_CM_PER_USBPHYOCP2SCP1_CLKCTRL_OFFSET0x05C0
+#define AM43XX_CM_PER_HDQ1W_CLKCTRL_OFFSET 0x04a0
#endif
--
1.7.9.5
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[Resend/PATCH] arm: dts: dra7: Add qspi device.
These add device tree entry for qspi controller driver on dra7-evm.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
Depends on sricharan's irq crossbar.
arch/arm/boot/dts/dra7-evm.dts | 80
arch/arm/boot/dts/dra7.dtsi| 14 +++
2 files changed, 94 insertions(+)
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index 5babba0..62f4256 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -93,6 +93,21 @@
0x24c (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */
;
};
+
+ qspi1_pins: pinmux_qspi1_pins {
+ pinctrl-single,pins =
+ 0x4c (PIN_INPUT | MUX_MODE1) /* gpmc_a3.qspi1_cs2 */
+ 0x50 (PIN_INPUT | MUX_MODE1) /* gpmc_a4.qspi1_cs3 */
+ 0x74 (PIN_INPUT | MUX_MODE1) /* gpmc_a13.qspi1_rtclk */
+ 0x78 (PIN_INPUT | MUX_MODE1) /* gpmc_a14.qspi1_d3 */
+ 0x7c (PIN_INPUT | MUX_MODE1) /* gpmc_a15.qspi1_d2 */
+ 0x80 (PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d1 */
+ 0x84 (PIN_INPUT | MUX_MODE1) /* gpmc_a17.qspi1_d0 */
+ 0x88 (PIN_INPUT | MUX_MODE1) /* qpmc_a18.qspi1_sclk */
+ 0xb8 (PIN_INPUT_PULLUP | MUX_MODE1) /*
gpmc_cs2.qspi1_cs0 */
+ 0xbc (PIN_INPUT_PULLUP | MUX_MODE1) /*
gpmc_cs3.qspi1_cs1 */
+ ;
+ };
};
i2c1 {
@@ -273,3 +288,68 @@
cpu0 {
cpu0-supply = smps123_reg;
};
+
+qspi {
+ status = okay;
+ pinctrl-names = default;
+ pinctrl-0 = qspi1_pins;
+
+ spi-max-frequency = 4800;
+ m25p80@0 {
+ compatible = s25fl256s1;
+ spi-max-frequency = 4800;
+ reg = 0;
+ spi-tx-bus-width = 1;
+ spi-rx-bus-width = 4;
+ spi-cpol;
+ spi-cpha;
+ #address-cells = 1;
+ #size-cells = 1;
+
+ /* MTD partition table.
+* The ROM checks the first four physical blocks
+* for a valid file to boot and the flash here is
+* 64KiB block size.
+*/
+ partition@0 {
+ label = QSPI.SPL;
+ reg = 0x 0x1;
+ };
+ partition@1 {
+ label = QSPI.SPL.backup1;
+ reg = 0x0001 0x0001;
+ };
+ partition@2 {
+ label = QSPI.SPL.backup2;
+ reg = 0x0002 0x0001;
+ };
+ partition@3 {
+ label = QSPI.SPL.backup3;
+ reg = 0x0003 0x0001;
+ };
+ partition@4 {
+ label = QSPI.u-boot;
+ reg = 0x0004 0x0010;
+ };
+ partition@5 {
+ label = QSPI.u-boot-spl-os;
+ reg = 0x0014 0x0001;
+ };
+ partition@6 {
+ label = QSPI.u-boot-env;
+ reg = 0x0015 0x0001;
+ };
+ partition@7 {
+ label = QSPI.u-boot-env.backup1;
+ reg = 0x0016 0x001;
+ };
+ partition@8 {
+ label = QSPI.kernel;
+ reg = 0x0017 0x080;
+ };
+ partition@9 {
+ label = QSPI.file-system;
+ reg = 0x0097 0x0169;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index d93311a..a4557b4 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -798,6 +798,20 @@
dma-names = tx0, rx0;
status = disabled;
};
+
+ qspi: qspi@4b30 {
+ compatible = ti,dra7xxx-qspi;
+ reg = 0x4b30 0x100;
+ reg-names = qspi_base;
+ #address-cells = 1;
+ #size-cells = 0;
+ ti,hwmods = qspi;
+ clocks = qspi_gfclk_div;
+ clock-names = fck;
+ num-cs = 4;
+ interrupts = 0 343 0x4;
+ status = disabled;
+ };
};
crossbar_mpu: crossbar@4a02 {
--
1.7.9.5
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[PATCHv2] arm: dts: am33xx-clock: Fix ehrpwm tbclk data.
tbclk does not need to be a composite clock, we can simply
use gate clock for this purpose.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
v1-v2:
change compatible string according to mainline.
arch/arm/boot/dts/am33xx-clocks.dtsi | 30 ++
1 file changed, 6 insertions(+), 24 deletions(-)
diff --git a/arch/arm/boot/dts/am33xx-clocks.dtsi
b/arch/arm/boot/dts/am33xx-clocks.dtsi
index 9ccfe50..712edce 100644
--- a/arch/arm/boot/dts/am33xx-clocks.dtsi
+++ b/arch/arm/boot/dts/am33xx-clocks.dtsi
@@ -96,47 +96,29 @@
clock-div = 1;
};
- ehrpwm0_gate_tbclk: ehrpwm0_gate_tbclk {
+ ehrpwm0_tbclk: ehrpwm0_tbclk@44e10664 {
#clock-cells = 0;
- compatible = ti,composite-no-wait-gate-clock;
+ compatible = ti,gate-clock;
clocks = dpll_per_m2_ck;
ti,bit-shift = 0;
reg = 0x0664;
};
- ehrpwm0_tbclk: ehrpwm0_tbclk {
- #clock-cells = 0;
- compatible = ti,composite-clock;
- clocks = ehrpwm0_gate_tbclk;
- };
-
- ehrpwm1_gate_tbclk: ehrpwm1_gate_tbclk {
+ ehrpwm1_tbclk: ehrpwm1_tbclk@44e10664 {
#clock-cells = 0;
- compatible = ti,composite-no-wait-gate-clock;
+ compatible = ti,gate-clock;
clocks = dpll_per_m2_ck;
ti,bit-shift = 1;
reg = 0x0664;
};
- ehrpwm1_tbclk: ehrpwm1_tbclk {
- #clock-cells = 0;
- compatible = ti,composite-clock;
- clocks = ehrpwm1_gate_tbclk;
- };
-
- ehrpwm2_gate_tbclk: ehrpwm2_gate_tbclk {
+ ehrpwm2_tbclk: ehrpwm2_tbclk@44e10664 {
#clock-cells = 0;
- compatible = ti,composite-no-wait-gate-clock;
+ compatible = ti,gate-clock;
clocks = dpll_per_m2_ck;
ti,bit-shift = 2;
reg = 0x0664;
};
-
- ehrpwm2_tbclk: ehrpwm2_tbclk {
- #clock-cells = 0;
- compatible = ti,composite-clock;
- clocks = ehrpwm2_gate_tbclk;
- };
};
prcm_clocks {
clk_32768_ck: clk_32768_ck {
--
1.7.9.5
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[PATCHv2] arm: dts: am43x-clock: add tbclk data for ehrpwm.
We need tbclk clock data for the functioning of ehrpwm
module. Hence, populating the required clock information
in clock dts file.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
v1-v2:
change compatible according to mainline.
arch/arm/boot/dts/am43xx-clocks.dtsi | 48 ++
drivers/clk/ti/clk-43xx.c|6 +
2 files changed, 54 insertions(+)
diff --git a/arch/arm/boot/dts/am43xx-clocks.dtsi
b/arch/arm/boot/dts/am43xx-clocks.dtsi
index 142009c..401 100644
--- a/arch/arm/boot/dts/am43xx-clocks.dtsi
+++ b/arch/arm/boot/dts/am43xx-clocks.dtsi
@@ -87,6 +87,54 @@
clock-mult = 1;
clock-div = 1;
};
+
+ ehrpwm0_tbclk: ehrpwm0_tbclk@44e10664 {
+ #clock-cells = 0;
+ compatible = ti,gate-clock;
+ clocks = dpll_per_m2_ck;
+ ti,bit-shift = 0;
+ reg = 0x0664;
+ };
+
+ ehrpwm1_tbclk: ehrpwm1_tbclk@44e10664 {
+ #clock-cells = 0;
+ compatible = ti,gate-clock;
+ clocks = dpll_per_m2_ck;
+ ti,bit-shift = 1;
+ reg = 0x0664;
+ };
+
+ ehrpwm2_tbclk: ehrpwm2_tbclk@44e10664 {
+ #clock-cells = 0;
+ compatible = ti,gate-clock;
+ clocks = dpll_per_m2_ck;
+ ti,bit-shift = 2;
+ reg = 0x0664;
+ };
+
+ ehrpwm3_tbclk: ehrpwm3_tbclk@44e10664 {
+ #clock-cells = 0;
+ compatible = ti,gate-clock;
+ clocks = dpll_per_m2_ck;
+ ti,bit-shift = 3;
+ reg = 0x0664;
+ };
+
+ ehrpwm4_tbclk: ehrpwm4_tbclk@44e10664 {
+ #clock-cells = 0;
+ compatible = ti,gate-clock;
+ clocks = dpll_per_m2_ck;
+ ti,bit-shift = 4;
+ reg = 0x0664;
+ };
+
+ ehrpwm5_tbclk: ehrpwm5_tbclk@44e10664 {
+ #clock-cells = 0;
+ compatible = ti,gate-clock;
+ clocks = dpll_per_m2_ck;
+ ti,bit-shift = 5;
+ reg = 0x0664;
+ };
};
prcm_clocks {
clk_32768_ck: clk_32768_ck {
diff --git a/drivers/clk/ti/clk-43xx.c b/drivers/clk/ti/clk-43xx.c
index 67c8de5..527a43d 100644
--- a/drivers/clk/ti/clk-43xx.c
+++ b/drivers/clk/ti/clk-43xx.c
@@ -105,6 +105,12 @@ static struct ti_dt_clk am43xx_clks[] = {
DT_CLK(NULL, func_12m_clk, func_12m_clk),
DT_CLK(NULL, vtp_clk_div, vtp_clk_div),
DT_CLK(NULL, usbphy_32khz_clkmux, usbphy_32khz_clkmux),
+ DT_CLK(48300200.ehrpwm, tbclk, ehrpwm0_tbclk),
+ DT_CLK(48302200.ehrpwm, tbclk, ehrpwm1_tbclk),
+ DT_CLK(48304200.ehrpwm, tbclk, ehrpwm2_tbclk),
+ DT_CLK(48306200.ehrpwm, tbclk, ehrpwm3_tbclk),
+ DT_CLK(48308200.ehrpwm, tbclk, ehrpwm4_tbclk),
+ DT_CLK(4830a200.ehrpwm, tbclk, ehrpwm5_tbclk),
{ .node_name = NULL },
};
--
1.7.9.5
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[PATCHv3] arm: dts: am43x-clock: add tbclk data for ehrpwm.
We need tbclk clock data for the functioning of ehrpwm
module. Hence, populating the required clock information
in clock dts file.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
v2-v3
- correct bitshifting
arch/arm/boot/dts/am43xx-clocks.dtsi | 48 ++
drivers/clk/ti/clk-43xx.c|6 +
2 files changed, 54 insertions(+)
diff --git a/arch/arm/boot/dts/am43xx-clocks.dtsi
b/arch/arm/boot/dts/am43xx-clocks.dtsi
index 142009c..42d7b1f 100644
--- a/arch/arm/boot/dts/am43xx-clocks.dtsi
+++ b/arch/arm/boot/dts/am43xx-clocks.dtsi
@@ -87,6 +87,54 @@
clock-mult = 1;
clock-div = 1;
};
+
+ ehrpwm0_tbclk: ehrpwm0_tbclk {
+ #clock-cells = 0;
+ compatible = ti,gate-clock;
+ clocks = dpll_per_m2_ck;
+ ti,bit-shift = 0;
+ reg = 0x0664;
+ };
+
+ ehrpwm1_tbclk: ehrpwm1_tbclk {
+ #clock-cells = 0;
+ compatible = ti,gate-clock;
+ clocks = dpll_per_m2_ck;
+ ti,bit-shift = 1;
+ reg = 0x0664;
+ };
+
+ ehrpwm2_tbclk: ehrpwm2_tbclk {
+ #clock-cells = 0;
+ compatible = ti,gate-clock;
+ clocks = dpll_per_m2_ck;
+ ti,bit-shift = 2;
+ reg = 0x0664;
+ };
+
+ ehrpwm3_tbclk: ehrpwm3_tbclk {
+ #clock-cells = 0;
+ compatible = ti,gate-clock;
+ clocks = dpll_per_m2_ck;
+ ti,bit-shift = 4;
+ reg = 0x0664;
+ };
+
+ ehrpwm4_tbclk: ehrpwm4_tbclk {
+ #clock-cells = 0;
+ compatible = ti,gate-clock;
+ clocks = dpll_per_m2_ck;
+ ti,bit-shift = 5;
+ reg = 0x0664;
+ };
+
+ ehrpwm5_tbclk: ehrpwm5_tbclk {
+ #clock-cells = 0;
+ compatible = ti,gate-clock;
+ clocks = dpll_per_m2_ck;
+ ti,bit-shift = 6;
+ reg = 0x0664;
+ };
};
prcm_clocks {
clk_32768_ck: clk_32768_ck {
diff --git a/drivers/clk/ti/clk-43xx.c b/drivers/clk/ti/clk-43xx.c
index 67c8de5..527a43d 100644
--- a/drivers/clk/ti/clk-43xx.c
+++ b/drivers/clk/ti/clk-43xx.c
@@ -105,6 +105,12 @@ static struct ti_dt_clk am43xx_clks[] = {
DT_CLK(NULL, func_12m_clk, func_12m_clk),
DT_CLK(NULL, vtp_clk_div, vtp_clk_div),
DT_CLK(NULL, usbphy_32khz_clkmux, usbphy_32khz_clkmux),
+ DT_CLK(48300200.ehrpwm, tbclk, ehrpwm0_tbclk),
+ DT_CLK(48302200.ehrpwm, tbclk, ehrpwm1_tbclk),
+ DT_CLK(48304200.ehrpwm, tbclk, ehrpwm2_tbclk),
+ DT_CLK(48306200.ehrpwm, tbclk, ehrpwm3_tbclk),
+ DT_CLK(48308200.ehrpwm, tbclk, ehrpwm4_tbclk),
+ DT_CLK(4830a200.ehrpwm, tbclk, ehrpwm5_tbclk),
{ .node_name = NULL },
};
--
1.7.9.5
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[Resend/PATCH] arm: dts: am43x-epos: Add qspi device.
This patch adds qspi nodes for am43xx SOC devices.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
Note,
checpatch gives 1 warning on flash compatible string
mx66l51235l. This flash is supported in m25p80 driver and
the driver is used for other flash devices also. Hence, each
flash compatible is not described in[1], but a genric example
is shown using spansion flash device.
[1]:
Documentation/devicetree/bindings/mtd/m25p80.txt
arch/arm/boot/dts/am4372.dtsi| 11 ++
arch/arm/boot/dts/am43x-epos-evm.dts | 63 ++
2 files changed, 74 insertions(+)
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index 36d523a..49633ff 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -735,6 +735,17 @@
#size-cells = 1;
status = disabled;
};
+
+ qspi: qspi@4790 {
+ compatible = ti,am4372-qspi;
+ reg = 0x4790 0x100;
+ #address-cells = 1;
+ #size-cells = 0;
+ ti,hwmods = qspi;
+ interrupts = 0 138 0x4;
+ num-cs = 4;
+ status = disabled;
+ };
};
};
diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts
b/arch/arm/boot/dts/am43x-epos-evm.dts
index 167dbc8..25cd07c 100644
--- a/arch/arm/boot/dts/am43x-epos-evm.dts
+++ b/arch/arm/boot/dts/am43x-epos-evm.dts
@@ -138,6 +138,17 @@
0x160 (PIN_INPUT | MUX_MODE7) /*
spi0_cs1.gpio0_6 */
;
};
+
+ qspi1_default: qspi1_default {
+ pinctrl-single,pins =
+ 0x7c (PIN_INPUT_PULLUP | MUX_MODE3)
+ 0x88 (PIN_INPUT_PULLUP | MUX_MODE2)
+ 0x90 (PIN_INPUT_PULLUP | MUX_MODE3)
+ 0x94 (PIN_INPUT_PULLUP | MUX_MODE3)
+ 0x98 (PIN_INPUT_PULLUP | MUX_MODE3)
+ 0x9c (PIN_INPUT_PULLUP | MUX_MODE3)
+ ;
+ };
};
matrix_keypad: matrix_keypad@0 {
@@ -367,3 +378,55 @@
pinctrl-0 = spi1_pins;
status = okay;
};
+
+qspi {
+ status = okay;
+ pinctrl-names = default;
+ pinctrl-0 = qspi1_default;
+
+ spi-max-frequency = 4800;
+ m25p80@0 {
+ compatible = mx66l51235l;
+ spi-max-frequency = 4800;
+ reg = 0;
+ spi-cpol;
+ spi-cpha;
+ spi-tx-bus-width = 1;
+ spi-rx-bus-width = 4;
+ #address-cells = 1;
+ #size-cells = 1;
+
+ /* MTD partition table.
+* The ROM checks the first 512KiB
+* for a valid file to boot(XIP).
+*/
+ partition@0 {
+ label = QSPI.U_BOOT;
+ reg = 0x 0x8;
+ };
+ partition@1 {
+ label = QSPI.U_BOOT.backup;
+ reg = 0x0008 0x0008;
+ };
+ partition@2 {
+ label = QSPI.U-BOOT-SPL_OS;
+ reg = 0x0010 0x0001;
+ };
+ partition@3 {
+ label = QSPI.U_BOOT_ENV;
+ reg = 0x0011 0x0001;
+ };
+ partition@4 {
+ label = QSPI.U-BOOT-ENV.backup;
+ reg = 0x0012 0x0001;
+ };
+ partition@5 {
+ label = QSPI.KERNEL;
+ reg = 0x0013 0x080;
+ };
+ partition@6 {
+ label = QSPI.FILESYSTEM;
+ reg = 0x0093 0x36D;
+ };
+ };
+};
--
1.7.9.5
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[PATCH] arm: dts: am33xx-clock: Fix ehrpwm tbclk data.
tbclk does not need to be a composite clock, we can simply
use gate clock for this purpose.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
arch/arm/boot/dts/am33xx-clocks.dtsi | 42 ++
1 file changed, 12 insertions(+), 30 deletions(-)
diff --git a/arch/arm/boot/dts/am33xx-clocks.dtsi
b/arch/arm/boot/dts/am33xx-clocks.dtsi
index 9ccfe50..a45d27f 100644
--- a/arch/arm/boot/dts/am33xx-clocks.dtsi
+++ b/arch/arm/boot/dts/am33xx-clocks.dtsi
@@ -96,46 +96,28 @@
clock-div = 1;
};
- ehrpwm0_gate_tbclk: ehrpwm0_gate_tbclk {
+ ehrpwm0_tbclk: ehrpwm0_tbclk@44e10664 {
#clock-cells = 0;
- compatible = ti,composite-no-wait-gate-clock;
+ compatible = gate-clock;
clocks = dpll_per_m2_ck;
- ti,bit-shift = 0;
- reg = 0x0664;
+ bit-shift = 0;
+ reg = 0x44e10664 0x4;
};
- ehrpwm0_tbclk: ehrpwm0_tbclk {
+ ehrpwm1_tbclk: ehrpwm1_tbclk@44e10664 {
#clock-cells = 0;
- compatible = ti,composite-clock;
- clocks = ehrpwm0_gate_tbclk;
- };
-
- ehrpwm1_gate_tbclk: ehrpwm1_gate_tbclk {
- #clock-cells = 0;
- compatible = ti,composite-no-wait-gate-clock;
+ compatible = gate-clock;
clocks = dpll_per_m2_ck;
- ti,bit-shift = 1;
- reg = 0x0664;
- };
-
- ehrpwm1_tbclk: ehrpwm1_tbclk {
- #clock-cells = 0;
- compatible = ti,composite-clock;
- clocks = ehrpwm1_gate_tbclk;
+ bit-shift = 1;
+ reg = 0x44e10664 0x4;
};
- ehrpwm2_gate_tbclk: ehrpwm2_gate_tbclk {
+ ehrpwm2_tbclk: ehrpwm2_tbclk@44e10664 {
#clock-cells = 0;
- compatible = ti,composite-no-wait-gate-clock;
+ compatible = gate-clock;
clocks = dpll_per_m2_ck;
- ti,bit-shift = 2;
- reg = 0x0664;
- };
-
- ehrpwm2_tbclk: ehrpwm2_tbclk {
- #clock-cells = 0;
- compatible = ti,composite-clock;
- clocks = ehrpwm2_gate_tbclk;
+ bit-shift = 2;
+ reg = 0x44e10664 0x4;
};
};
prcm_clocks {
--
1.7.9.5
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[PATCH] arm: dts: am43x-clock: add tbclk data for ehrpwm.
We need tbclk clock data for the functioning of ehrpwm
module. Hence, populating the required clock information
in clock dts file.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
arch/arm/boot/dts/am43xx-clocks.dtsi | 48 ++
drivers/clk/ti/clk-43xx.c|6 +
2 files changed, 54 insertions(+)
diff --git a/arch/arm/boot/dts/am43xx-clocks.dtsi
b/arch/arm/boot/dts/am43xx-clocks.dtsi
index 142009c..54f68e8 100644
--- a/arch/arm/boot/dts/am43xx-clocks.dtsi
+++ b/arch/arm/boot/dts/am43xx-clocks.dtsi
@@ -87,6 +87,54 @@
clock-mult = 1;
clock-div = 1;
};
+
+ ehrpwm0_tbclk: ehrpwm0_tbclk@44e10664 {
+ #clock-cells = 0;
+ compatible = gate-clock;
+ clocks = dpll_per_m2_ck;
+ bit-shift = 0;
+ reg = 0x44e10664 0x4;
+ };
+
+ ehrpwm1_tbclk: ehrpwm1_tbclk@44e10664 {
+ #clock-cells = 0;
+ compatible = gate-clock;
+ clocks = dpll_per_m2_ck;
+ bit-shift = 1;
+ reg = 0x44e10664 0x4;
+ };
+
+ ehrpwm2_tbclk: ehrpwm2_tbclk@44e10664 {
+ #clock-cells = 0;
+ compatible = gate-clock;
+ clocks = dpll_per_m2_ck;
+ bit-shift = 2;
+ reg = 0x44e10664 0x4;
+ };
+
+ ehrpwm3_tbclk: ehrpwm3_tbclk@44e10664 {
+ #clock-cells = 0;
+ compatible = gate-clock;
+ clocks = dpll_per_m2_ck;
+ bit-shift = 3;
+ reg = 0x44e10664 0x4;
+ };
+
+ ehrpwm4_tbclk: ehrpwm4_tbclk@44e10664 {
+ #clock-cells = 0;
+ compatible = gate-clock;
+ clocks = dpll_per_m2_ck;
+ bit-shift = 4;
+ reg = 0x44e10664 0x4;
+ };
+
+ ehrpwm5_tbclk: ehrpwm5_tbclk@44e10664 {
+ #clock-cells = 0;
+ compatible = gate-clock;
+ clocks = dpll_per_m2_ck;
+ bit-shift = 5;
+ reg = 0x44e10664 0x4;
+ };
};
prcm_clocks {
clk_32768_ck: clk_32768_ck {
diff --git a/drivers/clk/ti/clk-43xx.c b/drivers/clk/ti/clk-43xx.c
index 67c8de5..527a43d 100644
--- a/drivers/clk/ti/clk-43xx.c
+++ b/drivers/clk/ti/clk-43xx.c
@@ -105,6 +105,12 @@ static struct ti_dt_clk am43xx_clks[] = {
DT_CLK(NULL, func_12m_clk, func_12m_clk),
DT_CLK(NULL, vtp_clk_div, vtp_clk_div),
DT_CLK(NULL, usbphy_32khz_clkmux, usbphy_32khz_clkmux),
+ DT_CLK(48300200.ehrpwm, tbclk, ehrpwm0_tbclk),
+ DT_CLK(48302200.ehrpwm, tbclk, ehrpwm1_tbclk),
+ DT_CLK(48304200.ehrpwm, tbclk, ehrpwm2_tbclk),
+ DT_CLK(48306200.ehrpwm, tbclk, ehrpwm3_tbclk),
+ DT_CLK(48308200.ehrpwm, tbclk, ehrpwm4_tbclk),
+ DT_CLK(4830a200.ehrpwm, tbclk, ehrpwm5_tbclk),
{ .node_name = NULL },
};
--
1.7.9.5
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[PATCH] arm: dts: am43x-clock: add tbclk data for ehrpwm.
We need tblclk clock data for the functioning of ehrpwm
module. Hence, populating the required clock information
in clock dts file.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
arch/arm/boot/dts/am43xx-clocks.dtsi | 84 ++
drivers/clk/ti/clk-43xx.c|6 +++
2 files changed, 90 insertions(+)
diff --git a/arch/arm/boot/dts/am43xx-clocks.dtsi
b/arch/arm/boot/dts/am43xx-clocks.dtsi
index 142009c..869f9a5 100644
--- a/arch/arm/boot/dts/am43xx-clocks.dtsi
+++ b/arch/arm/boot/dts/am43xx-clocks.dtsi
@@ -87,6 +87,90 @@
clock-mult = 1;
clock-div = 1;
};
+
+ ehrpwm0_gate_tbclk: ehrpwm0_gate_tbclk {
+ #clock-cells = 0;
+ compatible = ti,composite-no-wait-gate-clock;
+ clocks = dpll_per_m2_ck;
+ ti,bit-shift = 0;
+ reg = 0x0664;
+ };
+
+ ehrpwm0_tbclk: ehrpwm0_tbclk {
+ #clock-cells = 0;
+ compatible = ti,composite-clock;
+ clocks = ehrpwm0_gate_tbclk;
+ };
+
+ ehrpwm1_gate_tbclk: ehrpwm1_gate_tbclk {
+ #clock-cells = 0;
+ compatible = ti,composite-no-wait-gate-clock;
+ clocks = dpll_per_m2_ck;
+ ti,bit-shift = 1;
+ reg = 0x0664;
+ };
+
+ ehrpwm1_tbclk: ehrpwm1_tbclk {
+ #clock-cells = 0;
+ compatible = ti,composite-clock;
+ clocks = ehrpwm1_gate_tbclk;
+ };
+
+ ehrpwm2_gate_tbclk: ehrpwm2_gate_tbclk {
+ #clock-cells = 0;
+ compatible = ti,composite-no-wait-gate-clock;
+ clocks = dpll_per_m2_ck;
+ ti,bit-shift = 2;
+ reg = 0x0664;
+ };
+
+ ehrpwm2_tbclk: ehrpwm2_tbclk {
+ #clock-cells = 0;
+ compatible = ti,composite-clock;
+ clocks = ehrpwm2_gate_tbclk;
+ };
+
+ ehrpwm3_gate_tbclk: ehrpwm3_gate_tbclk {
+ #clock-cells = 0;
+ compatible = ti,composite-no-wait-gate-clock;
+ clocks = dpll_per_m2_ck;
+ ti,bit-shift = 2;
+ reg = 0x0664;
+ };
+
+ ehrpwm3_tbclk: ehrpwm3_tbclk {
+ #clock-cells = 0;
+ compatible = ti,composite-clock;
+ clocks = ehrpwm3_gate_tbclk;
+ };
+
+ ehrpwm4_gate_tbclk: ehrpwm4_gate_tbclk {
+ #clock-cells = 0;
+ compatible = ti,composite-no-wait-gate-clock;
+ clocks = dpll_per_m2_ck;
+ ti,bit-shift = 2;
+ reg = 0x0664;
+ };
+
+ ehrpwm4_tbclk: ehrpwm4_tbclk {
+ #clock-cells = 0;
+ compatible = ti,composite-clock;
+ clocks = ehrpwm4_gate_tbclk;
+ };
+
+ ehrpwm5_gate_tbclk: ehrpwm5_gate_tbclk {
+ #clock-cells = 0;
+ compatible = ti,composite-no-wait-gate-clock;
+ clocks = dpll_per_m2_ck;
+ ti,bit-shift = 2;
+ reg = 0x0664;
+ };
+
+ ehrpwm5_tbclk: ehrpwm5_tbclk {
+ #clock-cells = 0;
+ compatible = ti,composite-clock;
+ clocks = ehrpwm5_gate_tbclk;
+ };
};
prcm_clocks {
clk_32768_ck: clk_32768_ck {
diff --git a/drivers/clk/ti/clk-43xx.c b/drivers/clk/ti/clk-43xx.c
index 67c8de5..5413a6a 100644
--- a/drivers/clk/ti/clk-43xx.c
+++ b/drivers/clk/ti/clk-43xx.c
@@ -105,6 +105,12 @@ static struct ti_dt_clk am43xx_clks[] = {
DT_CLK(NULL, func_12m_clk, func_12m_clk),
DT_CLK(NULL, vtp_clk_div, vtp_clk_div),
DT_CLK(NULL, usbphy_32khz_clkmux, usbphy_32khz_clkmux),
+ DT_CLK(48300200.ehrpwm, tbclk, ehrpwm0_tbclk),
+ DT_CLK(48302200.ehrpwm, tbclk, ehrpwm1_tbclk),
+ DT_CLK(48304200.ehrpwm, tbclk, ehrpwm2_tbclk),
+ DT_CLK(48306200.ehrpwm, tbclk, ehrpwm0_tbclk),
+ DT_CLK(48308200.ehrpwm, tbclk, ehrpwm1_tbclk),
+ DT_CLK(4830a200.ehrpwm, tbclk, ehrpwm2_tbclk),
{ .node_name = NULL },
};
--
1.7.9.5
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[PATCH 2/5] w1: omap_hdq: Add compatible property for omap hdq driver.
Add compatible property for omap hdq driver.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
.../devicetree/bindings/hdq1w/omap_hdq.txt | 20
drivers/w1/masters/omap_hdq.c |8
2 files changed, 28 insertions(+)
create mode 100644 Documentation/devicetree/bindings/hdq1w/omap_hdq.txt
diff --git a/Documentation/devicetree/bindings/hdq1w/omap_hdq.txt
b/Documentation/devicetree/bindings/hdq1w/omap_hdq.txt
new file mode 100644
index 000..a7e011e
--- /dev/null
+++ b/Documentation/devicetree/bindings/hdq1w/omap_hdq.txt
@@ -0,0 +1,20 @@
+HDQ/1w for OMAP platforms
+
+Required properties :
+- compatible : Must be ti,am43xx-hdq.
+- ti,hwmods : Must be hdq1w.
+- reg: Should contain register location and length.
+- interrupts: Should contain interrupt.
+- clock: Clock input to HDQ1w controller.
+
+Example:
+
+ hdq: hdq@48347000 {
+ compatible = ti,am43xx-hdq;
+ reg = 0x48347000 0x1000;
+ interrupts = GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH;
+ clocks = func_12m_clk;
+ clock-names = fck;
+ ti,hwmods = hdq1w;
+ status = disabled;
+ };
diff --git a/drivers/w1/masters/omap_hdq.c b/drivers/w1/masters/omap_hdq.c
index 0a7bf7f..ec36bee 100644
--- a/drivers/w1/masters/omap_hdq.c
+++ b/drivers/w1/masters/omap_hdq.c
@@ -17,6 +17,7 @@
#include linux/io.h
#include linux/sched.h
#include linux/pm_runtime.h
+#include linux/of.h
#include ../w1.h
#include ../w1_int.h
@@ -73,11 +74,18 @@ struct hdq_data {
static int omap_hdq_probe(struct platform_device *pdev);
static int omap_hdq_remove(struct platform_device *pdev);
+static const struct of_device_id omap_hdq_dt_match[] = {
+ { .compatible = ti,am43xx-hdq},
+ {},
+};
+MODULE_DEVICE_TABLE(of, omap_hdq_dt_match);
+
static struct platform_driver omap_hdq_driver = {
.probe =omap_hdq_probe,
.remove = omap_hdq_remove,
.driver = {
.name = omap_hdq,
+ .of_match_table = of_match_ptr(omap_hdq_dt_match),
},
};
--
1.7.9.5
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[PATCH 0/5] AM437x: HDQ/1wire protocol
This series adds support for HDQ/1w protocol driver for am43x epos evm where it can be used for measuring the temperature of a slave device connected to a particular header. Tested the patch series on AM437x, hdq master and slave devices are getting registered and interrupts are getting triggered for break and tx conditions. Sourav Poddar (5): drivers: w1: omap_hdq: cleanup and bug fixes. w1: omap_hdq: Add compatible property for omap hdq driver. arm: mach-omap2: selective device build from the platform code. arm: dts: am4372: Add hdq device tree data. arm: hwmod: am437x: Add hwmod data for hdq1w. .../devicetree/bindings/hdq1w/omap_hdq.txt | 20 + arch/arm/boot/dts/am4372.dtsi | 10 +++ arch/arm/boot/dts/am43x-epos-evm.dts | 12 +++ arch/arm/mach-omap2/hdq1w.c|2 + arch/arm/mach-omap2/omap_hwmod_43xx_data.c | 36 arch/arm/mach-omap2/prcm43xx.h |1 + drivers/w1/masters/omap_hdq.c | 93 7 files changed, 157 insertions(+), 17 deletions(-) create mode 100644 Documentation/devicetree/bindings/hdq1w/omap_hdq.txt -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 3/5] arm: omap2: skip device build from platform code for dt.
For SOCs with dt enabled, device should be build through device tree.
Prevent device build call from platform code, if device tree is
enabled.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
arch/arm/mach-omap2/hdq1w.c |2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/mach-omap2/hdq1w.c b/arch/arm/mach-omap2/hdq1w.c
index cbc8e3c..f78b4a1 100644
--- a/arch/arm/mach-omap2/hdq1w.c
+++ b/arch/arm/mach-omap2/hdq1w.c
@@ -76,6 +76,7 @@ int omap_hdq1w_reset(struct omap_hwmod *oh)
return 0;
}
+#ifndef CONFIG_OF
static int __init omap_init_hdq(void)
{
int id = -1;
@@ -95,3 +96,4 @@ static int __init omap_init_hdq(void)
return 0;
}
omap_arch_initcall(omap_init_hdq);
+#endif
--
1.7.9.5
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[PATCH 1/5] drivers: w1: omap_hdq: cleanup and bug fixes.
The patch adds the following to the omap hdq driver.
1. HDQ Device reset call in probe.
2. Enabling '1 wire mode' and checking for presence pulse bit.
3. Proper disabling and enabling of interrupts during read path.
4. Add re-initialization code during SKIP ROM command execution.
5. Miscellaneous cleanup(formatting, return error checks).
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
drivers/w1/masters/omap_hdq.c | 85 -
1 file changed, 68 insertions(+), 17 deletions(-)
diff --git a/drivers/w1/masters/omap_hdq.c b/drivers/w1/masters/omap_hdq.c
index 9900e8e..0a7bf7f 100644
--- a/drivers/w1/masters/omap_hdq.c
+++ b/drivers/w1/masters/omap_hdq.c
@@ -27,21 +27,22 @@
#define OMAP_HDQ_TX_DATA 0x04
#define OMAP_HDQ_RX_DATA 0x08
#define OMAP_HDQ_CTRL_STATUS 0x0c
-#define OMAP_HDQ_CTRL_STATUS_INTERRUPTMASK (16)
-#define OMAP_HDQ_CTRL_STATUS_CLOCKENABLE (15)
-#define OMAP_HDQ_CTRL_STATUS_GO(14)
-#define OMAP_HDQ_CTRL_STATUS_INITIALIZATION(12)
-#define OMAP_HDQ_CTRL_STATUS_DIR (11)
-#define OMAP_HDQ_CTRL_STATUS_MODE (10)
+#define OMAP_HDQ_CTRL_STATUS_INTERRUPTMASK (1 6)
+#define OMAP_HDQ_CTRL_STATUS_CLOCKENABLE (1 5)
+#define OMAP_HDQ_CTRL_STATUS_PRESENCE (1 3)
+#define OMAP_HDQ_CTRL_STATUS_GO (1 4)
+#define OMAP_HDQ_CTRL_STATUS_INITIALIZATION(1 2)
+#define OMAP_HDQ_CTRL_STATUS_DIR (1 1)
+#define OMAP_HDQ_CTRL_STATUS_MODE (1 0)
#define OMAP_HDQ_INT_STATUS0x10
-#define OMAP_HDQ_INT_STATUS_TXCOMPLETE (12)
-#define OMAP_HDQ_INT_STATUS_RXCOMPLETE (11)
-#define OMAP_HDQ_INT_STATUS_TIMEOUT(10)
+#define OMAP_HDQ_INT_STATUS_TXCOMPLETE (1 2)
+#define OMAP_HDQ_INT_STATUS_RXCOMPLETE (1 1)
+#define OMAP_HDQ_INT_STATUS_TIMEOUT(1 0)
#define OMAP_HDQ_SYSCONFIG 0x14
-#define OMAP_HDQ_SYSCONFIG_SOFTRESET (11)
-#define OMAP_HDQ_SYSCONFIG_AUTOIDLE(10)
+#define OMAP_HDQ_SYSCONFIG_SOFTRESET (1 1)
+#define OMAP_HDQ_SYSCONFIG_AUTOIDLE(1 0)
#define OMAP_HDQ_SYSSTATUS 0x18
-#define OMAP_HDQ_SYSSTATUS_RESETDONE (10)
+#define OMAP_HDQ_SYSSTATUS_RESETDONE (1 0)
#define OMAP_HDQ_FLAG_CLEAR0
#define OMAP_HDQ_FLAG_SET 1
@@ -115,6 +116,15 @@ static inline u8 hdq_reg_merge(struct hdq_data *hdq_data,
u32 offset,
return new_val;
}
+static void hdq_disable_interrupt(struct hdq_data *hdq_data, u32 offset,
+ u8 mask)
+{
+ u32 ie;
+
+ ie = readl(hdq_data-hdq_base + offset);
+ writel(ie mask, hdq_data-hdq_base + offset);
+}
+
/*
* Wait for one or more bits in flag change.
* HDQ_FLAG_SET: wait until any bit in the flag is set.
@@ -263,8 +273,7 @@ static int _omap_hdq_reset(struct hdq_data *hdq_data)
* interrupt.
*/
hdq_reg_out(hdq_data, OMAP_HDQ_CTRL_STATUS,
- OMAP_HDQ_CTRL_STATUS_CLOCKENABLE |
- OMAP_HDQ_CTRL_STATUS_INTERRUPTMASK);
+ OMAP_HDQ_CTRL_STATUS_CLOCKENABLE);
/* wait for reset to complete */
ret = hdq_wait_for_flag(hdq_data, OMAP_HDQ_SYSSTATUS,
@@ -275,7 +284,8 @@ static int _omap_hdq_reset(struct hdq_data *hdq_data)
else {
hdq_reg_out(hdq_data, OMAP_HDQ_CTRL_STATUS,
OMAP_HDQ_CTRL_STATUS_CLOCKENABLE |
- OMAP_HDQ_CTRL_STATUS_INTERRUPTMASK);
+ OMAP_HDQ_CTRL_STATUS_INTERRUPTMASK |
+ OMAP_HDQ_CTRL_STATUS_MODE);
hdq_reg_out(hdq_data, OMAP_HDQ_SYSCONFIG,
OMAP_HDQ_SYSCONFIG_AUTOIDLE);
}
@@ -327,6 +337,18 @@ static int omap_hdq_break(struct hdq_data *hdq_data)
ret = -ETIMEDOUT;
goto out;
}
+
+ /*
+* check for the presence detect bit to get
+* set to show that the slave is responding
+*/
+ if (hdq_reg_in(hdq_data, OMAP_HDQ_CTRL_STATUS)
+ OMAP_HDQ_CTRL_STATUS_PRESENCE) {
+ dev_dbg(hdq_data-dev, Presence bit not set\n);
+ ret = -ETIMEDOUT;
+ goto out;
+ }
+
/*
* wait for both INIT and GO bits rerurn to zero.
* zero wait time expected for interrupt mode.
@@ -361,6 +383,8 @@ static int hdq_read_byte(struct hdq_data *hdq_data, u8 *val)
goto out;
}
+ hdq_data-hdq_irqstatus = 0;
+
if (!(hdq_data-hdq_irqstatus OMAP_HDQ_INT_STATUS_RXCOMPLETE)) {
hdq_reg_merge(hdq_data, OMAP_HDQ_CTRL_STATUS,
OMAP_HDQ_CTRL_STATUS_DIR | OMAP_HDQ_CTRL_STATUS_GO,
@@ -426,7 +450,8 @@ static int omap_hdq_get(struct hdq_data *hdq_data
[PATCH 5/5] arm: hwmod: am437x: Add hwmod data for hdq1w.
These adds hwmod data for hdq/1w driver.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
arch/arm/mach-omap2/omap_hwmod_43xx_data.c | 36
arch/arm/mach-omap2/prcm43xx.h |1 +
2 files changed, 37 insertions(+)
diff --git a/arch/arm/mach-omap2/omap_hwmod_43xx_data.c
b/arch/arm/mach-omap2/omap_hwmod_43xx_data.c
index 5c2cc80..3a8ca96 100644
--- a/arch/arm/mach-omap2/omap_hwmod_43xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_43xx_data.c
@@ -19,6 +19,7 @@
#include omap_hwmod.h
#include omap_hwmod_33xx_43xx_common_data.h
#include prcm43xx.h
+#include hdq1w.h
/* IP blocks */
static struct omap_hwmod am43xx_l4_hs_hwmod = {
@@ -415,6 +416,32 @@ static struct omap_hwmod am43xx_qspi_hwmod = {
},
};
+static struct omap_hwmod_class_sysconfig am43xx_hdq1w_sysc = {
+ .rev_offs = 0x,
+ .sysc_offs = 0x0014,
+ .syss_offs = 0x0018,
+ .sysc_flags = (SYSC_HAS_SOFTRESET),
+ .sysc_fields= omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class am43xx_hdq1w_hwmod_class = {
+ .name = hdq1w,
+ .sysc = am43xx_hdq1w_sysc,
+ .reset = omap_hdq1w_reset,
+};
+
+static struct omap_hwmod am43xx_hdq1w_hwmod = {
+ .name = hdq1w,
+ .class = am43xx_hdq1w_hwmod_class,
+ .clkdm_name = l4ls_clkdm,
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM43XX_CM_PER_HDQ1W_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
/* Interfaces */
static struct omap_hwmod_ocp_if am43xx_l3_main__l4_hs = {
.master = am33xx_l3_main_hwmod,
@@ -654,6 +681,14 @@ static struct omap_hwmod_ocp_if am43xx_l3_s__qspi = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
+/* l4_per - hdq1w */
+static struct omap_hwmod_ocp_if am43xx_l4_ls__hdq1w = {
+ .master = am33xx_l4_ls_hwmod,
+ .slave = am43xx_hdq1w_hwmod,
+ .clk= l4ls_gclk,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = {
am33xx_l4_wkup__synctimer,
am43xx_l4_ls__timer8,
@@ -748,6 +783,7 @@ static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[]
__initdata = {
am43xx_l4_ls__ocp2scp1,
am43xx_l3_s__usbotgss0,
am43xx_l3_s__usbotgss1,
+ am43xx_l4_ls__hdq1w,
NULL,
};
diff --git a/arch/arm/mach-omap2/prcm43xx.h b/arch/arm/mach-omap2/prcm43xx.h
index 7785be9..cabff53 100644
--- a/arch/arm/mach-omap2/prcm43xx.h
+++ b/arch/arm/mach-omap2/prcm43xx.h
@@ -142,5 +142,6 @@
#define AM43XX_CM_PER_USBPHYOCP2SCP0_CLKCTRL_OFFSET0x05B8
#define AM43XX_CM_PER_USB_OTG_SS1_CLKCTRL_OFFSET0x0268
#define AM43XX_CM_PER_USBPHYOCP2SCP1_CLKCTRL_OFFSET0x05C0
+#define AM43XX_CM_PER_HDQ1W_CLKCTRL_OFFSET 0x04a0
#endif
--
1.7.9.5
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[PATCH 4/5] arm: dts: am4372: Add hdq device tree data.
Add device tree nodes and pinmux for hdq/1wire on
am43x epos evm.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
arch/arm/boot/dts/am4372.dtsi| 10 ++
arch/arm/boot/dts/am43x-epos-evm.dts | 12
2 files changed, 22 insertions(+)
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index 36d523a..5f7c167 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -735,6 +735,16 @@
#size-cells = 1;
status = disabled;
};
+
+ hdq: hdq@48347000 {
+ compatible = ti,am43xx-hdq;
+ reg = 0x48347000 0x1000;
+ interrupts = GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH;
+ clocks = func_12m_clk;
+ clock-names = fck;
+ ti,hwmods = hdq1w;
+ status = disabled;
+ };
};
};
diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts
b/arch/arm/boot/dts/am43x-epos-evm.dts
index 167dbc8..e71ef1c 100644
--- a/arch/arm/boot/dts/am43x-epos-evm.dts
+++ b/arch/arm/boot/dts/am43x-epos-evm.dts
@@ -138,6 +138,12 @@
0x160 (PIN_INPUT | MUX_MODE7) /*
spi0_cs1.gpio0_6 */
;
};
+
+ hdq_pins: pinmux_hdq_pins {
+ pinctrl-single,pins =
+ 0x234 (PIN_INPUT_PULLUP | MUX_MODE1)/*
cam1_wen.hdq_gpio */
+ ;
+ };
};
matrix_keypad: matrix_keypad@0 {
@@ -367,3 +373,9 @@
pinctrl-0 = spi1_pins;
status = okay;
};
+
+hdq {
+ status = okay;
+ pinctrl-names = default;
+ pinctrl-0 = hdq_pins;
+};
--
1.7.9.5
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[PATCH] i2c: omap: Disable default probing of i2c devices for omap i2c.
I2c core supports defualt probing functionality for devices not registered through dt/board files. If there are any client driver registered, i2c core will try to check if there is any device present corresponding to the address supplied by the client driver. If the device is actually present and not registered, core will register it, else the device default probe will fail and we get a omap i2c controller specific timeout messages. For example, Using multi_v7_config on omap5-uevm, CONFIG_SENSORS_LM90 and CONFIG_ICS932S401 is the driver which is enabled and gets registered. I2c core tries to find a valid corresponding device on each of the address supplied by registered driver, but could not find anyone. Hence, keep dumping the controller timeout speciic message. The patch tends to disable class based instantiation, default probing will not be attempted by the i2c-core for omap i2c. Device will always get registered through device tree(dt case) and board files(for non dt cases). Tested i2c enumeration and data transfer(using i2c utilities) with linux-next master on the following boards using omap2plus_defconfig: * Omap3 beagle-Xm (for dt and non dt case) * omap4 panda * omap5-uevm * Dra7xx * Beaglebone white * Beaglebone black * am335x-evm * AM43xx epos evm Tested i2c enumeration with linux-next master(except omap5) on the following boards using multi_v7_defconfig: * Omap3 beagle-Xm (for dt and non dt case) * omap4 panda * omap5-uevm (tested on next-20140131 tag, where i2c problem can be seen) * Dra7xx * Beaglebone white * Beaglebone black * am335x-evm * AM43xx epos evm Cc: Felipe Balbi ba...@ti.com Cc: Nishanth Menon n...@ti.com Signed-off-by: Sourav Poddar sourav.pod...@ti.com --- drivers/i2c/busses/i2c-omap.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c index 85f8eac..4ec29a0 100644 --- a/drivers/i2c/busses/i2c-omap.c +++ b/drivers/i2c/busses/i2c-omap.c @@ -1238,7 +1238,7 @@ omap_i2c_probe(struct platform_device *pdev) adap = dev-adapter; i2c_set_adapdata(adap, dev); adap-owner = THIS_MODULE; - adap-class = I2C_CLASS_HWMON | I2C_CLASS_DEPRECATED; + adap-class = 0; strlcpy(adap-name, OMAP I2C adapter, sizeof(adap-name)); adap-algo = omap_i2c_algo; adap-dev.parent = pdev-dev; -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCHv2] i2c: omap: Disable default probing of i2c devices for omap i2c.
I2c core supports defualt probing functionality for devices not registered through dt/board files. If there are any client driver registered, i2c core will try to check if there is any device present corresponding to the address supplied by the client driver. If the device is actually present and not registered, core will register it, else the device default probe will fail and we get a omap i2c controller specific timeout messages. For example, Using multi_v7_config on omap5-uevm, CONFIG_SENSORS_LM90 and CONFIG_ICS932S401 is the driver which is enabled and gets registered. I2c core tries to find a valid corresponding device on each of the address supplied by registered driver, but could not find anyone. Hence, keep dumping the controller timeout speciic message. The patch tends to disable class based instantiation, default probing will not be attempted by the i2c-core for omap i2c. Device will always get registered through device tree(dt case) and board files(for non dt cases). Tested i2c enumeration and data transfer(using i2c utilities) with linux-next master on the following boards using omap2plus_defconfig: * Omap3 beagle-Xm (for dt and non dt case) * omap4 panda * omap5-uevm * Dra7xx * Beaglebone white * Beaglebone black * am335x-evm * AM43xx epos evm Tested i2c enumeration with linux-next master(except omap5) on the following boards using multi_v7_defconfig: * Omap3 beagle-Xm (for dt and non dt case) * omap4 panda * omap5-uevm (tested on next-20140131 tag, where i2c problem can be seen) * Dra7xx * Beaglebone white * Beaglebone black * am335x-evm * AM43xx epos evm Cc: Felipe Balbi ba...@ti.com Cc: Nishanth Menon n...@ti.com Signed-off-by: Sourav Poddar sourav.pod...@ti.com Reported-by: Nishanth Menon n...@ti.com --- v1-v2: add Reported-by attribute drivers/i2c/busses/i2c-omap.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c index 85f8eac..4ec29a0 100644 --- a/drivers/i2c/busses/i2c-omap.c +++ b/drivers/i2c/busses/i2c-omap.c @@ -1238,7 +1238,7 @@ omap_i2c_probe(struct platform_device *pdev) adap = dev-adapter; i2c_set_adapdata(adap, dev); adap-owner = THIS_MODULE; - adap-class = I2C_CLASS_HWMON | I2C_CLASS_DEPRECATED; + adap-class = 0; strlcpy(adap-name, OMAP I2C adapter, sizeof(adap-name)); adap-algo = omap_i2c_algo; adap-dev.parent = pdev-dev; -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCHv3 1/2] arm: dts: dra7: Add qspi device.
These add device tree entry for qspi controller driver on dra7-evm.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
Done and tested on top of
linux-next + benoit for_15 + tony crossbar branch +
crossbar dts patches.
v2-v3:
This was added as part of the following series,
http://www.spinics.net/lists/linux-omap/msg101024.html
Few patches of the above series are picked.
Sending this dts patch with updates[1] to enable spi mode
operations with flash device.
[1]:
- Enables only SPI mode operations
- Add partition table
- Add crossbar interrupt value.
arch/arm/boot/dts/dra7-evm.dts | 80
arch/arm/boot/dts/dra7.dtsi| 13 +++
2 files changed, 93 insertions(+)
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index 5babba0..986fcf3 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -93,6 +93,21 @@
0x24c (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */
;
};
+
+ qspi1_pins: pinmux_qspi1_pins {
+ pinctrl-single,pins =
+ 0x4c (PIN_INPUT | MUX_MODE1) /* gpmc_a3.qspi1_cs2 */
+ 0x50 (PIN_INPUT | MUX_MODE1) /* gpmc_a4.qspi1_cs3 */
+ 0x74 (PIN_INPUT | MUX_MODE1) /* gpmc_a13.qspi1_rtclk */
+ 0x78 (PIN_INPUT | MUX_MODE1) /* gpmc_a14.qspi1_d3 */
+ 0x7c (PIN_INPUT | MUX_MODE1) /* gpmc_a15.qspi1_d2 */
+ 0x80 (PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d1 */
+ 0x84 (PIN_INPUT | MUX_MODE1) /* gpmc_a17.qspi1_d0 */
+ 0x88 (PIN_INPUT | MUX_MODE1) /* qpmc_a18.qspi1_sclk */
+ 0xb8 (PIN_INPUT_PULLUP | MUX_MODE1) /*
gpmc_cs2.qspi1_cs0 */
+ 0xbc (PIN_INPUT_PULLUP | MUX_MODE1) /*
gpmc_cs3.qspi1_cs1 */
+ ;
+ };
};
i2c1 {
@@ -273,3 +288,68 @@
cpu0 {
cpu0-supply = smps123_reg;
};
+
+qspi {
+ status = okay;
+ pinctrl-names = default;
+ pinctrl-0 = qspi1_pins;
+
+ spi-max-frequency = 4800;
+ m25p80@0 {
+ compatible = s25fl256s1;
+ spi-max-frequency = 4800;
+ reg = 0;
+ spi-tx-bus-width = 1;
+ spi-rx-bus-width = 4;
+ spi-cpol;
+ spi-cpha;
+ #address-cells = 1;
+ #size-cells = 1;
+
+ /* MTD partition table.
+* The ROM checks the first four physical blocks
+* for a valid file to boot and the flash here is
+* 64KiB block size.
+*/
+ partition@0 {
+ label = QSPI.SPL;
+ reg = 0x 0x1;
+ };
+ partition@1 {
+ label = QSPI.SPL.backup1;
+ reg = 0x0001 0x0001;
+ };
+ partition@2 {
+ label = QSPI.SPL.backup2;
+ reg = 0x0002 0x0001;
+ };
+ partition@3 {
+ label = QSPI.SPL.backup3;
+ reg = 0x0003 0x0001;
+ };
+ partition@4 {
+ label = QSPI.u-boot;
+ reg = 0x0004 0x0018;
+ };
+ partition@5 {
+ label = QSPI.u-boot-spl-os;
+ reg = 0x001c 0x0001;
+ };
+ partition@6 {
+ label = QSPI.u-boot-env;
+ reg = 0x001d 0x0001;
+ };
+ partition@7 {
+ label = QSPI.u-boot-env.backup1;
+ reg = 0x001e 0x001;
+ };
+ partition@8 {
+ label = QSPI.kernel;
+ reg = 0x001f 0x0050;
+ };
+ partition@9 {
+ label = QSPI.file-system;
+ reg = 0x006f 0x0191;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 5d2ff52..a7a2fa8 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -645,6 +645,19 @@
dma-names = tx0, rx0;
status = disabled;
};
+
+ qspi: qspi@4b30 {
+ compatible = ti,dra7xxx-qspi;
+ reg = 0x4b30 0x100;
+ #address-cells = 1;
+ #size-cells = 0;
+ ti,hwmods = qspi;
+ clocks = qspi_gfclk_div;
+ clock-names = fck;
+ num-cs = 4;
+ interrupts = 0 343 0x4
[PATCHv3 2/2] arm: dts: am43x-epos: Add qspi device.
These add device tree entry for qspi controller driver on am43x-epos-evm.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
This was added as part of the following series,
http://www.spinics.net/lists/linux-omap/msg101024.html
Few patches of the above series are picked.
Sending this dts patch with updates[1] to enable spi mode
operations with flash device.
[1]: v2-v3
- Enables only SPI mode operations
- Add partition table
arch/arm/boot/dts/am4372.dtsi| 11 ++
arch/arm/boot/dts/am43x-epos-evm.dts | 63 ++
2 files changed, 74 insertions(+)
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index 5a7cc38..c426d25 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -698,6 +698,17 @@
edma 11;
dma-names = tx, rx;
};
+
+ qspi: qspi@4790 {
+ compatible = ti,am4372-qspi;
+ reg = 0x4790 0x100;
+ #address-cells = 1;
+ #size-cells = 0;
+ ti,hwmods = qspi;
+ interrupts = 0 138 0x4;
+ num-cs = 4;
+ status = disabled;
+ };
};
};
diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts
b/arch/arm/boot/dts/am43x-epos-evm.dts
index a7d0db1..20c7fa6 100644
--- a/arch/arm/boot/dts/am43x-epos-evm.dts
+++ b/arch/arm/boot/dts/am43x-epos-evm.dts
@@ -111,6 +111,17 @@
0x19c (PIN_OUTPUT | MUX_MODE3) /*
mcasp0_ahclkr.spi1_cs0 */
;
};
+
+ qspi1_default: qspi1_default {
+ pinctrl-single,pins =
+ 0x7c (PIN_INPUT_PULLUP | MUX_MODE3)
+ 0x88 (PIN_INPUT_PULLUP | MUX_MODE2)
+ 0x90 (PIN_INPUT_PULLUP | MUX_MODE3)
+ 0x94 (PIN_INPUT_PULLUP | MUX_MODE3)
+ 0x98 (PIN_INPUT_PULLUP | MUX_MODE3)
+ 0x9c (PIN_INPUT_PULLUP | MUX_MODE3)
+ ;
+ };
};
matrix_keypad: matrix_keypad@0 {
@@ -251,3 +262,55 @@
pinctrl-0 = spi1_pins;
status = okay;
};
+
+qspi {
+ status = okay;
+ pinctrl-names = default;
+ pinctrl-0 = qspi1_default;
+
+ spi-max-frequency = 4800;
+ m25p80@0 {
+ compatible = mx66l51235l;
+ spi-max-frequency = 4800;
+ reg = 0;
+ spi-cpol;
+ spi-cpha;
+ spi-tx-bus-width = 1;
+ spi-rx-bus-width = 4;
+ #address-cells = 1;
+ #size-cells = 1;
+
+ /* MTD partition table.
+* The ROM checks the first 512KiB
+* for a valid file to boot(XIP).
+*/
+ partition@0 {
+ label = QSPI.U_BOOT;
+ reg = 0x 0x8;
+ };
+ partition@1 {
+ label = QSPI.U_BOOT.backup;
+ reg = 0x0008 0x0008;
+ };
+ partition@2 {
+ label = QSPI.U-BOOT-SPL_OS;
+ reg = 0x0010 0x0001;
+ };
+ partition@3 {
+ label = QSPI.U_BOOT_ENV;
+ reg = 0x0011 0x0001;
+ };
+ partition@4 {
+ label = QSPI.U-BOOT-ENV.backup;
+ reg = 0x0012 0x0001;
+ };
+ partition@5 {
+ label = QSPI.KERNEL;
+ reg = 0x0013 0x080;
+ };
+ partition@6 {
+ label = QSPI.FILESYSTEM;
+ reg = 0x0093 0x36D;
+ };
+ };
+};
--
1.7.9.5
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Re: [PATCHv2 9/9] arm: dts: am43x-gp-evm: Add matrix gpio keys.
On Sunday 02 March 2014 11:00 PM, Benoit Cousson wrote:
Hi Sourav,
On 21/02/2014 15:28, Sourav Poddar wrote:
Hi Benoit,
On Tuesday 14 January 2014 07:51 PM, Benoit Cousson wrote:
Hi Felipe,
On 14/01/2014 14:14, Felipe Balbi wrote:
On Mon, Jan 13, 2014 at 10:13:13PM +0530, sourav wrote:
Benoit,
On Thursday 19 December 2013 06:03 PM, Sourav Poddar wrote:
Add gpio keys node for am43x gp evm.
Signed-off-by: Sourav Poddarsourav.pod...@ti.com
---
arch/arm/boot/dts/am437x-gp-evm.dts | 21 +
1 file changed, 21 insertions(+)
diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts
b/arch/arm/boot/dts/am437x-gp-evm.dts
index 0dc248d..4eb72b8 100644
--- a/arch/arm/boot/dts/am437x-gp-evm.dts
+++ b/arch/arm/boot/dts/am437x-gp-evm.dts
@@ -13,6 +13,7 @@
#include am4372.dtsi
#includedt-bindings/pinctrl/am43xx.h
#includedt-bindings/pwm/pwm.h
+#includedt-bindings/gpio/gpio.h
/ {
model = TI AM437x GP EVM;
@@ -24,6 +25,26 @@
brightness-levels =0 51 53 56 62 75 101 152 255;
default-brightness-level =8;
};
+
+matrix_keypad: matrix_keypad@0 {
+compatible = gpio-matrix-keypad;
+debounce-delay-ms =5;
+col-scan-delay-us =2;
+
+row-gpios =gpio3 21 GPIO_ACTIVE_HIGH /* Bank3, pin21 */
+ gpio4 3 GPIO_ACTIVE_HIGH /* Bank4, pin3 */
+ gpio4 2 GPIO_ACTIVE_HIGH; /* Bank4, pin2 */
+
+col-gpios =gpio3 19 GPIO_ACTIVE_HIGH /* Bank3, pin19 */
+ gpio3 20 GPIO_ACTIVE_HIGH; /* Bank3, pin20 */
+
+linux,keymap =0x0201 /* P1 */
+0x00010202 /* P2 */
+0x0167 /* UP */
+0x0101006a /* RIGHT */
+0x0269 /* LEFT */
+0x0201006c; /* DOWN */
+};
};
am43xx_pinmux {
ping on this series, this series is lying for a while.
This series is based on your for_3.14 branch.
Benoit, do you need us to do anything else to get this merged ? Sourav
already rebased the patches as you requested back in December 19th.
Nope, I've just needed more BW. I'll apply it ASAP.
Thanks,
Benoit
Ping on this.
I've just applied them. Sorry for the delay,
Regards,
Benoit
Thanks!
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Re: [PATCHv2 9/9] arm: dts: am43x-gp-evm: Add matrix gpio keys.
Hi Benoit,
On Tuesday 14 January 2014 07:51 PM, Benoit Cousson wrote:
Hi Felipe,
On 14/01/2014 14:14, Felipe Balbi wrote:
On Mon, Jan 13, 2014 at 10:13:13PM +0530, sourav wrote:
Benoit,
On Thursday 19 December 2013 06:03 PM, Sourav Poddar wrote:
Add gpio keys node for am43x gp evm.
Signed-off-by: Sourav Poddarsourav.pod...@ti.com
---
arch/arm/boot/dts/am437x-gp-evm.dts | 21 +
1 file changed, 21 insertions(+)
diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts
b/arch/arm/boot/dts/am437x-gp-evm.dts
index 0dc248d..4eb72b8 100644
--- a/arch/arm/boot/dts/am437x-gp-evm.dts
+++ b/arch/arm/boot/dts/am437x-gp-evm.dts
@@ -13,6 +13,7 @@
#include am4372.dtsi
#includedt-bindings/pinctrl/am43xx.h
#includedt-bindings/pwm/pwm.h
+#includedt-bindings/gpio/gpio.h
/ {
model = TI AM437x GP EVM;
@@ -24,6 +25,26 @@
brightness-levels =0 51 53 56 62 75 101 152 255;
default-brightness-level =8;
};
+
+matrix_keypad: matrix_keypad@0 {
+compatible = gpio-matrix-keypad;
+debounce-delay-ms =5;
+col-scan-delay-us =2;
+
+row-gpios =gpio3 21 GPIO_ACTIVE_HIGH /* Bank3, pin21 */
+ gpio4 3 GPIO_ACTIVE_HIGH /* Bank4, pin3 */
+ gpio4 2 GPIO_ACTIVE_HIGH; /* Bank4, pin2 */
+
+col-gpios =gpio3 19 GPIO_ACTIVE_HIGH /* Bank3, pin19 */
+ gpio3 20 GPIO_ACTIVE_HIGH; /* Bank3, pin20 */
+
+linux,keymap =0x0201 /* P1 */
+0x00010202 /* P2 */
+0x0167 /* UP */
+0x0101006a /* RIGHT */
+0x0269 /* LEFT */
+0x0201006c; /* DOWN */
+};
};
am43xx_pinmux {
ping on this series, this series is lying for a while.
This series is based on your for_3.14 branch.
Benoit, do you need us to do anything else to get this merged ? Sourav
already rebased the patches as you requested back in December 19th.
Nope, I've just needed more BW. I'll apply it ASAP.
Thanks,
Benoit
Ping on this.
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[PATCH] spi: omap2-mcspi: Fix mcspi FIFO usage
The following commit add Fifo support for omap mcspi.
commit d33f473dcd8e69321f001ba330d648f475b504c9
Author: Illia Smyrnov illia.smyr...@ti.com
Date: Mon Jun 17 16:31:06 2013 +0300
spi: omap2-mcspi: Add FIFO buffer support
Currently, enabling of FIFO is done based on rx_buf or tx_buf checks
and only one of the RX or TX fifo is enabled. There can be transfers
in which both RX/TX fifo is desired. Hence, fixing code for the
same to allow setting both TX/RX fifo when needed.
Application:
While doing a loopback testing on beaglebone white(DMA
with FIFO enabled), where both RX and TX buf buffers are passed,
./spidev_test hangs.
The $subject patch fixes that hang and data can be loopbacked.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
drivers/spi/spi-omap2-mcspi.c |4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/spi/spi-omap2-mcspi.c b/drivers/spi/spi-omap2-mcspi.c
index ed4af47..86402a7 100644
--- a/drivers/spi/spi-omap2-mcspi.c
+++ b/drivers/spi/spi-omap2-mcspi.c
@@ -299,7 +299,9 @@ static void omap2_mcspi_set_fifo(const struct spi_device
*spi,
if (t-rx_buf != NULL) {
chconf |= OMAP2_MCSPI_CHCONF_FFER;
xferlevel |= (fifo_depth - 1) 8;
- } else {
+ }
+
+ if (t-tx_buf != NULL) {
chconf |= OMAP2_MCSPI_CHCONF_FFET;
xferlevel |= fifo_depth - 1;
}
--
1.7.9.5
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[PATCHv2 0/9] Add device nodes for am43x epos and gp evm.
The patch series adds support for enabling pwm backlight, i2c2, spi and matrix gpio keys on am43x-epos-evm, while adding support for pwm, gpio keys on gp evm. Originally, this patches was divided into two seperate series, merging them into one and rebasing them on top of Benoit for_3.14/dts branch so that it can be pushed at once. Boot tested with Benoit for_3.14 + tero clock series(1) Tested on am43x-epos-evm, m43x-gp-evm. There is a some bug while using regulators through backlight driver on 3.13-rc1. So, tested pwm part with this temporary patch[2]. [1]: https://patchwork.kernel.org/patch/3009541/ [2]: http://www.spinics.net/lists/arm-kernel/msg288215.html Patches are available at: git://gitorious.org/linux-connectivity/linux-connectivity.git for_3.14 v1-v2: No code change, just squash two series into one and rebased it on benoit for_3.14/dts Darren Etheridge (1): pinctrl: am43xx: dt-bindings: add MUX_MODE8 Lokesh Vutla (1): arm: dts: am437x-gp-evm: Add gp dts. Sourav Poddar (6): arm: dts: am4372: Add pwm-cells property for ecap device. arm: dts: am43x-epos-evm: Add I2C2 data. arm: dts: am43x-epos-evm: Add SPI data. arm: dts: am437x-gp-evm: Add pwm backlight support. arm: dts: am437x-gp-evm: Enable gpio. arm: dts: am43x-gp-evm: Add matrix gpio keys. ARM: dts: am43x-epos-evm: Add pwm backlight support. .../devicetree/bindings/arm/omap/omap.txt |3 + arch/arm/boot/dts/Makefile |1 + arch/arm/boot/dts/am4372.dtsi |9 ++ arch/arm/boot/dts/am437x-gp-evm.dts| 100 arch/arm/boot/dts/am43x-epos-evm.dts | 67 + include/dt-bindings/pinctrl/am43xx.h |1 + 6 files changed, 181 insertions(+) create mode 100644 arch/arm/boot/dts/am437x-gp-evm.dts -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCHv2 6/9] arm: dts: am437x-gp-evm: Add gp dts.
From: Lokesh Vutla lokeshvu...@ti.com
AM437x GP EVM DTS with pinmux information to make I2C on
EVM usable.
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
Signed-off-by: Afzal Mohammed af...@ti.com
---
.../devicetree/bindings/arm/omap/omap.txt |3 ++
arch/arm/boot/dts/Makefile |1 +
arch/arm/boot/dts/am437x-gp-evm.dts| 47
3 files changed, 51 insertions(+)
create mode 100644 arch/arm/boot/dts/am437x-gp-evm.dts
diff --git a/Documentation/devicetree/bindings/arm/omap/omap.txt
b/Documentation/devicetree/bindings/arm/omap/omap.txt
index 808c154..be5f365 100644
--- a/Documentation/devicetree/bindings/arm/omap/omap.txt
+++ b/Documentation/devicetree/bindings/arm/omap/omap.txt
@@ -61,5 +61,8 @@ Boards:
- AM43x EPOS EVM
compatible = ti,am43x-epos-evm, ti,am4372, ti,am43
+- AM437x GP EVM
+ compatible = ti,am437x-gp-evm, ti,am4372, ti,am43
+
- DRA7 EVM: Software Developement Board for DRA7XX
compatible = ti,dra7-evm, ti,dra7
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index ad155fc..aaeddf9 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -209,6 +209,7 @@ dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \
am3517-evm.dtb \
am3517_mt_ventoux.dtb \
am43x-epos-evm.dtb \
+ am437x-gp-evm.dtb \
dra7-evm.dtb
dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-ethernet-disk-mini-v2.dtb
dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb
diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts
b/arch/arm/boot/dts/am437x-gp-evm.dts
new file mode 100644
index 000..11d93ba
--- /dev/null
+++ b/arch/arm/boot/dts/am437x-gp-evm.dts
@@ -0,0 +1,47 @@
+/*
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/* AM437x GP EVM */
+
+/dts-v1/;
+
+#include am4372.dtsi
+#include dt-bindings/pinctrl/am43xx.h
+
+/ {
+ model = TI AM437x GP EVM;
+ compatible = ti,am437x-gp-evm,ti,am4372,ti,am43;
+};
+
+am43xx_pinmux {
+ i2c0_pins: i2c0_pins {
+ pinctrl-single,pins =
+ 0x188 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)
/* i2c0_sda.i2c0_sda */
+ 0x18c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)
/* i2c0_scl.i2c0_scl */
+ ;
+ };
+
+ i2c1_pins: i2c1_pins {
+ pinctrl-single,pins =
+ 0x15c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2)
/* spi0_cs0.i2c1_scl */
+ 0x158 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2)
/* spi0_d1.i2c1_sda */
+ ;
+ };
+};
+
+i2c0 {
+status = okay;
+pinctrl-names = default;
+pinctrl-0 = i2c0_pins;
+};
+
+i2c1 {
+status = okay;
+pinctrl-names = default;
+pinctrl-0 = i2c1_pins;
+};
--
1.7.9.5
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[PATCHv2 4/9] arm: dts: am43x-epos-evm: Add I2C2 data.
Add I2C2 dts data.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
arch/arm/boot/dts/am43x-epos-evm.dts | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts
b/arch/arm/boot/dts/am43x-epos-evm.dts
index 0899c5f..d781a69 100644
--- a/arch/arm/boot/dts/am43x-epos-evm.dts
+++ b/arch/arm/boot/dts/am43x-epos-evm.dts
@@ -86,6 +86,13 @@
0x164 MUX_MODE0 /*
eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
;
};
+
+ i2c2_pins: pinmux_i2c2_pins {
+ pinctrl-single,pins =
+ 0x1c0 (PIN_INPUT_PULLUP | SLEWCTRL_FAST |
MUX_MODE8)/* i2c2_sda.i2c2_sda */
+ 0x1c4 (PIN_INPUT_PULLUP | SLEWCTRL_FAST |
MUX_MODE8)/* i2c2_scl.i2c2_scl */
+ ;
+ };
};
matrix_keypad: matrix_keypad@0 {
@@ -183,6 +190,12 @@
};
};
+i2c2 {
+ pinctrl-names = default;
+ pinctrl-0 = i2c2_pins;
+ status = okay;
+};
+
gpio0 {
status = okay;
};
--
1.7.9.5
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[PATCHv2 3/9] pinctrl: am43xx: dt-bindings: add MUX_MODE8
From: Darren Etheridge detheri...@ti.com AM43xx devices have an extra MUX_MODE for certain pins. Updating dt include to have MUX_MODE8 which maps to 0x8. Signed-off-by: Darren Etheridge detheri...@ti.com Signed-off-by: Sourav Poddar sourav.pod...@ti.com --- include/dt-bindings/pinctrl/am43xx.h |1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/pinctrl/am43xx.h b/include/dt-bindings/pinctrl/am43xx.h index eb6c366a..9c2e4f8 100644 --- a/include/dt-bindings/pinctrl/am43xx.h +++ b/include/dt-bindings/pinctrl/am43xx.h @@ -13,6 +13,7 @@ #define MUX_MODE5 5 #define MUX_MODE6 6 #define MUX_MODE7 7 +#define MUX_MODE8 8 #define PULL_DISABLE (1 16) #define PULL_UP(1 17) -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCHv2 2/9] ARM: dts: am43x-epos-evm: Add pwm backlight support.
Add pwm backlight support for am43x epos evm.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
arch/arm/boot/dts/am43x-epos-evm.dts | 24
1 file changed, 24 insertions(+)
diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts
b/arch/arm/boot/dts/am43x-epos-evm.dts
index fbf9c4c..0899c5f 100644
--- a/arch/arm/boot/dts/am43x-epos-evm.dts
+++ b/arch/arm/boot/dts/am43x-epos-evm.dts
@@ -13,6 +13,7 @@
#include am4372.dtsi
#include dt-bindings/pinctrl/am43xx.h
#include dt-bindings/gpio/gpio.h
+#include dt-bindings/pwm/pwm.h
/ {
model = TI AM43x EPOS EVM;
@@ -79,6 +80,12 @@
0x18c (PIN_INPUT_PULLUP | SLEWCTRL_FAST |
MUX_MODE0)/* i2c0_scl.i2c0_scl */
;
};
+
+ ecap0_pins: backlight_pins {
+ pinctrl-single,pins =
+ 0x164 MUX_MODE0 /*
eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
+ ;
+ };
};
matrix_keypad: matrix_keypad@0 {
@@ -113,6 +120,13 @@
0x0203006c /* DOWN */
0x03030069;/* LEFT */
};
+
+ backlight {
+ compatible = pwm-backlight;
+ pwms = ecap0 0 5 PWM_POLARITY_INVERTED;
+ brightness-levels = 0 51 53 56 62 75 101 152 255;
+ default-brightness-level = 8;
+ };
};
mmc1 {
@@ -184,3 +198,13 @@
gpio3 {
status = okay;
};
+
+epwmss0 {
+ status = okay;
+};
+
+ecap0 {
+ status = okay;
+ pinctrl-names = default;
+ pinctrl-0 = ecap0_pins;
+};
--
1.7.9.5
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[PATCHv2 7/9] arm: dts: am437x-gp-evm: Add pwm backlight support.
Add pwm backlight support for gp evm.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
arch/arm/boot/dts/am437x-gp-evm.dts | 24
1 file changed, 24 insertions(+)
diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts
b/arch/arm/boot/dts/am437x-gp-evm.dts
index 11d93ba..2e79bda 100644
--- a/arch/arm/boot/dts/am437x-gp-evm.dts
+++ b/arch/arm/boot/dts/am437x-gp-evm.dts
@@ -12,10 +12,18 @@
#include am4372.dtsi
#include dt-bindings/pinctrl/am43xx.h
+#include dt-bindings/pwm/pwm.h
/ {
model = TI AM437x GP EVM;
compatible = ti,am437x-gp-evm,ti,am4372,ti,am43;
+
+ backlight {
+ compatible = pwm-backlight;
+ pwms = ecap0 0 5 PWM_POLARITY_INVERTED;
+ brightness-levels = 0 51 53 56 62 75 101 152 255;
+ default-brightness-level = 8;
+ };
};
am43xx_pinmux {
@@ -32,6 +40,12 @@
0x158 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2)
/* spi0_d1.i2c1_sda */
;
};
+
+ ecap0_pins: backlight_pins {
+ pinctrl-single,pins =
+ 0x164 MUX_MODE0 /*
eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
+ ;
+ };
};
i2c0 {
@@ -45,3 +59,13 @@
pinctrl-names = default;
pinctrl-0 = i2c1_pins;
};
+
+epwmss0 {
+ status = okay;
+};
+
+ecap0 {
+ status = okay;
+ pinctrl-names = default;
+ pinctrl-0 = ecap0_pins;
+};
--
1.7.9.5
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[PATCHv2 5/9] arm: dts: am43x-epos-evm: Add SPI data.
Add SPI dts data.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
arch/arm/boot/dts/am43x-epos-evm.dts | 30 ++
1 file changed, 30 insertions(+)
diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts
b/arch/arm/boot/dts/am43x-epos-evm.dts
index d781a69..a7d0db1 100644
--- a/arch/arm/boot/dts/am43x-epos-evm.dts
+++ b/arch/arm/boot/dts/am43x-epos-evm.dts
@@ -93,6 +93,24 @@
0x1c4 (PIN_INPUT_PULLUP | SLEWCTRL_FAST |
MUX_MODE8)/* i2c2_scl.i2c2_scl */
;
};
+
+ spi0_pins: pinmux_spi0_pins {
+ pinctrl-single,pins =
+ 0x150 (PIN_INPUT | MUX_MODE0) /*
spi0_clk.spi0_clk */
+ 0x154 (PIN_OUTPUT | MUX_MODE0) /*
spi0_d0.spi0_d0 */
+ 0x158 (PIN_INPUT | MUX_MODE0) /*
spi0_d1.spi0_d1 */
+ 0x15c (PIN_OUTPUT | MUX_MODE0) /*
spi0_cs0.spi0_cs0 */
+ ;
+ };
+
+ spi1_pins: pinmux_spi1_pins {
+ pinctrl-single,pins =
+ 0x190 (PIN_INPUT | MUX_MODE3) /*
mcasp0_aclkx.spi1_clk */
+ 0x194 (PIN_OUTPUT | MUX_MODE3) /*
mcasp0_fsx.spi1_d0 */
+ 0x198 (PIN_INPUT | MUX_MODE3) /*
mcasp0_axr0.spi1_d1 */
+ 0x19c (PIN_OUTPUT | MUX_MODE3) /*
mcasp0_ahclkr.spi1_cs0 */
+ ;
+ };
};
matrix_keypad: matrix_keypad@0 {
@@ -221,3 +239,15 @@
pinctrl-names = default;
pinctrl-0 = ecap0_pins;
};
+
+spi0 {
+ pinctrl-names = default;
+ pinctrl-0 = spi0_pins;
+ status = okay;
+};
+
+spi1 {
+ pinctrl-names = default;
+ pinctrl-0 = spi1_pins;
+ status = okay;
+};
--
1.7.9.5
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[PATCHv2 1/9] arm: dts: am4372: Add pwm-cells property for ecap device.
Add pwm-cells node for all ecap, ehrpwm in am43x dtsi files.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
arch/arm/boot/dts/am4372.dtsi |9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index 974d103..c314adb 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -495,6 +495,7 @@
ecap0: ecap@48300100 {
compatible = ti,am4372-ecap,ti,am33xx-ecap;
+ #pwm-cells = 3;
reg = 0x48300100 0x80;
ti,hwmods = ecap0;
status = disabled;
@@ -502,6 +503,7 @@
ehrpwm0: ehrpwm@48300200 {
compatible =
ti,am4372-ehrpwm,ti,am33xx-ehrpwm;
+ #pwm-cells = 3;
reg = 0x48300200 0x80;
ti,hwmods = ehrpwm0;
status = disabled;
@@ -519,6 +521,7 @@
ecap1: ecap@48302100 {
compatible = ti,am4372-ecap,ti,am33xx-ecap;
+ #pwm-cells = 3;
reg = 0x48302100 0x80;
ti,hwmods = ecap1;
status = disabled;
@@ -526,6 +529,7 @@
ehrpwm1: ehrpwm@48302200 {
compatible =
ti,am4372-ehrpwm,ti,am33xx-ehrpwm;
+ #pwm-cells = 3;
reg = 0x48302200 0x80;
ti,hwmods = ehrpwm1;
status = disabled;
@@ -543,6 +547,7 @@
ecap2: ecap@48304100 {
compatible = ti,am4372-ecap,ti,am33xx-ecap;
+ #pwm-cells = 3;
reg = 0x48304100 0x80;
ti,hwmods = ecap2;
status = disabled;
@@ -550,6 +555,7 @@
ehrpwm2: ehrpwm@48304200 {
compatible =
ti,am4372-ehrpwm,ti,am33xx-ehrpwm;
+ #pwm-cells = 3;
reg = 0x48304200 0x80;
ti,hwmods = ehrpwm2;
status = disabled;
@@ -567,6 +573,7 @@
ehrpwm3: ehrpwm@48306200 {
compatible =
ti,am4372-ehrpwm,ti,am33xx-ehrpwm;
+ #pwm-cells = 3;
reg = 0x48306200 0x80;
ti,hwmods = ehrpwm3;
status = disabled;
@@ -584,6 +591,7 @@
ehrpwm4: ehrpwm@48308200 {
compatible =
ti,am4372-ehrpwm,ti,am33xx-ehrpwm;
+ #pwm-cells = 3;
reg = 0x48308200 0x80;
ti,hwmods = ehrpwm4;
status = disabled;
@@ -601,6 +609,7 @@
ehrpwm5: ehrpwm@4830a200 {
compatible =
ti,am4372-ehrpwm,ti,am33xx-ehrpwm;
+ #pwm-cells = 3;
reg = 0x4830a200 0x80;
ti,hwmods = ehrpwm5;
status = disabled;
--
1.7.9.5
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[PATCHv2 8/9] arm: dts: am437x-gp-evm: Enable gpio.
Enable gpio3, gpio4, it will be used by gpio matrix keys. Also,
can be used by othe peripherals.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
arch/arm/boot/dts/am437x-gp-evm.dts |8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts
b/arch/arm/boot/dts/am437x-gp-evm.dts
index 2e79bda..0dc248d 100644
--- a/arch/arm/boot/dts/am437x-gp-evm.dts
+++ b/arch/arm/boot/dts/am437x-gp-evm.dts
@@ -69,3 +69,11 @@
pinctrl-names = default;
pinctrl-0 = ecap0_pins;
};
+
+gpio3 {
+ status = okay;
+};
+
+gpio4 {
+ status = okay;
+};
--
1.7.9.5
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[PATCHv2 9/9] arm: dts: am43x-gp-evm: Add matrix gpio keys.
Add gpio keys node for am43x gp evm.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
arch/arm/boot/dts/am437x-gp-evm.dts | 21 +
1 file changed, 21 insertions(+)
diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts
b/arch/arm/boot/dts/am437x-gp-evm.dts
index 0dc248d..4eb72b8 100644
--- a/arch/arm/boot/dts/am437x-gp-evm.dts
+++ b/arch/arm/boot/dts/am437x-gp-evm.dts
@@ -13,6 +13,7 @@
#include am4372.dtsi
#include dt-bindings/pinctrl/am43xx.h
#include dt-bindings/pwm/pwm.h
+#include dt-bindings/gpio/gpio.h
/ {
model = TI AM437x GP EVM;
@@ -24,6 +25,26 @@
brightness-levels = 0 51 53 56 62 75 101 152 255;
default-brightness-level = 8;
};
+
+ matrix_keypad: matrix_keypad@0 {
+ compatible = gpio-matrix-keypad;
+ debounce-delay-ms = 5;
+ col-scan-delay-us = 2;
+
+ row-gpios = gpio3 21 GPIO_ACTIVE_HIGH /* Bank3, pin21 */
+ gpio4 3 GPIO_ACTIVE_HIGH /* Bank4, pin3 */
+ gpio4 2 GPIO_ACTIVE_HIGH; /* Bank4, pin2 */
+
+ col-gpios = gpio3 19 GPIO_ACTIVE_HIGH /* Bank3, pin19 */
+ gpio3 20 GPIO_ACTIVE_HIGH; /* Bank3, pin20 */
+
+ linux,keymap = 0x0201 /* P1 */
+ 0x00010202 /* P2 */
+ 0x0167 /* UP */
+ 0x0101006a /* RIGHT */
+ 0x0269 /* LEFT */
+ 0x0201006c; /* DOWN */
+ };
};
am43xx_pinmux {
--
1.7.9.5
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[PATCH 1/3] pwm: core: Rearrange pwm lock.
[c039eec8] (driver_detach+0xb4/0xb8)
[ 219.984466] [c039eec8] (driver_detach+0xb4/0xb8) from [c039e4ec]
(bus_remove_driver+0x8c/0xd0)
[ 219.993438] [c039e4ec] (bus_remove_driver+0x8c/0xd0) from [c00abd2c]
(SyS_delete_module+0x118/0x22c)
[ 220.002899] [c00abd2c] (SyS_delete_module+0x118/0x22c) from [c0014100]
(ret_fast_syscall+0x0/0x48)
Looks like s_active lock cannot be held while pwm lock is held.
The patch fixes the above issue by unlocking the pwm lock before acquiring the
sysfs lock.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
drivers/pwm/core.c |4 +++-
1 files changed, 3 insertions(+), 1 deletions(-)
diff --git a/drivers/pwm/core.c b/drivers/pwm/core.c
index 2ca9504..3e1d499 100644
--- a/drivers/pwm/core.c
+++ b/drivers/pwm/core.c
@@ -300,6 +300,7 @@ int pwmchip_remove(struct pwm_chip *chip)
if (test_bit(PWMF_REQUESTED, pwm-flags)) {
ret = -EBUSY;
+ mutex_unlock(pwm_lock);
goto out;
}
}
@@ -311,10 +312,11 @@ int pwmchip_remove(struct pwm_chip *chip)
free_pwms(chip);
+ mutex_unlock(pwm_lock);
+
pwmchip_sysfs_unexport(chip);
out:
- mutex_unlock(pwm_lock);
return ret;
}
EXPORT_SYMBOL_GPL(pwmchip_remove);
--
1.7.1
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[PATCH 3/3] driver: pwmss: Disable stop clk bit during enable clock call.
Writing to ecap register on second insmod crashes with an external abort. This happens becuase the STOP_CLK bit remains set(from rmmod) during the second insmod thereby not allowing the clocks to get enabled. So, we disable STOP clock bit while doing a clock enable. Signed-off-by: Sourav Poddar sourav.pod...@ti.com --- drivers/pwm/pwm-tipwmss.c |2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/drivers/pwm/pwm-tipwmss.c b/drivers/pwm/pwm-tipwmss.c index 3b119bc..4749866 100644 --- a/drivers/pwm/pwm-tipwmss.c +++ b/drivers/pwm/pwm-tipwmss.c @@ -40,6 +40,8 @@ u16 pwmss_submodule_state_change(struct device *dev, int set) mutex_lock(info-pwmss_lock); val = readw(info-mmio_base + PWMSS_CLKCONFIG); + if (set == PWMSS_ECAPCLK_EN) + val = ~PWMSS_ECAPCLK_STOP_REQ; val |= set; writew(val , info-mmio_base + PWMSS_CLKCONFIG); mutex_unlock(info-pwmss_lock); -- 1.7.1 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 0/3] pwm: ti: Miscellaneous Fixes and cleanup for pwm.
This patch series caters to the issue faced while using tiecap as a module. The patch fix lock dependency issue which leads to crash during rmmod. Also fixes the clock control register setup values during CLK EN call. Sourav Poddar (3): pwm: core: Rearrange pwm lock usage. driver: pwm: ti-ecap: Rmove duplicate put_sync call. driver: pwmss: Disable stop during Enable clock call.. drivers/pwm/core.c|4 +++- drivers/pwm/pwm-tiecap.c |1 - drivers/pwm/pwm-tipwmss.c |2 ++ 3 files changed, 5 insertions(+), 2 deletions(-) -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 2/3] driver: pwm: ti-ecap: Remove duplicate put_sync call.
Remove duplicate 'pm_runtime_put_sync' in the remove path. Signed-off-by: Sourav Poddar sourav.pod...@ti.com --- drivers/pwm/pwm-tiecap.c |1 - 1 files changed, 0 insertions(+), 1 deletions(-) diff --git a/drivers/pwm/pwm-tiecap.c b/drivers/pwm/pwm-tiecap.c index 4e5c3d1..032092c 100644 --- a/drivers/pwm/pwm-tiecap.c +++ b/drivers/pwm/pwm-tiecap.c @@ -279,7 +279,6 @@ static int ecap_pwm_remove(struct platform_device *pdev) pwmss_submodule_state_change(pdev-dev.parent, PWMSS_ECAPCLK_STOP_REQ); pm_runtime_put_sync(pdev-dev); - pm_runtime_put_sync(pdev-dev); pm_runtime_disable(pdev-dev); return pwmchip_remove(pc-chip); } -- 1.7.1 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 0/3] Add more device nodes for am43x gp evm.
Benoit, On Wednesday 27 November 2013 01:01 PM, Sourav Poddar wrote: The patch series adds support for enabling gpio, pwm backlight and matrix gpio keys on am43x-gp-evm. Done on top of 3.13-rc1 + tero clock series(1) + Afzal's basic gp support(2). [1]: https://patchwork.kernel.org/patch/3009541/ [2]: https://patchwork.kernel.org/patch/3171761/ Tested on am43x-gp-evm. There is a some bug while using regulators through backlight driver on 3.13-rc1. So, tested pwm part with this patch[3]. [3]: http://www.spinics.net/lists/arm-kernel/msg288215.html Sourav Poddar (3): arm: dts: am437x-gp-evm: Enable gpio. ARM: dts: am43x-gp-evm: Add matrix gpio keys. ARM: dts: am437x-gp-evm: Add pwm backlight support. arch/arm/boot/dts/am437x-gp-evm.dts | 53 +++ 1 files changed, 53 insertions(+), 0 deletions(-) Ping on this? -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 0/5] Add more device nodes for am43x-epos-evm
Benoit, On Wednesday 27 November 2013 01:00 PM, Sourav Poddar wrote: The patch series adds support for enabling pwm backlight, i2c2, spi and matrix gpio keys on am43x-gp-evm. Done on top of 3.13-rc1 + tero clock series(1) [1]: https://patchwork.kernel.org/patch/3009541/ Tested on am43x-gp-evm. There is a some bug while using regulators through backlight driver on 3.13-rc1. So, tested pwm part with this temporary patch[2]. [2]: http://www.spinics.net/lists/arm-kernel/msg288215.html Darren Etheridge (1): pinctrl: am43xx: dt-bindings: add MUX_MODE8 Sourav Poddar (4): arm: dts: am4372: Add pwm-cellsproperty for ecap device. arm: dts: am43x-epos-evm: Add I2C data. arm: dts: am43x-epos-evm: Add SPI data. ARM: dts: am43x-epos-evm: Add pwm backlight support. arch/arm/boot/dts/am4372.dtsi|9 + arch/arm/boot/dts/am43x-epos-evm.dts | 67 ++ include/dt-bindings/pinctrl/am43xx.h |1 + 3 files changed, 77 insertions(+), 0 deletions(-) Ping on this? -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 0/3] Add more device nodes for am43x gp evm.
On Wednesday 18 December 2013 11:19 PM, Benoit Cousson wrote: Hi Sourav, On 18/12/2013 18:43, Sourav Poddar wrote: Benoit, On Wednesday 27 November 2013 01:01 PM, Sourav Poddar wrote: The patch series adds support for enabling gpio, pwm backlight and matrix gpio keys on am43x-gp-evm. Done on top of 3.13-rc1 + tero clock series(1) + Afzal's basic gp support(2). [1]: https://patchwork.kernel.org/patch/3009541/ [2]: https://patchwork.kernel.org/patch/3171761/ Tested on am43x-gp-evm. There is a some bug while using regulators through backlight driver on 3.13-rc1. So, tested pwm part with this patch[3]. [3]: http://www.spinics.net/lists/arm-kernel/msg288215.html Sourav Poddar (3): arm: dts: am437x-gp-evm: Enable gpio. ARM: dts: am43x-gp-evm: Add matrix gpio keys. ARM: dts: am437x-gp-evm: Add pwm backlight support. arch/arm/boot/dts/am437x-gp-evm.dts | 53 +++ 1 files changed, 53 insertions(+), 0 deletions(-) Ping on this? The series looks good, but you should rebase it on top of for_3.14/dts that is based on the big cleanup branch Tony has done. I cannot apply it right now. Ok. I will rebase it and send you the series, As you can see there is one dependency on afzal basic support patch, as mentioned in the cover letter. If you are ok with that patch, it has to go first. So, if you wish I can work with afzal and send you this series and afzal patch together. Thanks, Benoit -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 0/3] Add more device nodes for am43x gp evm.
On Thursday 19 December 2013 12:21 AM, Benoit Cousson wrote: On 18/12/2013 19:15, Sourav Poddar wrote: On Wednesday 18 December 2013 11:19 PM, Benoit Cousson wrote: Hi Sourav, On 18/12/2013 18:43, Sourav Poddar wrote: Benoit, On Wednesday 27 November 2013 01:01 PM, Sourav Poddar wrote: The patch series adds support for enabling gpio, pwm backlight and matrix gpio keys on am43x-gp-evm. Done on top of 3.13-rc1 + tero clock series(1) + Afzal's basic gp support(2). [1]: https://patchwork.kernel.org/patch/3009541/ [2]: https://patchwork.kernel.org/patch/3171761/ Tested on am43x-gp-evm. There is a some bug while using regulators through backlight driver on 3.13-rc1. So, tested pwm part with this patch[3]. [3]: http://www.spinics.net/lists/arm-kernel/msg288215.html Sourav Poddar (3): arm: dts: am437x-gp-evm: Enable gpio. ARM: dts: am43x-gp-evm: Add matrix gpio keys. ARM: dts: am437x-gp-evm: Add pwm backlight support. arch/arm/boot/dts/am437x-gp-evm.dts | 53 +++ 1 files changed, 53 insertions(+), 0 deletions(-) Ping on this? The series looks good, but you should rebase it on top of for_3.14/dts that is based on the big cleanup branch Tony has done. I cannot apply it right now. Ok. I will rebase it and send you the series, As you can see there is one dependency on afzal basic support patch, as mentioned in the cover letter. If you are ok with that patch, it has to go first. So, if you wish I can work with afzal and send you this series and afzal patch together. Yes, go ahead and repost the whole series with the depency. BTW, could you do that as well with your other series? Yes, I will do that. Thanks, Benoit -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 0/5] Add more device nodes for am43x-epos-evm
+ Andrew Morton. Ping on this. On Wednesday 27 November 2013 01:00 PM, Sourav Poddar wrote: The patch series adds support for enabling pwm backlight, i2c2, spi and matrix gpio keys on am43x-gp-evm. Done on top of 3.13-rc1 + tero clock series(1) [1]: https://patchwork.kernel.org/patch/3009541/ Tested on am43x-gp-evm. There is a some bug while using regulators through backlight driver on 3.13-rc1. So, tested pwm part with this temporary patch[2]. [2]: http://www.spinics.net/lists/arm-kernel/msg288215.html Darren Etheridge (1): pinctrl: am43xx: dt-bindings: add MUX_MODE8 Sourav Poddar (4): arm: dts: am4372: Add pwm-cellsproperty for ecap device. arm: dts: am43x-epos-evm: Add I2C data. arm: dts: am43x-epos-evm: Add SPI data. ARM: dts: am43x-epos-evm: Add pwm backlight support. arch/arm/boot/dts/am4372.dtsi|9 + arch/arm/boot/dts/am43x-epos-evm.dts | 67 ++ include/dt-bindings/pinctrl/am43xx.h |1 + 3 files changed, 77 insertions(+), 0 deletions(-) -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCHv2 07/10] drivers: mtd: m25p80: Adapt driver to support memory mapped read.
On Thursday 12 December 2013 01:25 PM, Huang Shijie wrote:
On Fri, Dec 06, 2013 at 07:54:48PM +0530, Sourav Poddar wrote:
Adapt driver to do a memory mapped read.
@@ -109,6 +109,7 @@ struct m25p {
u8 program_opcode;
u8 *command;
enum read_type flash_read;
+ void __iomem *mem_addr;
I think we can remove this field.
You can use a local variable in the m25p80_read.
};
static inline struct m25p *mtd_to_m25p(struct mtd_info *mtd)
@@ -515,6 +516,7 @@ static int m25p80_read(struct mtd_info *mtd, loff_t from,
size_t len,
size_t *retlen, u_char *buf)
{
struct m25p *flash = mtd_to_m25p(mtd);
+ struct spi_master *master = flash-spi-master;
struct spi_transfer t[2];
struct spi_message m;
uint8_t opcode;
@@ -523,6 +525,20 @@ static int m25p80_read(struct mtd_info *mtd, loff_t from,
size_t len,
pr_debug(%s: %s from 0x%08x, len %zd\n, dev_name(flash-spi-dev),
__func__, (u32)from, len);
+ if (master-mmap) {
+ mutex_lock(flash-lock);
+ /* Wait till previous write/erase is done. */
+ if (wait_till_ready(flash)) {
+ mutex_unlock(flash-lock);
+ return 1;
+ }
+ flash-mem_addr = master-get_buf(master);
+ memcpy(buf, flash-mem_addr + from, len);
+ master-put_buf(master);
+ *retlen = len;
+ goto out;
+ }
+
spi_message_init(m);
memset(t, 0, (sizeof t));
@@ -558,6 +574,7 @@ static int m25p80_read(struct mtd_info *mtd, loff_t from,
size_t len,
*retlen = m.actual_length - m25p_cmdsz(flash) - dummy;
+out:
mutex_unlock(flash-lock);
return 0;
@@ -1286,6 +1303,9 @@ static int m25p_probe(struct spi_device *spi)
flash-addr_width = 3;
}
+ if (spi-master-configure_from_slave)
+ m25p80_fill_flash_information(flash);
+
You have add a configure_from_slave hook in the SPI, why you also need
a same hook in the SPI-NOR framework?
We need a way to provoke this, currently it is placed in m25p80. If m25p80
is removed, for where should I handle these in nor framework?
And i think the enable_mmap/disable_mmap is not needed too.
All the three hooks are used to set the SPI bus controller.
And the SPI-NOR framework only handles the issues between the
SPI bus controller and the SPI-NOR, or the SPI-NOR controller and the
SPI-NOR.
My controller can be used as spi flash controller as well as a spi
controller.
thanks
Huang Shijie
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Re: [PATCHv2 09/10] arm: dts: dra7: Add qspi device.
Hi Mark, On Tuesday 10 December 2013 04:01 PM, Mark Brown wrote: On Tue, Dec 10, 2013 at 09:55:15AM +0530, Sourav Poddar wrote: I posted this for review along with other code changes. I will post them seperately to Benoit. Please wait until the driver updates have been reviewed. I was thinking of sending this dts patches seperately to benoit, so that we can enable atleast 1/4 bit mode for our controller. Anyways, there is no memory mapped specific binding used. Once, we get our driver updates reviewed and *if* there is anything memory mapped specific added, I can send them as a seperate patch. Anyways with spi nor framework in sight the driver uodates can go anyewhere and might take some time. . Does this sound Ok to you? -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCHv2 09/10] arm: dts: dra7: Add qspi device.
On Tuesday 10 December 2013 04:01 PM, Mark Brown wrote: On Tue, Dec 10, 2013 at 09:55:15AM +0530, Sourav Poddar wrote: I posted this for review along with other code changes. I will post them seperately to Benoit. Please wait until the driver updates have been reviewed. Ok. -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCHv2 05/10] spi/qspi: Add api for get_buf/put_buf.
On Tuesday 10 December 2013 06:28 PM, Marek Vasut wrote:
On Friday, December 06, 2013 at 03:24:46 PM, Sourav Poddar wrote:
Adapt qspi driver to use (get_buf/put_buf) pointers added
earlier.
These can be called just before the memcpy operations to get hold
of the memory mapped address and to turn on the controller clocks.
Signed-off-by: Sourav Poddarsourav.pod...@ti.com
---
v1-v2:
enable/disable memory mapped only when get_buf/put_buf is
called (basicaaly only when memory mapped read operation is
desired).
drivers/spi/spi-ti-qspi.c | 19 +++
1 files changed, 19 insertions(+), 0 deletions(-)
diff --git a/drivers/spi/spi-ti-qspi.c b/drivers/spi/spi-ti-qspi.c
index e4a8afc..b83583c 100644
--- a/drivers/spi/spi-ti-qspi.c
+++ b/drivers/spi/spi-ti-qspi.c
@@ -248,6 +248,23 @@ static void ti_qspi_configure_from_slave(struct
spi_device *spi) ti_qspi_write(qspi, memval, QSPI_SPI_SETUP0_REG);
}
+static inline int __iomem *ti_qspi_get_mem_buf(struct spi_master *master)
Should this not be a 'void __iomem *' instead of 'int __iomem *' in any case ?
Yes, it should be. Will fix in v3.
+{
+ struct ti_qspi *qspi = spi_master_get_devdata(master);
+
+ pm_runtime_get_sync(qspi-dev);
+ enable_qspi_memory_mapped(qspi);
+ return qspi-mmap_base;
+}
+
+static void ti_qspi_put_mem_buf(struct spi_master *master)
+{
+ struct ti_qspi *qspi = spi_master_get_devdata(master);
+
+ disable_qspi_memory_mapped(qspi);
+ pm_runtime_put(qspi-dev);
+}
+
static void ti_qspi_restore_ctx(struct ti_qspi *qspi)
{
struct ti_qspi_regs *ctx_reg =qspi-ctx_reg;
@@ -517,6 +534,8 @@ static int ti_qspi_probe(struct platform_device *pdev)
master-bits_per_word_mask = BIT(32 - 1) | BIT(16 - 1) | BIT(8 - 1);
master-mmap = true;
master-configure_from_slave = ti_qspi_configure_from_slave;
+ master-get_buf = ti_qspi_get_mem_buf;
+ master-put_buf = ti_qspi_put_mem_buf;
if (!of_property_read_u32(np, num-cs,num_cs))
master-num_chipselect = num_cs;
Best regards,
Marek Vasut
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Re: [PATCHv2 04/10] spi/qspi: configure set up register for memory map.
On Tuesday 10 December 2013 06:27 PM, Marek Vasut wrote:
On Friday, December 06, 2013 at 03:24:45 PM, Sourav Poddar wrote:
These add api to configure set up registers which will be used
for memory mapped operations.
These was provided as a pointer in the earlier patch and can be
used by the slave devices to configure the master controller as an
when required according to the usecases.
Signed-off-by: Sourav Poddarsourav.pod...@ti.com
---
drivers/spi/spi-ti-qspi.c | 29 +
1 files changed, 29 insertions(+), 0 deletions(-)
diff --git a/drivers/spi/spi-ti-qspi.c b/drivers/spi/spi-ti-qspi.c
index 48294d1..e4a8afc 100644
--- a/drivers/spi/spi-ti-qspi.c
+++ b/drivers/spi/spi-ti-qspi.c
@@ -117,6 +117,10 @@ struct ti_qspi {
#define MEM_CS(1 8)
#define MEM_CS_DIS(0 8)
+#define QSPI_SETUP0_RD_NORMAL (0x0 12)
+#define QSPI_SETUP0_RD_DUAL (0x1 12)
+#define QSPI_SETUP0_RD_QUAD (0x3 12)
+
#define QSPI_FRAME 4096
#define QSPI_AUTOSUSPEND_TIMEOUT 2000
@@ -220,6 +224,30 @@ static int ti_qspi_setup(struct spi_device *spi)
return 0;
}
+static void ti_qspi_configure_from_slave(struct spi_device *spi)
+{
+ struct ti_qspi *qspi = spi_master_get_devdata(spi-master);
+ struct slave_info info = spi-info;
+ u32 memval, mode;
+
+ mode = spi-mode (SPI_RX_DUAL | SPI_RX_QUAD);
+ memval = (info.read_opcode 0) | (info.program_opcode 16) |
+ ((info.addr_width - 1) 8) | (info.dummy_cycles 10);
+
+ switch (mode) {
+ case SPI_RX_DUAL:
+ memval |= QSPI_SETUP0_RD_DUAL;
+ break;
+ case SPI_RX_QUAD:
+ memval |= QSPI_SETUP0_RD_QUAD;
+ break;
+ default:
You want to catch invalid/unsupported mode here instead, so please add 'case 0:'
for 1-bit transfer and treat default: as an error .
Ok. make sense. will change that in v3.
+ memval |= QSPI_SETUP0_RD_NORMAL;
+ break;
+ }
+ ti_qspi_write(qspi, memval, QSPI_SPI_SETUP0_REG);
+}
+
static void ti_qspi_restore_ctx(struct ti_qspi *qspi)
{
struct ti_qspi_regs *ctx_reg =qspi-ctx_reg;
@@ -488,6 +516,7 @@ static int ti_qspi_probe(struct platform_device *pdev)
master-dev.of_node = pdev-dev.of_node;
master-bits_per_word_mask = BIT(32 - 1) | BIT(16 - 1) | BIT(8 - 1);
master-mmap = true;
+ master-configure_from_slave = ti_qspi_configure_from_slave;
if (!of_property_read_u32(np, num-cs,num_cs))
master-num_chipselect = num_cs;
Best regards,
Marek Vasut
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Re: [PATCHv2 00/10] Add memory mapped support for ti qspi, m25p80 serial flash.
Hi Marek, On Tuesday 10 December 2013 06:19 PM, Marek Vasut wrote: On Friday, December 06, 2013 at 03:24:41 PM, Sourav Poddar wrote: The patch series aims to add memory mapped support for TI qspi contoller and also add support for the same in serial flash driver(m25p80). My question is, shall we not wait for the new SPI NOR framework to be well fleshed out and only then implement this controller driver on top of it ? I think it will still take lot of time for spi framework to come to alignment and get merged in the mainline. Till then, m25p80 development should go on independently. Once, the spi framework is ready, I can myself port this into the new framework. I have a feeling this patchset adds quite a lot of ad-hoc hacks into the m25p80 driver, which would become dead code once converted to the SPI NOR framework. I dont think that spi framework till now provides capabilities which can be used to handle memory mapped cases. I did a quad mode support for m25p80 which easily got cloned into the new spi framework. Same can be done for the memory mapped support too Best regards, Marek Vasut -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCHv2 00/10] Add memory mapped support for ti qspi, m25p80 serial flash.
On Tuesday 10 December 2013 11:52 PM, Marek Vasut wrote: On Tuesday, December 10, 2013 at 05:11:43 PM, Mark Brown wrote: On Tue, Dec 10, 2013 at 01:49:13PM +0100, Marek Vasut wrote: My question is, shall we not wait for the new SPI NOR framework to be well fleshed out and only then implement this controller driver on top of it ? I have a feeling this patchset adds quite a lot of ad-hoc hacks into the m25p80 driver, which would become dead code once converted to the SPI NOR framework. There is some stuff that pushes up into the controller in that while the device is in memory mapped mode as far as I can tell it's not safe to do other accesses so if someone's put more than one device on the SPI bus we need to handle interactions there. OK, so it's either-or . That seems OK, you might want to have two drivers for this ip block, one to handle it as a SPI block and one to handle it as a SPI-NOR block. ... that is of course, if these two modes can't work together. the two modes cant work together. Best regards, Marek Vasut -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCHv2 00/10] Add memory mapped support for ti qspi, m25p80 serial flash.
Hi Mark,
On Tuesday 10 December 2013 11:59 PM, Mark Brown wrote:
On Tue, Dec 10, 2013 at 07:22:10PM +0100, Marek Vasut wrote:
On Tuesday, December 10, 2013 at 05:11:43 PM, Mark Brown wrote:
There is some stuff that pushes up into the controller in that while the
device is in memory mapped mode as far as I can tell it's not safe to do
other accesses so if someone's put more than one device on the SPI bus
we need to handle interactions there.
OK, so it's either-or . That seems OK, you might want to have two drivers for
this ip block, one to handle it as a SPI block and one to handle it as a SPI-NOR
block. ... that is of course, if these two modes can't work together.
Or the client disables the memory map when it's not actively being used
and the stops other transfers starting while the mapping is in place.
I'd expect we'll have to cope with shared use at some point, hardware
engineers will probably build such systems.
So, what I am doing here in my code is that whenever I desired to use a
mmap operations I do a
a. flash_lock()
b. wait till the previous erase/write is finished
c. 'get_buf' which in turn does
- get_sync
- enable memory mapped
d. memcpy
e. 'put_buf' which in turn does
- disable memory mapped
- put_sync
f. flash_unlock
Do you see any point missing here?
On your comment about disabling transfers while doing a mmap..
Are you suggesting on having a check in qspi transfer api something like
this..
transfer_one_message {
if (mmap)
return -EINPROGRESS;
}
Where mmap can be set/unset in get_buf/put_buf respectively.
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Re: [PATCHv2 09/10] arm: dts: dra7: Add qspi device.
On Monday 09 December 2013 11:12 PM, Tony Lindgren wrote:
* Sourav Poddarsourav.pod...@ti.com [131206 06:29]:
These add device tree entry for qspi controller driver on dra7.
FYI these .dts changes need to be queued separately by Benoit and
should be posted as a seprate series in general to avoid confusion.
Ok, thanks!
I posted this for review along with other code changes.
I will post them seperately to Benoit.
Regards,
Tony
Signed-off-by: Sourav Poddarsourav.pod...@ti.com
---
v1-v2:
use MUX_MODE1 instead of numeric value
arch/arm/boot/dts/dra7-evm.dts | 32
arch/arm/boot/dts/dra7.dtsi| 13 +
2 files changed, 45 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index 5babba0..4a57fdf 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -93,6 +93,21 @@
0x24c (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */
;
};
+
+ qspi1_pins: pinmux_qspi1_pins {
+ pinctrl-single,pins =
+ 0x4c (PIN_INPUT | MUX_MODE1) /* gpmc_a3.qspi1_cs2 */
+ 0x50 (PIN_INPUT | MUX_MODE1) /* gpmc_a4.qspi1_cs3 */
+ 0x74 (PIN_INPUT | MUX_MODE1) /* gpmc_a13.qspi1_rtclk */
+ 0x78 (PIN_INPUT | MUX_MODE1) /* gpmc_a14.qspi1_d3 */
+ 0x7c (PIN_INPUT | MUX_MODE1) /* gpmc_a15.qspi1_d2 */
+ 0x80 (PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d1 */
+ 0x84 (PIN_INPUT | MUX_MODE1) /* gpmc_a17.qspi1_d0 */
+ 0x88 (PIN_INPUT | MUX_MODE1) /* qpmc_a18.qspi1_sclk */
+ 0xb8 (PIN_INPUT_PULLUP | MUX_MODE1) /*
gpmc_cs2.qspi1_cs0 */
+ 0xbc (PIN_INPUT_PULLUP | MUX_MODE1) /*
gpmc_cs3.qspi1_cs1 */
+ ;
+ };
};
i2c1 {
@@ -273,3 +288,20 @@
cpu0 {
cpu0-supply =smps123_reg;
};
+
+qspi {
+ status = okay;
+ pinctrl-names = default;
+ pinctrl-0 =qspi1_pins;
+
+ spi-max-frequency =4800;
+ m25p80@0 {
+ compatible = s25fl256s1;
+ spi-max-frequency =4800;
+ reg =0;
+ spi-tx-bus-width =1;
+ spi-rx-bus-width =4;
+ spi-cpol;
+ spi-cpha;
+ };
+};
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 67275c8..b06d899 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -582,6 +582,19 @@
dma-names = tx0, rx0;
status = disabled;
};
+
+ qspi: qspi@4b30 {
+ compatible = ti,dra7xxx-qspi;
+ reg =0x4b30 0x100,0x4a002558 0x4,
+ 0x5c00 0x3ff;
+ reg-names = qspi_base, qspi_ctrlmod, qspi_mmap;
+ #address-cells =1;
+ #size-cells =0;
+ ti,hwmods = qspi;
+ num-cs =4;
+ interrupts =0 124 0x4;
+ status = disabled;
+ };
};
clocks {
--
1.7.1
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[PATCHv2 00/10] Add memory mapped support for ti qspi, m25p80 serial flash.
The patch series aims to add memory mapped support for TI qspi contoller and also add support for the same in serial flash driver(m25p80). These feature was added as a part of the series[1]: The series[1] add support for quad and memory mapped feature in spi and flash driver. Based on Brian Norris suggestion on splitting the quad and memory mapped feature, I had sent a seperate series for quad support which has beed accepted by Brian. The $subject patch series takes care of the memory mapped part. Overview of memory mapped support in qspi: TI qspi controller supports memory mapped read support, switching to which requires register modifications(qspi registers, control module register for DRA, qspi register for am43x). Once switched, the flash data can be available at a soc specific memory mapped address. For operations in normal mode, we need to keep memory mapped disable. Flow of the patch is to keep the memory mapped enable by default in the driver. Whenever Normal spi mode operations are desired, we switch to configuration mode and at the end of it memory mapped is again enabled. There are few function pointers added to fecilitate easy communication between the flash and spi controllers. Major changes in the $subject patch based on discussion in [1]: - Feature has been broken down into small meaningfl patches. - memcpy is done in flash driver and spi framework is bypassed. - configuration of memory mapped spi controller regsiters is done through function calls from flash side. [1]: http://lists.infradead.org/pipermail/linux-mtd/2013-October/049058.html v1-v2: Mentioned on individual patches. Overall change is the squashing of few patches. v1: https://patchwork.kernel.org/patch/3237091/ Tested on DRA7 board with spansion S25FL256S flash along with some internal irq crossbar patches. Tested on AM437x epos evm with macronix MX66l51235l flash. Testing done: -Erase the whole flash. -write to the flash -read back the flash - compare the data Sourav Poddar (10): spi/spi.h: Add get_buf/put_buf support in spi master.. spi/qspi: parse register by name. spi/qspi: Add support to switc to memory mapped operation. spi/qspi: configure set up register for memory map.. spi/qspi: Add api for get_buf/put_buf. drivers: mtd: m25p80: Add api to configure master register. drivers: mtd: m25p80: Adapt driver to support memory mapped read. Documentation: bindings: ti-qspi: update binding information. arm: dts: dra7: Add qspi device. arm: dts: am43x-epos: Add qspi device. Documentation/devicetree/bindings/spi/ti_qspi.txt |8 +- arch/arm/boot/dts/am4372.dtsi | 12 ++ arch/arm/boot/dts/am43x-epos-evm.dts | 28 + arch/arm/boot/dts/dra7-evm.dts| 32 + arch/arm/boot/dts/dra7.dtsi | 13 ++ drivers/mtd/devices/m25p80.c | 38 ++ drivers/spi/spi-ti-qspi.c | 130 - include/linux/spi/spi.h | 22 8 files changed, 280 insertions(+), 3 deletions(-) -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCHv2 01/10] spi/spi.h: Add get_buf/put_buf support in spi master.
Add get_buf, put_buf api support in spi master.
This can be used in a scenario where spi controller
supports memory mapped operations(typically with flash devices).
So, the memcpy needs top be done in slave devices which need the
required memory mapped address. These api can be used to get that
master address.
These can also be used to turm the master controller clock, as usually
the clocks get turned in spi core. But, in memory mapped case, we will
bypass the spi core and hence needa way out to turn on the controller clock.
Add configure from slave api, which can be used to configure the master
controller with slave specific information.
Add slave info struct, that can be filled with slave properties required by
master controller for its register configuration.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
v1-v2:
- Added a slave info structure.
- Merge all other header related patches into this.
include/linux/spi/spi.h | 22 ++
1 files changed, 22 insertions(+), 0 deletions(-)
diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h
index 8c62ba7..c91d883 100644
--- a/include/linux/spi/spi.h
+++ b/include/linux/spi/spi.h
@@ -31,6 +31,14 @@
*/
extern struct bus_type spi_bus_type;
+/* For SPI flash */
+struct slave_info {
+ u8 read_opcode;
+ u8 program_opcode;
+ u8 addr_width;
+ u8 dummy_cycles;
+};
+
/**
* struct spi_device - Master side proxy for an SPI slave device
* @dev: Driver model representation of the device.
@@ -73,6 +81,7 @@ extern struct bus_type spi_bus_type;
struct spi_device {
struct device dev;
struct spi_master *master;
+ struct slave_info info; /* flash devices */
u32 max_speed_hz;
u8 chip_select;
u16 mode;
@@ -291,6 +300,14 @@ static inline void spi_unregister_driver(struct spi_driver
*sdrv)
* number. Any individual value may be -ENOENT for CS lines that
* are not GPIOs (driven by the SPI controller itself).
*
+ * @get_buf: used for memory mapped cases, when the slave device wants to
+ * know the address to be used for memcopy.
+ * @put_buf: Used for memory mapped cases after get_buf, after the memcpy
+ * has finished.
+ * @configure_from_slave: Used when SPI controller has registers which need
+ * to be configured from slave specifics information(typical use case for
+ * SPI flash device).
+ * @mmap: Used to show that controller supports memory mapped operation.
* Each SPI master controller can communicate with one or more @spi_device
* children. These make a small bus, sharing MOSI, MISO and SCK signals
* but not chip select signals. Each device may be configured to use a
@@ -421,8 +438,13 @@ struct spi_master {
int (*transfer_one)(struct spi_master *master, struct spi_device *spi,
struct spi_transfer *transfer);
+ int __iomem *(*get_buf)(struct spi_master *master);
+ void(*put_buf)(struct spi_master *master);
+ void(*configure_from_slave)(struct spi_device *spi);
+
/* gpio chip select */
int *cs_gpios;
+ boolmmap;
};
static inline void *spi_master_get_devdata(struct spi_master *master)
--
1.7.1
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[PATCHv2 07/10] drivers: mtd: m25p80: Adapt driver to support memory mapped read.
Adapt driver to do a memory mapped read.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
v1-v2:
- Add a check to Wait for the previous erase/write to
finish.
- Ensure proper locking
drivers/mtd/devices/m25p80.c | 20
1 files changed, 20 insertions(+), 0 deletions(-)
diff --git a/drivers/mtd/devices/m25p80.c b/drivers/mtd/devices/m25p80.c
index b90c7e5..eb75d84 100644
--- a/drivers/mtd/devices/m25p80.c
+++ b/drivers/mtd/devices/m25p80.c
@@ -109,6 +109,7 @@ struct m25p {
u8 program_opcode;
u8 *command;
enum read_type flash_read;
+ void __iomem *mem_addr;
};
static inline struct m25p *mtd_to_m25p(struct mtd_info *mtd)
@@ -515,6 +516,7 @@ static int m25p80_read(struct mtd_info *mtd, loff_t from,
size_t len,
size_t *retlen, u_char *buf)
{
struct m25p *flash = mtd_to_m25p(mtd);
+ struct spi_master *master = flash-spi-master;
struct spi_transfer t[2];
struct spi_message m;
uint8_t opcode;
@@ -523,6 +525,20 @@ static int m25p80_read(struct mtd_info *mtd, loff_t from,
size_t len,
pr_debug(%s: %s from 0x%08x, len %zd\n, dev_name(flash-spi-dev),
__func__, (u32)from, len);
+ if (master-mmap) {
+ mutex_lock(flash-lock);
+ /* Wait till previous write/erase is done. */
+ if (wait_till_ready(flash)) {
+ mutex_unlock(flash-lock);
+ return 1;
+ }
+ flash-mem_addr = master-get_buf(master);
+ memcpy(buf, flash-mem_addr + from, len);
+ master-put_buf(master);
+ *retlen = len;
+ goto out;
+ }
+
spi_message_init(m);
memset(t, 0, (sizeof t));
@@ -558,6 +574,7 @@ static int m25p80_read(struct mtd_info *mtd, loff_t from,
size_t len,
*retlen = m.actual_length - m25p_cmdsz(flash) - dummy;
+out:
mutex_unlock(flash-lock);
return 0;
@@ -1286,6 +1303,9 @@ static int m25p_probe(struct spi_device *spi)
flash-addr_width = 3;
}
+ if (spi-master-configure_from_slave)
+ m25p80_fill_flash_information(flash);
+
dev_info(spi-dev, %s (%lld Kbytes)\n, id-name,
(long long)flash-mtd.size 10);
--
1.7.1
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[PATCHv2 10/10] arm: dts: am43x-epos: Add qspi device.
These add device tree entry for qspi controller driver on am43x-epos-evm.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
arch/arm/boot/dts/am4372.dtsi| 12
arch/arm/boot/dts/am43x-epos-evm.dts | 28
2 files changed, 40 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index f1dd131..5d029de 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -663,6 +663,18 @@
edma 11;
dma-names = tx, rx;
};
+
+ qspi: qspi@4790 {
+ compatible = ti,am4372-qspi;
+ reg = 0x4790 0x100, 0x3000 0x3ff;
+ reg-names = qspi_base, qspi_mmap;
+ #address-cells = 1;
+ #size-cells = 0;
+ ti,hwmods = qspi;
+ interrupts = 0 138 0x4;
+ num-cs = 4;
+ status = disabled;
+ };
};
clocks {
diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts
b/arch/arm/boot/dts/am43x-epos-evm.dts
index fbf9c4c..a037a92 100644
--- a/arch/arm/boot/dts/am43x-epos-evm.dts
+++ b/arch/arm/boot/dts/am43x-epos-evm.dts
@@ -79,6 +79,17 @@
0x18c (PIN_INPUT_PULLUP | SLEWCTRL_FAST |
MUX_MODE0)/* i2c0_scl.i2c0_scl */
;
};
+
+ qspi1_default: qspi1_default {
+ pinctrl-single,pins =
+ 0x7c (PIN_INPUT_PULLUP | MUX_MODE3)
+ 0x88 (PIN_INPUT_PULLUP | MUX_MODE2)
+ 0x90 (PIN_INPUT_PULLUP | MUX_MODE3)
+ 0x94 (PIN_INPUT_PULLUP | MUX_MODE3)
+ 0x98 (PIN_INPUT_PULLUP | MUX_MODE3)
+ 0x9c (PIN_INPUT_PULLUP | MUX_MODE3)
+ ;
+ };
};
matrix_keypad: matrix_keypad@0 {
@@ -184,3 +195,20 @@
gpio3 {
status = okay;
};
+
+qspi {
+ status = okay;
+ pinctrl-names = default;
+ pinctrl-0 = qspi1_default;
+
+ spi-max-frequency = 4800;
+ m25p80@0 {
+ compatible = mx66l51235l;
+ spi-max-frequency = 4800;
+ reg = 0;
+ spi-cpol;
+ spi-cpha;
+ spi-tx-bus-width = 1;
+ spi-rx-bus-width = 4;
+ };
+};
--
1.7.1
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[PATCHv2 09/10] arm: dts: dra7: Add qspi device.
These add device tree entry for qspi controller driver on dra7.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
v1-v2:
use MUX_MODE1 instead of numeric value
arch/arm/boot/dts/dra7-evm.dts | 32
arch/arm/boot/dts/dra7.dtsi| 13 +
2 files changed, 45 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index 5babba0..4a57fdf 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -93,6 +93,21 @@
0x24c (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */
;
};
+
+ qspi1_pins: pinmux_qspi1_pins {
+ pinctrl-single,pins =
+ 0x4c (PIN_INPUT | MUX_MODE1) /* gpmc_a3.qspi1_cs2 */
+ 0x50 (PIN_INPUT | MUX_MODE1) /* gpmc_a4.qspi1_cs3 */
+ 0x74 (PIN_INPUT | MUX_MODE1) /* gpmc_a13.qspi1_rtclk */
+ 0x78 (PIN_INPUT | MUX_MODE1) /* gpmc_a14.qspi1_d3 */
+ 0x7c (PIN_INPUT | MUX_MODE1) /* gpmc_a15.qspi1_d2 */
+ 0x80 (PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d1 */
+ 0x84 (PIN_INPUT | MUX_MODE1) /* gpmc_a17.qspi1_d0 */
+ 0x88 (PIN_INPUT | MUX_MODE1) /* qpmc_a18.qspi1_sclk */
+ 0xb8 (PIN_INPUT_PULLUP | MUX_MODE1) /*
gpmc_cs2.qspi1_cs0 */
+ 0xbc (PIN_INPUT_PULLUP | MUX_MODE1) /*
gpmc_cs3.qspi1_cs1 */
+ ;
+ };
};
i2c1 {
@@ -273,3 +288,20 @@
cpu0 {
cpu0-supply = smps123_reg;
};
+
+qspi {
+ status = okay;
+ pinctrl-names = default;
+ pinctrl-0 = qspi1_pins;
+
+ spi-max-frequency = 4800;
+ m25p80@0 {
+ compatible = s25fl256s1;
+ spi-max-frequency = 4800;
+ reg = 0;
+ spi-tx-bus-width = 1;
+ spi-rx-bus-width = 4;
+ spi-cpol;
+ spi-cpha;
+ };
+};
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 67275c8..b06d899 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -582,6 +582,19 @@
dma-names = tx0, rx0;
status = disabled;
};
+
+ qspi: qspi@4b30 {
+ compatible = ti,dra7xxx-qspi;
+ reg = 0x4b30 0x100, 0x4a002558 0x4,
+ 0x5c00 0x3ff;
+ reg-names = qspi_base, qspi_ctrlmod, qspi_mmap;
+ #address-cells = 1;
+ #size-cells = 0;
+ ti,hwmods = qspi;
+ num-cs = 4;
+ interrupts = 0 124 0x4;
+ status = disabled;
+ };
};
clocks {
--
1.7.1
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[PATCHv2 02/10] spi/qspi: parse register by name.
Modify the qspi driver to parse reg information by name.
If reg names is not found, then revert back to normal
get resource.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
v1-v2:
- if __byname variant is not found, go for standard
api. If both are not found, then the resource is considered
to be optional and is not required for the given SOC.
drivers/spi/spi-ti-qspi.c | 53 +++-
1 files changed, 51 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/spi-ti-qspi.c b/drivers/spi/spi-ti-qspi.c
index 033ef8d..a0cee08 100644
--- a/drivers/spi/spi-ti-qspi.c
+++ b/drivers/spi/spi-ti-qspi.c
@@ -46,6 +46,8 @@ struct ti_qspi {
struct spi_master *master;
void __iomem*base;
+ void __iomem*ctrl_base;
+ void __iomem*mmap_base;
struct clk *fclk;
struct device *dev;
@@ -54,6 +56,8 @@ struct ti_qspi {
u32 spi_max_frequency;
u32 cmd;
u32 dc;
+
+ bool ctrl_mod;
};
#define QSPI_PID (0x0)
@@ -437,7 +441,7 @@ static int ti_qspi_probe(struct platform_device *pdev)
{
struct ti_qspi *qspi;
struct spi_master *master;
- struct resource *r;
+ struct resource *r, *res_ctrl, *res_mmap;
struct device_node *np = pdev-dev.of_node;
u32 max_freq;
int ret = 0, num_cs, irq;
@@ -465,7 +469,35 @@ static int ti_qspi_probe(struct platform_device *pdev)
qspi-master = master;
qspi-dev = pdev-dev;
- r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ r = platform_get_resource_byname(pdev, IORESOURCE_MEM, qspi_base);
+ if (r == NULL) {
+ r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (r == NULL) {
+ dev_err(pdev-dev, missing platform data\n);
+ return -ENODEV;
+ }
+ }
+
+ res_mmap = platform_get_resource_byname(pdev,
+ IORESOURCE_MEM, qspi_mmap);
+ if (res_mmap == NULL) {
+ res_mmap = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+ if (res_mmap == NULL) {
+ dev_err(pdev-dev,
+ memory mapped resource not required\n);
+ return -ENODEV;
+ }
+ }
+
+ res_ctrl = platform_get_resource_byname(pdev,
+ IORESOURCE_MEM, qspi_ctrlmod);
+ if (res_ctrl == NULL) {
+ res_ctrl = platform_get_resource(pdev, IORESOURCE_MEM, 2);
+ if (res_ctrl == NULL) {
+ dev_dbg(pdev-dev,
+ control module resources not required\n);
+ }
+ }
irq = platform_get_irq(pdev, 0);
if (irq 0) {
@@ -481,6 +513,23 @@ static int ti_qspi_probe(struct platform_device *pdev)
goto free_master;
}
+ if (res_ctrl) {
+ qspi-ctrl_mod = true;
+ qspi-ctrl_base = devm_ioremap_resource(pdev-dev, res_ctrl);
+ if (IS_ERR(qspi-ctrl_base)) {
+ ret = PTR_ERR(qspi-ctrl_base);
+ goto free_master;
+ }
+ }
+
+ if (res_mmap) {
+ qspi-mmap_base = devm_ioremap_resource(pdev-dev, res_mmap);
+ if (IS_ERR(qspi-mmap_base)) {
+ ret = PTR_ERR(qspi-mmap_base);
+ goto free_master;
+ }
+ }
+
ret = devm_request_irq(pdev-dev, irq, ti_qspi_isr, 0,
dev_name(pdev-dev), qspi);
if (ret 0) {
--
1.7.1
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[PATCHv2 05/10] spi/qspi: Add api for get_buf/put_buf.
Adapt qspi driver to use (get_buf/put_buf) pointers added
earlier.
These can be called just before the memcpy operations to get hold
of the memory mapped address and to turn on the controller clocks.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
v1-v2:
enable/disable memory mapped only when get_buf/put_buf is
called (basicaaly only when memory mapped read operation is
desired).
drivers/spi/spi-ti-qspi.c | 19 +++
1 files changed, 19 insertions(+), 0 deletions(-)
diff --git a/drivers/spi/spi-ti-qspi.c b/drivers/spi/spi-ti-qspi.c
index e4a8afc..b83583c 100644
--- a/drivers/spi/spi-ti-qspi.c
+++ b/drivers/spi/spi-ti-qspi.c
@@ -248,6 +248,23 @@ static void ti_qspi_configure_from_slave(struct spi_device
*spi)
ti_qspi_write(qspi, memval, QSPI_SPI_SETUP0_REG);
}
+static inline int __iomem *ti_qspi_get_mem_buf(struct spi_master *master)
+{
+ struct ti_qspi *qspi = spi_master_get_devdata(master);
+
+ pm_runtime_get_sync(qspi-dev);
+ enable_qspi_memory_mapped(qspi);
+ return qspi-mmap_base;
+}
+
+static void ti_qspi_put_mem_buf(struct spi_master *master)
+{
+ struct ti_qspi *qspi = spi_master_get_devdata(master);
+
+ disable_qspi_memory_mapped(qspi);
+ pm_runtime_put(qspi-dev);
+}
+
static void ti_qspi_restore_ctx(struct ti_qspi *qspi)
{
struct ti_qspi_regs *ctx_reg = qspi-ctx_reg;
@@ -517,6 +534,8 @@ static int ti_qspi_probe(struct platform_device *pdev)
master-bits_per_word_mask = BIT(32 - 1) | BIT(16 - 1) | BIT(8 - 1);
master-mmap = true;
master-configure_from_slave = ti_qspi_configure_from_slave;
+ master-get_buf = ti_qspi_get_mem_buf;
+ master-put_buf = ti_qspi_put_mem_buf;
if (!of_property_read_u32(np, num-cs, num_cs))
master-num_chipselect = num_cs;
--
1.7.1
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[PATCHv2 03/10] spi/qspi: Add support to switc to memory mapped operation.
These add apis that can be used to switch to memory mapped operatons
by configuring control module and qspi registers.
It also add master-mmap property to show that qspi
supports memory mapped operation.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
v1-v2:
Squash a patch to add mater-mmap here itself.
drivers/spi/spi-ti-qspi.c | 29 +
1 files changed, 29 insertions(+), 0 deletions(-)
diff --git a/drivers/spi/spi-ti-qspi.c b/drivers/spi/spi-ti-qspi.c
index a0cee08..48294d1 100644
--- a/drivers/spi/spi-ti-qspi.c
+++ b/drivers/spi/spi-ti-qspi.c
@@ -113,6 +113,10 @@ struct ti_qspi {
#define QSPI_CSPOL(n) (1 (1 + n * 8))
#define QSPI_CKPOL(n) (1 (n * 8))
+#define MM_SWITCH (1 0)
+#define MEM_CS (1 8)
+#define MEM_CS_DIS (0 8)
+
#defineQSPI_FRAME 4096
#define QSPI_AUTOSUSPEND_TIMEOUT 2000
@@ -129,6 +133,30 @@ static inline void ti_qspi_write(struct ti_qspi *qspi,
writel(val, qspi-base + reg);
}
+static void enable_qspi_memory_mapped(struct ti_qspi *qspi)
+{
+ u32 val;
+
+ ti_qspi_write(qspi, MM_SWITCH, QSPI_SPI_SWITCH_REG);
+ if (qspi-ctrl_mod) {
+ val = readl(qspi-ctrl_base);
+ val |= MEM_CS;
+ writel(val, qspi-ctrl_base);
+ }
+}
+
+static void disable_qspi_memory_mapped(struct ti_qspi *qspi)
+{
+ u32 val;
+
+ ti_qspi_write(qspi, ~MM_SWITCH, QSPI_SPI_SWITCH_REG);
+ if (qspi-ctrl_mod) {
+ val = readl(qspi-ctrl_base);
+ val = MEM_CS_DIS;
+ writel(val, qspi-ctrl_base);
+ }
+}
+
static int ti_qspi_setup(struct spi_device *spi)
{
struct ti_qspi *qspi = spi_master_get_devdata(spi-master);
@@ -459,6 +487,7 @@ static int ti_qspi_probe(struct platform_device *pdev)
master-transfer_one_message = ti_qspi_start_transfer_one;
master-dev.of_node = pdev-dev.of_node;
master-bits_per_word_mask = BIT(32 - 1) | BIT(16 - 1) | BIT(8 - 1);
+ master-mmap = true;
if (!of_property_read_u32(np, num-cs, num_cs))
master-num_chipselect = num_cs;
--
1.7.1
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[PATCHv2 08/10] Documentation: bindings: ti-qspi: update binding information.
These update binding information for ti qspi controller.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
v1-v2:
Add 'reg-names' variables used in dts files.
Documentation/devicetree/bindings/spi/ti_qspi.txt |8 +++-
1 files changed, 7 insertions(+), 1 deletions(-)
diff --git a/Documentation/devicetree/bindings/spi/ti_qspi.txt
b/Documentation/devicetree/bindings/spi/ti_qspi.txt
index 1f9641a..601a360 100644
--- a/Documentation/devicetree/bindings/spi/ti_qspi.txt
+++ b/Documentation/devicetree/bindings/spi/ti_qspi.txt
@@ -3,6 +3,11 @@ TI QSPI controller.
Required properties:
- compatible : should be ti,dra7xxx-qspi or ti,am4372-qspi.
- reg: Should contain QSPI registers location and length.
+- reg-names: Should contain the resource reg names.
+ - qspi_base: Qspi configuration register Address space
+ - qspi_mmap: Memory mapped Address space
+ - (optional) qspi_ctrlmod: Control module Address space
+- interrupts: should contain the qspi interrupt number.
- #address-cells, #size-cells : Must be present if the device has sub-nodes
- ti,hwmods: Name of the hwmod associated to the QSPI
@@ -14,7 +19,8 @@ Example:
qspi: qspi@4b30 {
compatible = ti,dra7xxx-qspi;
- reg = 0x4b30 0x100;
+ reg = 0x4790 0x100, 0x3000 0x3ff;
+ reg-names = qspi_base, qspi_mmap;
#address-cells = 1;
#size-cells = 0;
spi-max-frequency = 2500;
--
1.7.1
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[PATCHv2 06/10] drivers: mtd: m25p80: Add api to configure master register.
These can be used to fill information needed to configure
master controller registers.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
v1-v2:
instead of a u8 *val, use a struct (slave_info) already defined
in the first patch of the series. This will allow us to add more
parameters into the struct.
drivers/mtd/devices/m25p80.c | 18 ++
1 files changed, 18 insertions(+), 0 deletions(-)
diff --git a/drivers/mtd/devices/m25p80.c b/drivers/mtd/devices/m25p80.c
index 7dc2c14..b90c7e5 100644
--- a/drivers/mtd/devices/m25p80.c
+++ b/drivers/mtd/devices/m25p80.c
@@ -490,6 +490,24 @@ static inline int m25p80_dummy_cycles_read(struct m25p
*flash)
}
/*
+ * This API can be used to transfer flash information to
+ * SPI controller which needs some of its registers to get
+ * configured on flash information.
+ */
+static void m25p80_fill_flash_information(struct m25p *flash)
+{
+ struct spi_device *spi = flash-spi;
+ struct spi_master *master = spi-master;
+
+ spi-info.read_opcode = flash-read_opcode;
+ spi-info.program_opcode = flash-program_opcode;
+ spi-info.addr_width = flash-addr_width;
+ spi-info.dummy_cycles = m25p80_dummy_cycles_read(flash);
+
+ master-configure_from_slave(flash-spi);
+}
+
+/*
* Read an address range from the flash chip. The address range
* may be any size provided it is within the physical boundaries.
*/
--
1.7.1
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[PATCHv2 04/10] spi/qspi: configure set up register for memory map.
These add api to configure set up registers which will be used
for memory mapped operations.
These was provided as a pointer in the earlier patch and can be
used by the slave devices to configure the master controller as an
when required according to the usecases.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
drivers/spi/spi-ti-qspi.c | 29 +
1 files changed, 29 insertions(+), 0 deletions(-)
diff --git a/drivers/spi/spi-ti-qspi.c b/drivers/spi/spi-ti-qspi.c
index 48294d1..e4a8afc 100644
--- a/drivers/spi/spi-ti-qspi.c
+++ b/drivers/spi/spi-ti-qspi.c
@@ -117,6 +117,10 @@ struct ti_qspi {
#define MEM_CS (1 8)
#define MEM_CS_DIS (0 8)
+#define QSPI_SETUP0_RD_NORMAL (0x0 12)
+#define QSPI_SETUP0_RD_DUAL (0x1 12)
+#define QSPI_SETUP0_RD_QUAD (0x3 12)
+
#defineQSPI_FRAME 4096
#define QSPI_AUTOSUSPEND_TIMEOUT 2000
@@ -220,6 +224,30 @@ static int ti_qspi_setup(struct spi_device *spi)
return 0;
}
+static void ti_qspi_configure_from_slave(struct spi_device *spi)
+{
+ struct ti_qspi *qspi = spi_master_get_devdata(spi-master);
+ struct slave_info info = spi-info;
+ u32 memval, mode;
+
+ mode = spi-mode (SPI_RX_DUAL | SPI_RX_QUAD);
+ memval = (info.read_opcode 0) | (info.program_opcode 16) |
+ ((info.addr_width - 1) 8) | (info.dummy_cycles 10);
+
+ switch (mode) {
+ case SPI_RX_DUAL:
+ memval |= QSPI_SETUP0_RD_DUAL;
+ break;
+ case SPI_RX_QUAD:
+ memval |= QSPI_SETUP0_RD_QUAD;
+ break;
+ default:
+ memval |= QSPI_SETUP0_RD_NORMAL;
+ break;
+ }
+ ti_qspi_write(qspi, memval, QSPI_SPI_SETUP0_REG);
+}
+
static void ti_qspi_restore_ctx(struct ti_qspi *qspi)
{
struct ti_qspi_regs *ctx_reg = qspi-ctx_reg;
@@ -488,6 +516,7 @@ static int ti_qspi_probe(struct platform_device *pdev)
master-dev.of_node = pdev-dev.of_node;
master-bits_per_word_mask = BIT(32 - 1) | BIT(16 - 1) | BIT(8 - 1);
master-mmap = true;
+ master-configure_from_slave = ti_qspi_configure_from_slave;
if (!of_property_read_u32(np, num-cs, num_cs))
master-num_chipselect = num_cs;
--
1.7.1
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Re: [PATCH 00/17] Add memory mapped support for ti qspi, m25p80 serial flash.
Hi Brian, On Tuesday 26 November 2013 01:04 PM, Sourav Poddar wrote: The patch series aims to add memory mapped support for TI qspi contoller and also add support for the same in serial flash driver(m25p80). These feature was added as a part of the series[1]: The series[1] add support for quad and memory mapped feature in spi and flash driver. Based on Brian Norris suggestion on splitting the quad and memory mapped feature, I had sent a seperate series for quad support which has beed accepted by Brian. The $subject patch series takes care of the memory mapped part. Overview of memory mapped support in qspi: TI qspi controller supports memory mapped read support, switching to which requires register modifications(qspi registers, control module register for DRA, qspi register for am43x). Once switched, the flash data can be available at a soc specific memory mapped address. For operations in normal mode, we need to keep memory mapped disable. Flow of the patch is to keep the memory mapped enable by default in the driver. Whenever Normal spi mode operations are desired, we switch to configuration mode and at the end of it memory mapped is again enabled. There are few function pointers added to fecilitate easy communication between the flash and spi controllers. Major changes in the $subject patch based on discussion in [1]: - Feature has been broken down into small meaningfl patches. - memcpy is done in flash driver and spi framework is bypassed. - configuration of memory mapped spi controller regsiters is done through function calls from flash side. [1]: http://lists.infradead.org/pipermail/linux-mtd/2013-October/049058.html Tested on DRA7 board with spansion S25FL256S flash along with some internal irq crossbar patches. Tested on AM437x epos evm with macronix MX66l51235l flash. Testing done: -Erase the whole flash. -write to the flash -read back the flash - compare the data Sourav Poddar (17): spi/spi.h: Add get_buf/put_buf support in spi master.. spi/spi.h: Add configure from slave support. spi/qspi: parse register by name. spi/qspi: parse control module register. spi/qspi: parse memory map register. spi/qspi: Add support to switc to memory mapped operation. spi/qspi: configure set up register for memory map.. spi/qspi: Add api for get_buf/put_buf. spi/spi.h: Add mem variable in spi master. spi/spi.h: Add mmap flag in spi master. spi/qspi: set mmap flag to true. spi/qspi: convert driver to enable/disable memory mapped.. drivers: mtd: m25p80: Add api to configure master register . drivers: mtd: m25p80: Adapt driver to support memory mapped read. arm: dts: dra7: Add qspi device. arm: dts: am43x-epos: Add qspi device. Documentation: bindings: ti-qspi: update binding information. Documentation/devicetree/bindings/spi/ti_qspi.txt |2 + arch/arm/boot/dts/am4372.dtsi | 12 ++ arch/arm/boot/dts/am43x-epos-evm.dts | 28 + arch/arm/boot/dts/dra7-evm.dts| 32 ++ arch/arm/boot/dts/dra7.dtsi | 13 +++ drivers/mtd/devices/m25p80.c | 30 ++ drivers/spi/spi-ti-qspi.c | 115 - include/linux/spi/spi.h | 16 +++ 8 files changed, 246 insertions(+), 2 deletions(-) Gentle ping on this series on mtd side... -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 0/5] Add more device nodes for am43x-epos-evm
On Wednesday 27 November 2013 01:00 PM, Sourav Poddar wrote: The patch series adds support for enabling pwm backlight, i2c2, spi and matrix gpio keys on am43x-gp-evm. Done on top of 3.13-rc1 + tero clock series(1) [1]: https://patchwork.kernel.org/patch/3009541/ Tested on am43x-gp-evm. There is a some bug while using regulators through backlight driver on 3.13-rc1. So, tested pwm part with this temporary patch[2]. [2]: http://www.spinics.net/lists/arm-kernel/msg288215.html Darren Etheridge (1): pinctrl: am43xx: dt-bindings: add MUX_MODE8 Sourav Poddar (4): arm: dts: am4372: Add pwm-cellsproperty for ecap device. arm: dts: am43x-epos-evm: Add I2C data. arm: dts: am43x-epos-evm: Add SPI data. ARM: dts: am43x-epos-evm: Add pwm backlight support. arch/arm/boot/dts/am4372.dtsi|9 + arch/arm/boot/dts/am43x-epos-evm.dts | 67 ++ include/dt-bindings/pinctrl/am43xx.h |1 + 3 files changed, 77 insertions(+), 0 deletions(-) gentle ping on this.. -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 0/3] Add more device nodes for am43x gp evm.
Hi Benoit, On Wednesday 27 November 2013 01:01 PM, Sourav Poddar wrote: The patch series adds support for enabling gpio, pwm backlight and matrix gpio keys on am43x-gp-evm. Done on top of 3.13-rc1 + tero clock series(1) + Afzal's basic gp support(2). [1]: https://patchwork.kernel.org/patch/3009541/ [2]: https://patchwork.kernel.org/patch/3171761/ Tested on am43x-gp-evm. There is a some bug while using regulators through backlight driver on 3.13-rc1. So, tested pwm part with this patch[3]. [3]: http://www.spinics.net/lists/arm-kernel/msg288215.html Sourav Poddar (3): arm: dts: am437x-gp-evm: Enable gpio. ARM: dts: am43x-gp-evm: Add matrix gpio keys. ARM: dts: am437x-gp-evm: Add pwm backlight support. arch/arm/boot/dts/am437x-gp-evm.dts | 53 +++ 1 files changed, 53 insertions(+), 0 deletions(-) Gentle pIng on this. -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] ARM: DTS: omap4-sdp: Add regulator for LCD backlight (pwm-backlight)
On Thursday 28 November 2013 02:58 PM, Peter Ujfalusi wrote: Since in DT booted kernel dummy regulators are no longer supported we need to provide valid phandle for the regulator needed by the backlight. On the board VBAT is used to power the LCD backlight(s). Signed-off-by: Peter Ujfalusipeter.ujfal...@ti.com --- Hi, This patch is needed for 3.13 to get the LCD backlight to work again. Is this usage of power supply a mandatory requirement? There is a thread which discusses this issue[1]: http://www.spinics.net/lists/arm-kernel/msg288215.html According to the above, regulator framework have support in 3.13-rc1 to returns a dummy regulator if there is none specified in the dts data. Thierry told that there seems to be a bug in regulator in handling these case. Though, I also posted a patch on pwm a couple of days ago[2] [2]: https://patchwork.kernel.org/patch/3246711/ I posted it without power-supply by testing it with the solution proposed in [1]. If I dont use the solution[1], it fails for me also. -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 03/17] spi/qspi: parse register by name.
On Thursday 28 November 2013 04:24 PM, Mark Brown wrote: On Thu, Nov 28, 2013 at 10:15:14AM +0530, Sourav Poddar wrote: On Tuesday 26 November 2013 05:54 PM, Mark Brown wrote: Do device tree binding changes early on in the series rather than at the end, one of the things that gets reviewed for is binding updates. Your code should also cope with the existing bindings, falling back on the current behaviour if it can't get the names or the extra resources. My current code only has a single resouce, hence *_byname* variants was not used. With extra resources, I am switching to byname variants, So, if a particular resource name is not found, it should just bypass that, thinking the resource is not required and should not resort to existing bindings.. That means that if you switch all resources to _byname then the driver won't find any resources at all and will fail. This will in turn mean that any device trees that work with the current code wil start failing, breaking compatibility. I am changing my code to use *byname for all resources. There is no dts available now in mainline using this code. I have added the dts file as patch 15, 16 of this series to take care of this. -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 12/17] spi/qspi: convert driver to enable/disable memory mapped.
On Thursday 28 November 2013 04:19 PM, Mark Brown wrote: On Thu, Nov 28, 2013 at 10:54:12AM +0530, Sourav Poddar wrote: At the beginning of this api, I am doing a disable memory mapped, as becuase of the code implemntation, if the control has reaches this api, memory mapped is not the desired operation. Then, at the end of this api after spi_finalize_current_message(master), which indicated the current transfer complete, I issue a end of transfer command. Only after which, I enable memory mapped mode again. So, will the condition you mention above will hit.? Please help me understand if i am missing something? Removing the mapping isn't going to stop another context which has obtained a handle on the map trying to look at the mapping. hmm..so the 'memcpy' part should be made atomic.(if possible?). -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 03/17] spi/qspi: parse register by name.
On Thursday 28 November 2013 04:41 PM, Mark Brown wrote: On Thu, Nov 28, 2013 at 04:28:07PM +0530, Sourav Poddar wrote: On Thursday 28 November 2013 04:24 PM, Mark Brown wrote: That means that if you switch all resources to _byname then the driver won't find any resources at all and will fail. This will in turn mean that any device trees that work with the current code wil start failing, breaking compatibility. I am changing my code to use *byname for all resources. There is no dts available now in mainline using this code. I have added the dts file as patch 15, 16 of this series to take care of this. We're now aiming for DT to be a stable interface and the existing binding has been included in a release so you really ought to be keeping compatiblity. Ok. So I will check for *byname, if not found I will switch to platform_get_resource. -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 12/17] spi/qspi: convert driver to enable/disable memory mapped.
On Thursday 28 November 2013 05:29 PM, Mark Brown wrote: On Thu, Nov 28, 2013 at 04:38:27PM +0530, Sourav Poddar wrote: On Thursday 28 November 2013 04:19 PM, Mark Brown wrote: Removing the mapping isn't going to stop another context which has obtained a handle on the map trying to look at the mapping. hmm..so the 'memcpy' part should be made atomic.(if possible?). Or holding the memory region should prevent normal SPI use (so any users ought to drop the memory region when they don't need it). hmm.ok i will unmap the memory region when not in use. I'm still a bit surprised there's no DMA controllers for this... Yes, but thats the truth :( -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
HDQ 1 Wire on AM43x
Hi, I am trying to cleanup and use HDQ 1wire on AM43x with 3.12-rc6 kernel. Slave device connected on my board is DS18B20, for which I have enabled the w1_therm.c driver. I populated the required hwmod entries and the log obtained is inlined[1]. Is there any way to test this out? In some older thread, I saw that there is some discussion on some 'hdq idle fixes' done to get the hdq working. ? I see a lot of sys entires, but all looks to be the attributes and could not figure out any slave where I can 'cat' the temperature data. Do I need to enable anything more apart from what my below configs looks like: # CONFIG_W1=y CONFIG_W1_CON=y # # 1-wire Bus Masters # # CONFIG_W1_MASTER_DS2490 is not set # CONFIG_W1_MASTER_DS2482 is not set # CONFIG_W1_MASTER_DS1WM is not set # CONFIG_W1_MASTER_GPIO is not set CONFIG_HDQ_MASTER_OMAP=y # # 1-wire Slaves # CONFIG_W1_SLAVE_THERM=y Thanks, Sourav [1]: Starting kernel ... [0.00] Booting Linux on physical CPU 0x0 [0.00] Linux version 3.12.0-67367-g2d1978c-dirty (a0131647@a0131647) (gcc version 4.7.3 20130226 (prerelease) (crosstool-NG linaro-1.13.1-4.7-2013.03 [0.00] CPU: ARMv7 Processor [412fc09a] revision 10 (ARMv7), cr=10c53c7d [0.00] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache [0.00] Machine: Generic AM43 (Flattened Device Tree), model: TI AM43x EPOS EVM [0.00] cma: CMA: reserved 16 MiB at 9e80 [0.00] Memory policy: ECC disabled, Data cache writeback [0.00] CPU: All CPU(s) started in SVC mode. [0.00] AM437x ES1.0 (sgx neon ) [0.00] PERCPU: Embedded 9 pages/cpu @c12c9000 s14656 r8192 d14016 u36864 [0.00] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 129280 [0.00] Kernel command line: root=/dev/ram0 rw mem=512M console=ttyO0,115200n8 initrd=0x8200,20M ramdisk_size=20480 no_console_suspend [0.00] PID hash table entries: 2048 (order: 1, 8192 bytes) [0.00] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes) [0.00] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes) [0.00] Memory: 464604K/521216K available (6012K kernel code, 690K rwdata, 2340K rodata, 426K init, 5536K bss, 56612K reserved, 0K highmem) [0.00] Virtual kernel memory layout: [0.00] vector : 0x - 0x1000 ( 4 kB) [0.00] fixmap : 0xfff0 - 0xfffe ( 896 kB) [0.00] vmalloc : 0xe080 - 0xff00 ( 488 MB) [0.00] lowmem : 0xc000 - 0xe000 ( 512 MB) [0.00] pkmap : 0xbfe0 - 0xc000 ( 2 MB) [0.00] modules : 0xbf00 - 0xbfe0 ( 14 MB) [0.00] .text : 0xc0008000 - 0xc083058c (8354 kB) [0.00] .init : 0xc0831000 - 0xc089b940 ( 427 kB) [0.00] .data : 0xc089c000 - 0xc0948b20 ( 691 kB) [0.00].bss : 0xc0948b20 - 0xc0eb0f00 (5537 kB) [0.00] Hierarchical RCU implementation. [0.00] RCU restricting CPUs from NR_CPUS=2 to nr_cpu_ids=1. [0.00] NR_IRQS:16 nr_irqs:16 16 [0.00] GIC CPU mask not found - kernel will fail to boot. [0.00] GIC CPU mask not found - kernel will fail to boot. [0.00] OMAP clockevent source: timer1 at 32786 Hz [0.00] sched_clock: 32 bits at 32kHz, resolution 30517ns, wraps every 131071999ms [0.00] OMAP clocksource: 32k_counter at 32768 Hz [0.00] Console: colour dummy device 80x30 . [2.861450] Driver for 1-wire Dallas network protocol. [2.878417] omap_hdq 48347000.hdq: OMAP HDQ Hardware Rev 0.:. Driver in Interrupt mode [3.250061] w1_master_driver w1_bus_master1: Family 1 for 01..3d is not registered. [3.262054] omap_wdt: OMAP Watchdog Timer Rev 0x01: initial timeout 60 sec [3.275054] edma-dma-engine edma-dma-engine.0: allocated channel for 0:25 [3.282073] edma-dma-engine edma-dma-engine.0: allocated channel for 0:24 [3.336029] ledtrig-cpu: registered to indicate activity on CPUs [3.342712] edma-dma-engine edma-dma-engine.0: allocated channel for 0:36 [3.349639] omap-sham 5310.sham: hw accel on OMAP rev 0.0 [3.364746] omap-aes 53501000.aes: OMAP AES hw accel rev: 0.1 [3.370758] edma-dma-engine edma-dma-engine.0: allocated channel for 0:5 .. [3.675811] platform connector.6: Driver connector-hdmi requests probe deferral [3.687438] drivers/rtc/hctosys.c: unable to open rtc device (rtc0) [3.712982] RAMDISK: ext2 filesystem found at block 0 [3.718017] RAMDISK: Loading 15360KiB [1 disk] into ram disk... [ 3.724517] connector-hdmi connector.6: failed to find video source [3.730957] platform connector.6: Driver connector-hdmi requests probe deferral done. [4.392822] EXT2-fs (ram0): warning: mounting unchecked fs, running e2fsck is recommended [4.401641] VFS: Mounted root (ext2 filesystem)
Re: [PATCH 0/5] Add more device nodes for am43x-epos-evm
On Wednesday 27 November 2013 01:38 PM, Sathya Prakash wrote: On Wednesday 27 November 2013 01:00 PM, Sourav Poddar wrote: The patch series adds support for enabling pwm backlight, i2c2, spi and matrix gpio keys on am43x-gp-evm. Seems a typo - series is for epos evm. Yes, true. The series if for epos. Done on top of 3.13-rc1 + tero clock series(1) [1]: https://patchwork.kernel.org/patch/3009541/ Tested on am43x-gp-evm. There is a some bug while using regulators through backlight driver on 3.13-rc1. So, tested pwm part with this temporary patch[2]. [2]: http://www.spinics.net/lists/arm-kernel/msg288215.html Darren Etheridge (1): pinctrl: am43xx: dt-bindings: add MUX_MODE8 Sourav Poddar (4): arm: dts: am4372: Add pwm-cellsproperty for ecap device. arm: dts: am43x-epos-evm: Add I2C data. arm: dts: am43x-epos-evm: Add SPI data. ARM: dts: am43x-epos-evm: Add pwm backlight support. arch/arm/boot/dts/am4372.dtsi|9 + arch/arm/boot/dts/am43x-epos-evm.dts | 67 ++ include/dt-bindings/pinctrl/am43xx.h |1 + 3 files changed, 77 insertions(+), 0 deletions(-) -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html ~Sathya -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 09/17] spi/spi.h: Add mem variable in spi master.
On Tuesday 26 November 2013 06:50 PM, Mark Brown wrote: On Tue, Nov 26, 2013 at 06:35:35PM +0530, Sourav Poddar wrote: On Tuesday 26 November 2013 06:31 PM, Mark Brown wrote: Is this really generic enough to put here rather than in the driver data? The thought behind this was that if a master controller supports memory mapped operation and slave wants to use memcpy in his driver(bypassing spi ), then we should have a mean to communicate between the master and the slave. So, 'spi_master' seems to be the place for me for this data, which could be parsed in the slave side also. I would have expected that the address would be returned by the function that maps the buffer in rather than stored permanently in the master. Yes, it could be be done the above way. I will change. -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 06/17] spi/qspi: Add support to switc to memory mapped operation.
On Tuesday 26 November 2013 06:27 PM, Mark Brown wrote: On Tue, Nov 26, 2013 at 01:05:02PM +0530, Sourav Poddar wrote: +void enable_qspi_memory_mapped(struct ti_qspi *qspi) +void disable_qspi_memory_mapped(struct ti_qspi *qspi) These are driver internal functions so they should be static. It'd also be more normal to put the qspi_ at the start of the name though it's not too big a deal. Ok. will change. -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 03/17] spi/qspi: parse register by name.
On Tuesday 26 November 2013 05:54 PM, Mark Brown wrote: On Tue, Nov 26, 2013 at 04:47:49PM +0530, Sourav Poddar wrote: I have added reg-names property in dt bindings. (17/17) patch of this series has that info. Do device tree binding changes early on in the series rather than at the end, one of the things that gets reviewed for is binding updates. Your code should also cope with the existing bindings, falling back on the current behaviour if it can't get the names or the extra resources. My current code only has a single resouce, hence *_byname* variants was not used. With extra resources, I am switching to byname variants, So, if a particular resource name is not found, it should just bypass that, thinking the resource is not required and should not resort to existing bindings.. -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 02/17] spi/spi.h: Add configure from slave support.
On Tuesday 26 November 2013 05:51 PM, Mark Brown wrote: On Tue, Nov 26, 2013 at 04:51:53PM +0530, Sourav Poddar wrote: On Tuesday 26 November 2013 03:59 PM, Mark Brown wrote: + void(*configure_from_slave)(struct spi_device *spi, u8 *val); Clearly this is far too unstructured to be useful, this is only ever going to work with one specific combination of slave and master since there's absolutely no semantics defined. I thought val might be good enuf, and this can be filled with whatever data that need to be used from slave into master(irrespective of slave and master?). The name isn't the issue, it's the fact that you're passing a completely unspecified blob of data. May be, what you are suggesting here is to we should define a flash information structure and should pass that structure here ? -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 12/17] spi/qspi: convert driver to enable/disable memory mapped.
Hi Mark, On Tuesday 26 November 2013 06:41 PM, Mark Brown wrote: On Tue, Nov 26, 2013 at 01:05:08PM +0530, Sourav Poddar wrote: Idea is to enable memory mapped by default at the end of the probe, if the control reaches the transfer api, then the operation is not a memory mapped one. Hence, we switch to Normal mode and at the end of the transfer function. switch back to memory mapped mode. This doesn't see safe, what happens if something tries to use the map while a transfer is in progress? Transfer gets initiated with the following api ti_qspi_start_transfer_one. At the beginning of this api, I am doing a disable memory mapped, as becuase of the code implemntation, if the control has reaches this api, memory mapped is not the desired operation. Then, at the end of this api after spi_finalize_current_message(master), which indicated the current transfer complete, I issue a end of transfer command. Only after which, I enable memory mapped mode again. So, will the condition you mention above will hit.? Please help me understand if i am missing something? -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 03/17] spi/qspi: parse register by name.
On Tuesday 26 November 2013 04:00 PM, Mark Brown wrote: On Tue, Nov 26, 2013 at 01:04:59PM +0530, Sourav Poddar wrote: Modify the qspi driver to parse reg information by name. This presumably needs an update to the device tree bindings so that there's a name defined? I have added reg-names property in dt bindings. (17/17) patch of this series has that info. -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 04/17] spi/qspi: parse control module register.
On Tuesday 26 November 2013 04:01 PM, Mark Brown wrote: On Tue, Nov 26, 2013 at 01:05:00PM +0530, Sourav Poddar wrote: In qspi controller, we need to switch to memory mapped operations. These switching depends on This will need to be added to the DT binding. I have added a reg-name property. Does we need to add individual reg-names also? -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 02/17] spi/spi.h: Add configure from slave support.
On Tuesday 26 November 2013 03:59 PM, Mark Brown wrote: On Tue, Nov 26, 2013 at 01:04:58PM +0530, Sourav Poddar wrote: void(*get_buf)(struct spi_master *master); void(*put_buf)(struct spi_master *master); + void(*configure_from_slave)(struct spi_device *spi, u8 *val); Clearly this is far too unstructured to be useful, this is only ever going to work with one specific combination of slave and master since there's absolutely no semantics defined. I thought val might be good enuf, and this can be filled with whatever data that need to be used from slave into master(irrespective of slave and master?). -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 04/17] spi/qspi: parse control module register.
On Tuesday 26 November 2013 05:55 PM, Mark Brown wrote: On Tue, Nov 26, 2013 at 04:48:58PM +0530, Sourav Poddar wrote: On Tuesday 26 November 2013 04:01 PM, Mark Brown wrote: On Tue, Nov 26, 2013 at 01:05:00PM +0530, Sourav Poddar wrote: In qspi controller, we need to switch to memory mapped operations. These switching depends on This will need to be added to the DT binding. I have added a reg-name property. Does we need to add individual reg-names also? I don't understand what you mean by individual reg-names? I have added a binding named reg-names in my documentation patch. -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 04/17] spi/qspi: parse control module register.
On Tuesday 26 November 2013 06:25 PM, Mark Brown wrote: On Tue, Nov 26, 2013 at 06:08:34PM +0530, Sourav Poddar wrote: On Tuesday 26 November 2013 05:55 PM, Mark Brown wrote: On Tue, Nov 26, 2013 at 04:48:58PM +0530, Sourav Poddar wrote: I have added a reg-name property. Does we need to add individual reg-names also? I don't understand what you mean by individual reg-names? I have added a binding named reg-names in my documentation patch. OK, but I stil don't understand the above? I mean to say, do I need to document qspi_base, qspi_ctrlmod register names also which I have used in omy dts files. -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 09/17] spi/spi.h: Add mem variable in spi master.
On Tuesday 26 November 2013 06:31 PM, Mark Brown wrote: On Tue, Nov 26, 2013 at 01:05:05PM +0530, Sourav Poddar wrote: Add mem variable in spi_master, which can be used to hold on the memory mapped address. Is this really generic enough to put here rather than in the driver data? The thought behind this was that if a master controller supports memory mapped operation and slave wants to use memcpy in his driver(bypassing spi ), then we should have a mean to communicate between the master and the slave. So, 'spi_master' seems to be the place for me for this data, which could be parsed in the slave side also. -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 11/17] spi/qspi: set mmap flag to true.
On Tuesday 26 November 2013 06:40 PM, Mark Brown wrote: On Tue, Nov 26, 2013 at 01:05:07PM +0530, Sourav Poddar wrote: Set mmap flag to true to indicate that the qspi controller supports memory mapped operations. Please combine some of these patches - adding the mmap support and then separately adding this flag isn't really helping bisection, just have one patch enabling support for mmap in the driver. Similarly adding internal functions to the driver with no users and then separately adding the users isn't really adding much. Sure, I will do that in my next version. -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 04/17] spi/qspi: parse control module register.
On Tuesday 26 November 2013 06:49 PM, Mark Brown wrote: On Tue, Nov 26, 2013 at 06:30:15PM +0530, Sourav Poddar wrote: I mean to say, do I need to document qspi_base, qspi_ctrlmod register names also which I have used in omy dts files. Yes, you need to document what the valid names are and what they mean. Ok, will do that. Thanks -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 3/5] pinctrl: am43xx: dt-bindings: add MUX_MODE8
From: Darren Etheridge detheri...@ti.com AM43xx devices have an extra MUX_MODE for certain pins. Updating dt include to have MUX_MODE8 which maps to 0x8. Signed-off-by: Darren Etheridge detheri...@ti.com Signed-off-by: Sourav Poddar sourav.pod...@ti.com --- include/dt-bindings/pinctrl/am43xx.h |1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/include/dt-bindings/pinctrl/am43xx.h b/include/dt-bindings/pinctrl/am43xx.h index eb6c366..9c2e4f8 100644 --- a/include/dt-bindings/pinctrl/am43xx.h +++ b/include/dt-bindings/pinctrl/am43xx.h @@ -13,6 +13,7 @@ #define MUX_MODE5 5 #define MUX_MODE6 6 #define MUX_MODE7 7 +#define MUX_MODE8 8 #define PULL_DISABLE (1 16) #define PULL_UP(1 17) -- 1.7.1 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/5] arm: dts: am4372: Add pwm-cells property for ecap device.
Add pwm-cells node for all ecap, ehrpwm in am43x dtsi files.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
arch/arm/boot/dts/am4372.dtsi |9 +
1 files changed, 9 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index 6ccf5c2..ea55a4e 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -495,6 +495,7 @@
ecap0: ecap@48300100 {
compatible = ti,am4372-ecap,ti,am33xx-ecap;
+ #pwm-cells = 3;
reg = 0x48300100 0x80;
ti,hwmods = ecap0;
status = disabled;
@@ -502,6 +503,7 @@
ehrpwm0: ehrpwm@48300200 {
compatible =
ti,am4372-ehrpwm,ti,am33xx-ehrpwm;
+ #pwm-cells = 3;
reg = 0x48300200 0x80;
ti,hwmods = ehrpwm0;
status = disabled;
@@ -519,6 +521,7 @@
ecap1: ecap@48302100 {
compatible = ti,am4372-ecap,ti,am33xx-ecap;
+ #pwm-cells = 3;
reg = 0x48302100 0x80;
ti,hwmods = ecap1;
status = disabled;
@@ -526,6 +529,7 @@
ehrpwm1: ehrpwm@48302200 {
compatible =
ti,am4372-ehrpwm,ti,am33xx-ehrpwm;
+ #pwm-cells = 3;
reg = 0x48302200 0x80;
ti,hwmods = ehrpwm1;
status = disabled;
@@ -543,6 +547,7 @@
ecap2: ecap@48304100 {
compatible = ti,am4372-ecap,ti,am33xx-ecap;
+ #pwm-cells = 3;
reg = 0x48304100 0x80;
ti,hwmods = ecap2;
status = disabled;
@@ -550,6 +555,7 @@
ehrpwm2: ehrpwm@48304200 {
compatible =
ti,am4372-ehrpwm,ti,am33xx-ehrpwm;
+ #pwm-cells = 3;
reg = 0x48304200 0x80;
ti,hwmods = ehrpwm2;
status = disabled;
@@ -567,6 +573,7 @@
ehrpwm3: ehrpwm@48306200 {
compatible =
ti,am4372-ehrpwm,ti,am33xx-ehrpwm;
+ #pwm-cells = 3;
reg = 0x48306200 0x80;
ti,hwmods = ehrpwm3;
status = disabled;
@@ -584,6 +591,7 @@
ehrpwm4: ehrpwm@48308200 {
compatible =
ti,am4372-ehrpwm,ti,am33xx-ehrpwm;
+ #pwm-cells = 3;
reg = 0x48308200 0x80;
ti,hwmods = ehrpwm4;
status = disabled;
@@ -601,6 +609,7 @@
ehrpwm5: ehrpwm@4830a200 {
compatible =
ti,am4372-ehrpwm,ti,am33xx-ehrpwm;
+ #pwm-cells = 3;
reg = 0x4830a200 0x80;
ti,hwmods = ehrpwm5;
status = disabled;
--
1.7.1
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[PATCH 0/5] Add more device nodes for am43x-epos-evm
The patch series adds support for enabling pwm backlight, i2c2, spi and matrix gpio keys on am43x-gp-evm. Done on top of 3.13-rc1 + tero clock series(1) [1]: https://patchwork.kernel.org/patch/3009541/ Tested on am43x-gp-evm. There is a some bug while using regulators through backlight driver on 3.13-rc1. So, tested pwm part with this temporary patch[2]. [2]: http://www.spinics.net/lists/arm-kernel/msg288215.html Darren Etheridge (1): pinctrl: am43xx: dt-bindings: add MUX_MODE8 Sourav Poddar (4): arm: dts: am4372: Add pwm-cellsproperty for ecap device. arm: dts: am43x-epos-evm: Add I2C data. arm: dts: am43x-epos-evm: Add SPI data. ARM: dts: am43x-epos-evm: Add pwm backlight support. arch/arm/boot/dts/am4372.dtsi|9 + arch/arm/boot/dts/am43x-epos-evm.dts | 67 ++ include/dt-bindings/pinctrl/am43xx.h |1 + 3 files changed, 77 insertions(+), 0 deletions(-) -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 2/5] ARM: dts: am43x-epos-evm: Add pwm backlight support.
From: Sourav Poddar Date: Sat, 5 Oct 2013 05:19:46 +0530 sourav.pod...@ti.com
Add pwm backlight support for am43x epos evm.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
arch/arm/boot/dts/am43x-epos-evm.dts | 24
1 files changed, 24 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts
b/arch/arm/boot/dts/am43x-epos-evm.dts
index a037a92..5521999 100644
--- a/arch/arm/boot/dts/am43x-epos-evm.dts
+++ b/arch/arm/boot/dts/am43x-epos-evm.dts
@@ -13,6 +13,7 @@
#include am4372.dtsi
#include dt-bindings/pinctrl/am43xx.h
#include dt-bindings/gpio/gpio.h
+#include dt-bindings/pwm/pwm.h
/ {
model = TI AM43x EPOS EVM;
@@ -90,6 +91,12 @@
0x9c (PIN_INPUT_PULLUP | MUX_MODE3)
;
};
+
+ ecap0_pins: backlight_pins {
+ pinctrl-single,pins =
+ 0x164 MUX_MODE0 /*
eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
+ ;
+ };
};
matrix_keypad: matrix_keypad@0 {
@@ -124,6 +131,13 @@
0x0203006c /* DOWN */
0x03030069;/* LEFT */
};
+
+ backlight {
+ compatible = pwm-backlight;
+ pwms = ecap0 0 5 PWM_POLARITY_INVERTED;
+ brightness-levels = 0 51 53 56 62 75 101 152 255;
+ default-brightness-level = 8;
+ };
};
mmc1 {
@@ -212,3 +226,13 @@
spi-rx-bus-width = 4;
};
};
+
+epwmss0 {
+ status = okay;
+};
+
+ecap0 {
+ status = okay;
+ pinctrl-names = default;
+ pinctrl-0 = ecap0_pins;
+};
--
1.7.1
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[PATCH 0/3] Add more device nodes for am43x gp evm.
The patch series adds support for enabling gpio, pwm backlight and matrix gpio keys on am43x-gp-evm. Done on top of 3.13-rc1 + tero clock series(1) + Afzal's basic gp support(2). [1]: https://patchwork.kernel.org/patch/3009541/ [2]: https://patchwork.kernel.org/patch/3171761/ Tested on am43x-gp-evm. There is a some bug while using regulators through backlight driver on 3.13-rc1. So, tested pwm part with this patch[3]. [3]: http://www.spinics.net/lists/arm-kernel/msg288215.html Sourav Poddar (3): arm: dts: am437x-gp-evm: Enable gpio. ARM: dts: am43x-gp-evm: Add matrix gpio keys. ARM: dts: am437x-gp-evm: Add pwm backlight support. arch/arm/boot/dts/am437x-gp-evm.dts | 53 +++ 1 files changed, 53 insertions(+), 0 deletions(-) -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 4/5] arm: dts: am43x-epos-evm: Add I2C2 data.
Add I2C2 dts data.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
arch/arm/boot/dts/am43x-epos-evm.dts | 13 +
1 files changed, 13 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts
b/arch/arm/boot/dts/am43x-epos-evm.dts
index 5521999..7a504d1 100644
--- a/arch/arm/boot/dts/am43x-epos-evm.dts
+++ b/arch/arm/boot/dts/am43x-epos-evm.dts
@@ -97,6 +97,13 @@
0x164 MUX_MODE0 /*
eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
;
};
+
+ i2c2_pins: pinmux_i2c2_pins {
+ pinctrl-single,pins =
+ 0x1c0 (PIN_INPUT_PULLUP | SLEWCTRL_FAST |
MUX_MODE8)/* i2c2_sda.i2c2_sda */
+ 0x1c4 (PIN_INPUT_PULLUP | SLEWCTRL_FAST |
MUX_MODE8)/* i2c2_scl.i2c2_scl */
+ ;
+ };
};
matrix_keypad: matrix_keypad@0 {
@@ -194,6 +201,12 @@
};
};
+i2c2 {
+ pinctrl-names = default;
+ pinctrl-0 = i2c2_pins;
+ status = okay;
+};
+
gpio0 {
status = okay;
};
--
1.7.1
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[PATCH 5/5] arm: dts: am43x-epos-evm: Add SPI data.
Add SPI dts data.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
arch/arm/boot/dts/am43x-epos-evm.dts | 30 ++
1 files changed, 30 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts
b/arch/arm/boot/dts/am43x-epos-evm.dts
index 7a504d1..2ebcde6 100644
--- a/arch/arm/boot/dts/am43x-epos-evm.dts
+++ b/arch/arm/boot/dts/am43x-epos-evm.dts
@@ -104,6 +104,24 @@
0x1c4 (PIN_INPUT_PULLUP | SLEWCTRL_FAST |
MUX_MODE8)/* i2c2_scl.i2c2_scl */
;
};
+
+ spi0_pins: pinmux_spi0_pins {
+ pinctrl-single,pins =
+ 0x150 (PIN_INPUT | MUX_MODE0) /*
spi0_clk.spi0_clk */
+ 0x154 (PIN_OUTPUT | MUX_MODE0) /*
spi0_d0.spi0_d0 */
+ 0x158 (PIN_INPUT | MUX_MODE0) /*
spi0_d1.spi0_d1 */
+ 0x15c (PIN_OUTPUT | MUX_MODE0) /*
spi0_cs0.spi0_cs0 */
+ ;
+ };
+
+ spi1_pins: pinmux_spi1_pins {
+ pinctrl-single,pins =
+ 0x190 (PIN_INPUT | MUX_MODE3) /*
mcasp0_aclkx.spi1_clk */
+ 0x194 (PIN_OUTPUT | MUX_MODE3) /*
mcasp0_fsx.spi1_d0 */
+ 0x198 (PIN_INPUT | MUX_MODE3) /*
mcasp0_axr0.spi1_d1 */
+ 0x19c (PIN_OUTPUT | MUX_MODE3) /*
mcasp0_ahclkr.spi1_cs0 */
+ ;
+ };
};
matrix_keypad: matrix_keypad@0 {
@@ -249,3 +267,15 @@
pinctrl-names = default;
pinctrl-0 = ecap0_pins;
};
+
+spi0 {
+ pinctrl-names = default;
+ pinctrl-0 = spi0_pins;
+ status = okay;
+};
+
+spi1 {
+ pinctrl-names = default;
+ pinctrl-0 = spi1_pins;
+ status = okay;
+};
--
1.7.1
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[PATCH 3/3] arm: dts: am43x-gp-evm: Add matrix gpio keys.
Add gpio keys node for am43x gp evm.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
arch/arm/boot/dts/am437x-gp-evm.dts | 21 +
1 files changed, 21 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts
b/arch/arm/boot/dts/am437x-gp-evm.dts
index 312a51c..9ef6b5a 100644
--- a/arch/arm/boot/dts/am437x-gp-evm.dts
+++ b/arch/arm/boot/dts/am437x-gp-evm.dts
@@ -13,6 +13,7 @@
#include am4372.dtsi
#include dt-bindings/pinctrl/am43xx.h
#include dt-bindings/pwm/pwm.h
+#include dt-bindings/gpio/gpio.h
/ {
model = TI AM437x GP EVM;
@@ -24,6 +25,26 @@
brightness-levels = 0 51 53 56 62 75 101 152 255;
default-brightness-level = 8;
};
+
+ matrix_keypad: matrix_keypad@0 {
+ compatible = gpio-matrix-keypad;
+ debounce-delay-ms = 5;
+ col-scan-delay-us = 2;
+
+ row-gpios = gpio3 21 GPIO_ACTIVE_HIGH /* Bank3, pin21 */
+ gpio4 3 GPIO_ACTIVE_HIGH /* Bank4, pin3 */
+ gpio4 2 GPIO_ACTIVE_HIGH; /* Bank4, pin2 */
+
+ col-gpios = gpio3 19 GPIO_ACTIVE_HIGH /* Bank3, pin19 */
+ gpio3 20 GPIO_ACTIVE_HIGH; /* Bank3, pin20 */
+
+ linux,keymap = 0x0201 /* P1 */
+ 0x00010202 /* P2 */
+ 0x0167 /* UP */
+ 0x0101006a /* RIGHT */
+ 0x0269 /* LEFT */
+ 0x0201006c; /* DOWN */
+ };
};
am43xx_pinmux {
--
1.7.1
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[PATCH 1/3] arm: dts: am437x-gp-evm: Add pwm backlight support.
Add pwm backlight support for gp evm.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
arch/arm/boot/dts/am437x-gp-evm.dts | 24
1 files changed, 24 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts
b/arch/arm/boot/dts/am437x-gp-evm.dts
index 11d93ba..2e79bda 100644
--- a/arch/arm/boot/dts/am437x-gp-evm.dts
+++ b/arch/arm/boot/dts/am437x-gp-evm.dts
@@ -12,10 +12,18 @@
#include am4372.dtsi
#include dt-bindings/pinctrl/am43xx.h
+#include dt-bindings/pwm/pwm.h
/ {
model = TI AM437x GP EVM;
compatible = ti,am437x-gp-evm,ti,am4372,ti,am43;
+
+ backlight {
+ compatible = pwm-backlight;
+ pwms = ecap0 0 5 PWM_POLARITY_INVERTED;
+ brightness-levels = 0 51 53 56 62 75 101 152 255;
+ default-brightness-level = 8;
+ };
};
am43xx_pinmux {
@@ -32,6 +40,12 @@
0x158 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2)
/* spi0_d1.i2c1_sda */
;
};
+
+ ecap0_pins: backlight_pins {
+ pinctrl-single,pins =
+ 0x164 MUX_MODE0 /*
eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
+ ;
+ };
};
i2c0 {
@@ -45,3 +59,13 @@
pinctrl-names = default;
pinctrl-0 = i2c1_pins;
};
+
+epwmss0 {
+ status = okay;
+};
+
+ecap0 {
+ status = okay;
+ pinctrl-names = default;
+ pinctrl-0 = ecap0_pins;
+};
--
1.7.1
--
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[PATCH 2/3] arm: dts: am437x-gp-evm: Enable gpio.
Enable gpio3, gpio4, it will be used by gpio matrix keys. Also,
can be used by othe peripherals.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
arch/arm/boot/dts/am437x-gp-evm.dts |8
1 files changed, 8 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts
b/arch/arm/boot/dts/am437x-gp-evm.dts
index a581f7d..312a51c 100644
--- a/arch/arm/boot/dts/am437x-gp-evm.dts
+++ b/arch/arm/boot/dts/am437x-gp-evm.dts
@@ -69,3 +69,11 @@
pinctrl-0 = ecap0_pins;
};
};
+
+gpio3 {
+ status = okay;
+};
+
+gpio4 {
+ status = okay;
+};
--
1.7.1
--
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