2015-01-06 5:25 GMT+09:00 Arnd Bergmann a...@arndb.de:
On Monday 05 January 2015 13:19:00 Marek Szyprowski wrote:
DT_MACHINE_START(OMAP4_DT, Generic OMAP4 (Flattened Device Tree))
+ .l2c_aux_val= OMAP_L2C_AUX_CTRL,
+ .l2c_aux_mask = 0xcf9f,
+ .l2c_write_sec =
2015-01-04 0:34 GMT+09:00 Nishanth Menon n...@ti.com:
On 15:40-20150103, Tomasz Figa wrote:
Hi Nishanth,
2015-01-03 2:43 GMT+09:00 Nishanth Menon n...@ti.com:
AM437x generation of processors support programming the PL310 L2Cache
controller's address filter start and end registers using
2015-01-04 1:45 GMT+09:00 Nishanth Menon n...@ti.com:
On 01/03/2015 10:16 AM, Tomasz Figa wrote:
2015-01-04 0:34 GMT+09:00 Nishanth Menon n...@ti.com:
On 15:40-20150103, Tomasz Figa wrote:
Hi Nishanth,
2015-01-03 2:43 GMT+09:00 Nishanth Menon n...@ti.com:
AM437x generation of processors
On 30.12.2014 03:23, Nishanth Menon wrote:
On 12/23/2014 04:48 AM, Marek Szyprowski wrote:
-static void l2c310_resume(void)
+static void l2c310_configure(void __iomem *base)
{
- void __iomem *base = l2x0_base;
+ unsigned revision;
- if (!(readl_relaxed(base + L2X0_CTRL)
On 30.12.2014 23:51, Nishanth Menon wrote:
Looks like the following also need addressing:
data-save is called twice (once more after l2cof_init)
l2c310_init_fns also needs l2c310_configure
will be nice to use l2x0_data only after we kmemdup data in __l2c_init
I'll check this.
Thanks.
On 02.01.2015 18:13, Tomasz Figa wrote:
On 30.12.2014 23:51, Nishanth Menon wrote:
Looks like the following also need addressing:
data-save is called twice (once more after l2cof_init)
l2c310_init_fns also needs l2c310_configure
will be nice to use l2x0_data only after we kmemdup data
Hi Tony,
2015-01-03 9:23 GMT+09:00 Tony Lindgren t...@atomide.com:
* Nishanth Menon n...@ti.com [150102 11:50]:
On 01/02/2015 12:46 PM, santosh.shilim...@oracle.com wrote:
On 1/2/15 9:43 AM, Nishanth Menon wrote:
Hi,
OMAP4 and AM437x ROM code provides services to program PL310's latency
Hi Nishanth,
2015-01-03 2:43 GMT+09:00 Nishanth Menon n...@ti.com:
AM437x generation of processors support programming the PL310 L2Cache
controller's address filter start and end registers using a secure
montior service.
typo: s/montior/monitor/
[snip]
+ base =
Thanks a lot for investigating this, even before I could look into
splitting this.
2014-12-30 3:23 GMT+09:00 Nishanth Menon n...@ti.com:
On 12/23/2014 04:48 AM, Marek Szyprowski wrote:
-static void l2c310_resume(void)
+static void l2c310_configure(void __iomem *base)
{
- void __iomem
Nishanth, Tony,
On 24.12.2014 02:13, Nishanth Menon wrote:
On 12/23/2014 11:06 AM, Tony Lindgren wrote:
* Marek Szyprowski m.szyprow...@samsung.com [141223 02:51]:
From: Tomasz Figa t.f...@samsung.com
Certain implementations of secure hypervisors (namely the one found on
Samsung Exynos-based
2014-12-06 1:23 GMT+09:00 Russell King - ARM Linux li...@arm.linux.org.uk:
On Fri, Dec 05, 2014 at 10:13:51AM -0600, Nishanth Menon wrote:
On 12/05/2014 10:10 AM, Nishanth Menon wrote:
Case #2: Reverting the following allows boot.
From next-20141204
10df7d5 ARM: 8211/1: l2c: Add support
Hi Anton,
On 13.10.2014 06:54, Anton Tikhomirov wrote:
Hi Vivek,
Exynos7 also has a separate special gate clock going to the IP
apart from the usual AHB clock. So add support for the same.
As we discussed before, Exynos7 SoCs have 7 clocks to be controlled
by the driver. Adding only sclk
On 24.09.2014 13:14, Mark Rutland wrote:
On Wed, Sep 24, 2014 at 12:05:38PM +0100, Marek Szyprowski wrote:
From: Tomasz Figa t.f...@samsung.com
Firmware on certain boards (e.g. ODROID-U3) can leave incorrect L2C prefetch
settings configured in registers leading to crashes if L2C is enabled
+static void exynos_l2_write_sec(unsigned long val, unsigned reg)
+{
+switch (reg) {
+case L2X0_CTRL:
+if (val L2X0_CTRL_EN)
+exynos_smc(SMC_CMD_L2X0INVALL, 0, 0, 0);
If we're calling this with the cache already enabled, presumably you're
doing
On 15.09.2014 11:03, Russell King - ARM Linux wrote:
diff --git a/arch/arm/mach-exynos/firmware.c
b/arch/arm/mach-exynos/firmware.c
index 554b350..71bcfbd 100644
--- a/arch/arm/mach-exynos/firmware.c
+++ b/arch/arm/mach-exynos/firmware.c
@@ -102,7 +102,9 @@ static int exynos_suspend(void)
Russell, Olof, Kukjin,
On 26.08.2014 16:17, Tomasz Figa wrote:
This series intends to add support for L2 cache on Exynos4 SoCs on boards
running under secure firmware, which requires certain initialization steps
to be done with help of firmware, as selected registers are writable only
from
| 56
++---
For drivers/clk/samsung/*
Acked-by: Tomasz Figa tomasz.f...@gmail.com
Best regards,
Tomasz
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earlier. This patch fixes this by making the assignment
conditional, depending on whether current .write_sec callback is NULL.
Signed-off-by: Tomasz Figa t.f...@samsung.com
---
arch/arm/kernel/irq.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/kernel/irq.c b/arch
to firmware to invalidate whole L2 cache before setting enable
bit in L2C control register (required by Exynos secure firmware).
Tomasz Figa (7):
ARM: l2c: Refactor the driver to use commit-like interface
ARM: l2c: Add interface to ask hypervisor to configure L2C
ARM: l2c: Get outer cache
On Exynos SoCs it is necessary to resume operation of L2C early in
assembly code, because otherwise certain systems will crash. This patch
adds necessary code to non-secure resume handler.
Signed-off-by: Tomasz Figa t.f...@samsung.com
---
arch/arm/mach-exynos/common.h | 1 +
arch/arm/mach
-by: Tomasz Figa t.f...@samsung.com
---
arch/arm/mm/cache-l2x0.c | 210 ++-
1 file changed, 115 insertions(+), 95 deletions(-)
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 5f2c988..b073563 100644
--- a/arch/arm/mm/cache-l2x0.c
This patch adds device tree nodes for L2 cache controller present on
Exynos4 SoCs.
Signed-off-by: Tomasz Figa t.f...@samsung.com
---
arch/arm/boot/dts/exynos4210.dtsi | 9 +
arch/arm/boot/dts/exynos4x12.dtsi | 14 ++
2 files changed, 23 insertions(+)
diff --git a/arch/arm
and .configure callbacks is provided by this patch.
Signed-off-by: Tomasz Figa t.f...@samsung.com
---
arch/arm/mach-exynos/firmware.c | 38 ++
1 file changed, 38 insertions(+)
diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c
index f5e626d
.
Signed-off-by: Tomasz Figa t.f...@samsung.com
---
Documentation/devicetree/bindings/arm/l2cc.txt | 10 +++
arch/arm/mm/cache-l2x0.c | 39 ++
2 files changed, 49 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/l2cc.txt
b/Documentation
parameters. This patch adds such.
Signed-off-by: Tomasz Figa t.f...@samsung.com
---
arch/arm/include/asm/outercache.h | 3 +++
arch/arm/mm/cache-l2x0.c | 6 ++
2 files changed, 9 insertions(+)
diff --git a/arch/arm/include/asm/outercache.h
b/arch/arm/include/asm/outercache.h
index
On 03.08.2014 00:09, Russell King - ARM Linux wrote:
On Thu, Jul 17, 2014 at 06:38:56PM +0200, Tomasz Figa wrote:
Certain implementations of secure hypervisors (namely the one found on
Samsung Exynos-based boards) do not provide access to individual L2C
registers. This makes the .write_sec
On 17.07.2014 18:38, Tomasz Figa wrote:
This series intends to add support for L2 cache on Exynos4 SoCs on boards
running under secure firmware, which requires certain initialization steps
to be done with help of firmware, as selected registers are writable only
from secure mode.
First four
-l2x0.c,
- added support of overriding of prefetch settings to work around incorrect
default settings on certain Exynos4x12-based boards,
- added call to firmware to invalidate whole L2 cache before setting enable
bit in L2C control register (required by Exynos secure firmware).
Tomasz Figa (7
On Exynos SoCs it is necessary to resume operation of L2C early in
assembly code, because otherwise certain systems will crash. This patch
adds necessary code to non-secure resume handler.
Signed-off-by: Tomasz Figa t.f...@samsung.com
---
arch/arm/mach-exynos/common.h | 1 +
arch/arm/mach
This patch adds device tree nodes for L2 cache controller present on
Exynos4 SoCs.
Signed-off-by: Tomasz Figa t.f...@samsung.com
---
arch/arm/boot/dts/exynos4210.dtsi | 9 +
arch/arm/boot/dts/exynos4x12.dtsi | 14 ++
2 files changed, 23 insertions(+)
diff --git a/arch/arm
-by: Tomasz Figa t.f...@samsung.com
---
arch/arm/mm/cache-l2x0.c | 201 ++-
1 file changed, 110 insertions(+), 91 deletions(-)
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 5f2c988..385c047 100644
--- a/arch/arm/mm/cache-l2x0.c
.
Signed-off-by: Tomasz Figa t.f...@samsung.com
---
Documentation/devicetree/bindings/arm/l2cc.txt | 10 +++
arch/arm/mm/cache-l2x0.c | 39 ++
2 files changed, 49 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/l2cc.txt
b/Documentation
and .configure callbacks is provided by this patch.
Signed-off-by: Tomasz Figa t.f...@samsung.com
---
arch/arm/mach-exynos/firmware.c | 38 ++
1 file changed, 38 insertions(+)
diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c
index f5e626d
parameters. This patch adds such.
Signed-off-by: Tomasz Figa t.f...@samsung.com
---
arch/arm/include/asm/outercache.h | 3 +++
arch/arm/mm/cache-l2x0.c | 5 +
2 files changed, 8 insertions(+)
diff --git a/arch/arm/include/asm/outercache.h
b/arch/arm/include/asm/outercache.h
index
earlier. This patch fixes this by making the assignment
conditional, depending on whether current .write_sec callback is NULL.
Signed-off-by: Tomasz Figa t.f...@samsung.com
---
arch/arm/kernel/irq.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/kernel/irq.c b/arch
...@arm.linux.org.uk
Build- and boot-tested on mach-s3c64xx.
Tested-by: Tomasz Figa tomasz.f...@gmail.com
Best regards,
Tomasz
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bit in L2C control register (required by Exynos secure firmware).
Tomasz Figa (6):
ARM: mm: cache-l2x0: Add base address argument to write_sec callback
ARM: Get outer cache .write_sec callback from mach_desc only if not
NULL
ARM: mm: cache-l2x0: Use l2c_write_sec() for LATENCY_CTRL
Signed-off-by: Tomasz Figa t.f...@samsung.com
---
Documentation/devicetree/bindings/arm/l2cc.txt | 10 ++
arch/arm/mm/cache-l2x0.c | 46 ++
2 files changed, 56 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/l2cc.txt
b
According to the documentation, TAG_LATENCY_CTRL and DATA_LATENCY_CTRL
registers of L2C-310 can be written only in secure mode, so
l2c_write_sec() should be used to change them, instead of plain
writel_relaxed().
Signed-off-by: Tomasz Figa t.f...@samsung.com
---
arch/arm/mm/cache-l2x0.c | 16
This patch adds device tree nodes for L2 cache controller present on
Exynos4 SoCs.
Signed-off-by: Tomasz Figa t.f...@samsung.com
---
arch/arm/boot/dts/exynos4210.dtsi | 9 +
arch/arm/boot/dts/exynos4x12.dtsi | 14 ++
2 files changed, 23 insertions(+)
diff --git a/arch/arm
so that its implementation can also access registers
directly.
Signed-off-by: Tomasz Figa t.f...@samsung.com
---
arch/arm/include/asm/mach/arch.h | 3 ++-
arch/arm/include/asm/outercache.h | 2 +-
arch/arm/mach-highbank/highbank.c | 3 ++-
arch/arm/mach-omap2/omap4-common.c | 3 ++-
arch/arm
is provided by this patch.
Signed-off-by: Tomasz Figa t.f...@samsung.com
---
arch/arm/mach-exynos/firmware.c | 63 +
1 file changed, 63 insertions(+)
diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c
index eb91d23..def7bb4
earlier. This patch fixes this by making the assignment
conditional, depending on whether current .write_sec callback is NULL.
Signed-off-by: Tomasz Figa t.f...@samsung.com
---
arch/arm/kernel/irq.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/kernel/irq.c b/arch
On 25.06.2014 15:50, Russell King - ARM Linux wrote:
On Wed, Jun 25, 2014 at 03:37:25PM +0200, Tomasz Figa wrote:
This series intends to add support for L2 cache on Exynos4 SoCs on boards
running under secure firmware, which requires certain initialization steps
to be done with help
On 25.06.2014 16:37, Russell King - ARM Linux wrote:
On Wed, Jun 25, 2014 at 04:13:16PM +0200, Tomasz Figa wrote:
On 25.06.2014 15:50, Russell King - ARM Linux wrote:
On Wed, Jun 25, 2014 at 03:37:25PM +0200, Tomasz Figa wrote:
This series intends to add support for L2 cache on Exynos4 SoCs
tested
your patches against a kernel with all of Russell King's recent
changes?
Thanks
Daniel
From b574212db2c1c226212c74b475acceb7fa507c27 Mon Sep 17 00:00:00 2001
From: Tomasz Figa t.f...@samsung.com
Date: Fri, 13 Jun 2014 16:40:29 +0200
Subject: [PATCH 1/3] ARM: EXYNOS: Invalidate L2
Hi Daniel,
On 12.06.2014 15:38, Daniel Drake wrote:
Hi Tomasz,
Thanks for working on this!
I have just tried this, against Linus master
64b2d1fbbfda07765dae3f601862796a61b2c451.
Added patch ARM: dts: Initial ODROID U2 support and booted on
ODROID-U2. I believe this board has the
Hi Russell,
On 12.06.2014 18:20, Russell King - ARM Linux wrote:
On Thu, Jun 12, 2014 at 02:38:49PM +0100, Daniel Drake wrote:
From 2e67231f10ed0b05c2bacfdd05774fe21315d6da Mon Sep 17 00:00:00 2001
From: Gu1 g...@aeroxteam.fr
Date: Mon, 21 Jan 2013 04:13:56 +0100
Subject: [PATCH] ARM:
interested people for testing.
Further two patches add impelmentation of .write_sec for Exynos secure
firmware and necessary DT nodes to enable L2 cache.
Tested on Exynos4210-based Universal C210 board (without secure firmware)
and Exynos4412-based TRATS2 board (with secure firmware).
Tomasz Figa (5
so that its implementation can also access registers
directly.
Signed-off-by: Tomasz Figa t.f...@samsung.com
---
arch/arm/include/asm/mach/arch.h | 3 ++-
arch/arm/include/asm/outercache.h | 2 +-
arch/arm/mach-highbank/highbank.c | 3 ++-
arch/arm/mach-omap2/omap4-common.c | 3 ++-
arch/arm
This patch adds device tree nodes for L2 cache controller present on
Exynos4 SoCs.
Signed-off-by: Tomasz Figa t.f...@samsung.com
---
arch/arm/boot/dts/exynos4210.dtsi | 9 +
arch/arm/boot/dts/exynos4x12.dtsi | 9 +
2 files changed, 18 insertions(+)
diff --git a/arch/arm/boot/dts
According to the documentation, TAG_LATENCY_CTRL and DATA_LATENCY_CTRL
registers of L2C-310 can be written only in secure mode, so
l2c_write_sec() should be used to change them, instead of plain
writel_relaxed().
Signed-off-by: Tomasz Figa t.f...@samsung.com
---
arch/arm/mm/cache-l2x0.c | 8
earlier. This patch fixes this by making the assignment
conditional, depending on whether current .write_sec callback is NULL.
Signed-off-by: Tomasz Figa t.f...@samsung.com
---
arch/arm/kernel/irq.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/kernel/irq.c b/arch
is provided by this patch.
Signed-off-by: Tomasz Figa t.f...@samsung.com
---
arch/arm/mach-exynos/firmware.c | 61 +
1 file changed, 61 insertions(+)
diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c
index eb91d23..34f7798
On 11.06.2014 18:00, Jon Loeliger wrote:
diff --git a/arch/arm/include/asm/mach/arch.h
b/arch/arm/include/asm/mach/arch.h
index 060a75e..ddaebcd 100644
--- a/arch/arm/include/asm/mach/arch.h
+++ b/arch/arm/include/asm/mach/arch.h
@@ -46,7 +46,8 @@ struct machine_desc {
enum
On 24.04.2014 15:11, Ulf Hansson wrote:
On 24 April 2014 12:13, Geert Uytterhoeven geert+rene...@glider.be wrote:
When adding a device from DT, check if its clocks are suitable for Runtime
PM, and register them with the PM core.
If Runtime PM is disabled, just enable the clock.
This allows
Hi Tero,
On Friday 25 of October 2013 18:56:55 Tero Kristo wrote:
Previously, only direct register read/write was supported. Now a
per-clock regmap can be provided for same purpose, which allows the
clock drivers to access clock registers behind e.g. I2C bus.
Signed-off-by: Tero Kristo
Hi Matt,
On Tuesday 29 of October 2013 12:50:43 Matt Sealey wrote:
On Fri, Oct 25, 2013 at 10:56 AM, Tero Kristo t-kri...@ti.com wrote:
Some devices require their clocks to be available with a specific
dev-id con-id mapping. With DT, the clocks can be found by default
only with their name,
On Monday 28 of October 2013 01:37:34 Kumar Gala wrote:
On Oct 27, 2013, at 11:14 AM, Sebastian Reichel wrote:
Add device tree support for the spi variant of wl1251
and document the binding.
Signed-off-by: Sebastian Reichel s...@debian.org
---
Hi Laurent,
On Tuesday 27 of August 2013 10:02:39 Laurent Pinchart wrote:
Add DT bindings for the pcf857x-compatible chips and parse the device
tree node in the driver.
Signed-off-by: Laurent Pinchart
laurent.pinchart+rene...@ideasonboard.com ---
On Tuesday 27 of August 2013 14:00:24 Archit Taneja wrote:
Hi,
On Tuesday 27 August 2013 01:44 PM, Tomasz Figa wrote:
Hi Laurent,
On Tuesday 27 of August 2013 10:02:39 Laurent Pinchart wrote:
Add DT bindings for the pcf857x-compatible chips and parse the device
tree node
On Tuesday 13 of August 2013 16:14:44 Kishon Vijay Abraham I wrote:
Hi,
On Wednesday 31 July 2013 11:45 AM, Felipe Balbi wrote:
Hi,
On Wed, Jul 31, 2013 at 11:14:32AM +0530, Kishon Vijay Abraham I wrote:
IMHO we need a lookup method for PHYs, just like for clocks,
regulators, PWMs
On Wednesday 14 of August 2013 00:19:28 Sylwester Nawrocki wrote:
W dniu 2013-08-13 14:05, Kishon Vijay Abraham I pisze:
On Tuesday 13 August 2013 05:07 PM, Tomasz Figa wrote:
On Tuesday 13 of August 2013 16:14:44 Kishon Vijay Abraham I wrote:
On Wednesday 31 July 2013 11:45 AM, Felipe
Hi Tero,
On Friday 02 of August 2013 19:25:20 Tero Kristo wrote:
clk_get_sys / clk_get can now find clocks from device-tree. If a DT
clock is found, an entry is added to the clk_lookup list also for
subsequent searches.
Signed-off-by: Tero Kristo t-kri...@ti.com
Cc: Russell King
On Friday 02 of August 2013 19:25:25 Tero Kristo wrote:
This patch creates a unique node for each clock in the OMAP4 power,
reset and clock manager (PRCM). OMAP443x and OMAP446x have slightly
different clock tree which is taken into account in the data.
Signed-off-by: Tero Kristo
Hi Russell,
On Saturday 03 of August 2013 19:35:43 Russell King - ARM Linux wrote:
On Sat, Aug 03, 2013 at 04:02:36PM +0200, Tomasz Figa wrote:
+ if (cl)
+ return cl;
+
+ /* If clock was not found, attempt to look-up from DT */
+ node = of_find_node_by_name(NULL, con_id
On Saturday 03 of August 2013 19:48:05 Russell King - ARM Linux wrote:
On Sat, Aug 03, 2013 at 08:39:34PM +0200, Tomasz Figa wrote:
Hi Russell,
On Saturday 03 of August 2013 19:35:43 Russell King - ARM Linux wrote:
On Sat, Aug 03, 2013 at 04:02:36PM +0200, Tomasz Figa wrote
Hi Alan,
On Monday 22 of July 2013 10:44:39 Alan Stern wrote:
On Mon, 22 Jul 2013, Kishon Vijay Abraham I wrote:
The PHY and the controller it is attached to are both physical
devices.
The connection between them is hardwired by the system
manufacturer and cannot be
[Fixed address of devicetree mailing list and added more people on CC.]
For reference, full thread can be found under following link:
http://thread.gmane.org/gmane.linux.ports.arm.kernel/252813
Best regards,
Tomasz
On Tuesday 23 of July 2013 09:29:32 Tomasz Figa wrote:
Hi Alan,
On Monday 22
On Tuesday 23 of July 2013 10:37:05 Alan Stern wrote:
On Tue, 23 Jul 2013, Tomasz Figa wrote:
On Tuesday 23 of July 2013 09:29:32 Tomasz Figa wrote:
Hi Alan,
Thanks for helping to clarify the issues here.
Okay. Are PHYs _always_ platform devices?
They can be i2c, spi or any
On Tuesday 23 of July 2013 09:18:46 Greg KH wrote:
On Tue, Jul 23, 2013 at 08:48:24PM +0530, Kishon Vijay Abraham I wrote:
Hi,
On Tuesday 23 July 2013 08:07 PM, Alan Stern wrote:
On Tue, 23 Jul 2013, Tomasz Figa wrote:
On Tuesday 23 of July 2013 09:29:32 Tomasz Figa wrote:
Hi Alan
On Tuesday 23 of July 2013 10:37:11 Greg KH wrote:
On Tue, Jul 23, 2013 at 06:50:29PM +0200, Tomasz Figa wrote:
Ick, no. Why can't you just pass the pointer to the phy itself? If
you
had a priv pointer to search from, then you could have just passed
the
original phy pointer
On Tuesday 23 of July 2013 12:44:23 Greg KH wrote:
On Tue, Jul 23, 2013 at 08:31:05PM +0100, Mark Brown wrote:
You don't know the id of the device you are looking up, due to
multiple devices being in the system (dynamic ids, look back earlier
in
this thread for details about that.)
On Tuesday 23 of July 2013 15:36:00 Alan Stern wrote:
On Tue, 23 Jul 2013, Tomasz Figa wrote:
IMHO it would be better if you provided some code example, but let's
try to check if I understood you correctly.
8
On Tuesday 23 of July 2013 11:04:14 Greg KH wrote:
On Tue, Jul 23, 2013 at 07:48:11PM +0200, Tomasz Figa wrote:
On Tuesday 23 of July 2013 10:37:11 Greg KH wrote:
On Tue, Jul 23, 2013 at 06:50:29PM +0200, Tomasz Figa wrote:
Ick, no. Why can't you just pass the pointer to the phy itself
On Tuesday 23 of July 2013 16:53:55 Alan Stern wrote:
On Tue, 23 Jul 2013, Tomasz Figa wrote:
That's what I was going to suggest too. The struct phy is defined
in
the board file, which already knows about all the PHYs that exist in
the system. (Or perhaps it is allocated dynamically
On Tuesday 23 of July 2013 13:50:07 Greg KH wrote:
On Tue, Jul 23, 2013 at 10:07:52PM +0200, Tomasz Figa wrote:
On Tuesday 23 of July 2013 12:44:23 Greg KH wrote:
On Tue, Jul 23, 2013 at 08:31:05PM +0100, Mark Brown wrote:
You don't know the id of the device you are looking up, due
On Tuesday 23 of July 2013 17:14:20 Alan Stern wrote:
On Tue, 23 Jul 2013, Tomasz Figa wrote:
If you want to keep the phy struct completely separate from the
board
file, there's an easy way to do it. Let's say the board file knows
about N different PHYs in the system. Then you
Hi,
On Saturday 20 of July 2013 19:59:10 Greg KH wrote:
On Sat, Jul 20, 2013 at 10:32:26PM -0400, Alan Stern wrote:
On Sat, 20 Jul 2013, Greg KH wrote:
That should be passed using platform data.
Ick, don't pass strings around, pass pointers. If you have
platform
data you
On Sunday 21 of July 2013 16:37:33 Kishon Vijay Abraham I wrote:
Hi,
On Sunday 21 July 2013 04:01 PM, Tomasz Figa wrote:
Hi,
On Saturday 20 of July 2013 19:59:10 Greg KH wrote:
On Sat, Jul 20, 2013 at 10:32:26PM -0400, Alan Stern wrote:
On Sat, 20 Jul 2013, Greg KH wrote
On Thursday 06 of June 2013 10:50:39 Jean-Christophe PLAGNIOL-VILLARD
wrote:
On 00:26 Thu 06 Jun , Grant Likely wrote:
On Tue, 09 Apr 2013 00:44:05 +0200, Javier Martinez Canillas
javier.marti...@collabora.co.uk wrote:
On 04/09/2013 12:05 AM, Rob Herring wrote:
On 04/05/2013 02:48
you want to achieve.
Best regards,
--
Tomasz Figa
Samsung Poland RD Center
SW Solution Development, Linux Platform
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:
kobject_uevent(udc-dev.kobj, KOBJ_REMOVE);
device_unregister(udc-dev);
- if (gadget-register_my_device)
device_unregister(gadget-dev);
Correct me if I am wrong, but doesn't this patch leave us with incorrect
indentation?
Otherwise looks good.
Best regards,
Tomasz Figa
,
err_put_udc, err_put_gadget, err_ret.
Otherwise looks good. Nice idea.
Reviewed-by: Tomasz Figa tomasz.f...@gmail.com
Best regards,
Tomasz Figa
udc-gadget = gadget;
@@ -189,18 +197,22 @@ int usb_add_gadget_udc(struct device *parent,
struct usb_gadget *gadget)
ret = device_add(udc
s3c_hsotg_remove(struct
platform_device *pdev) }
s3c_hsotg_phy_disable(hsotg);
-
clk_disable_unprepare(hsotg-clk);
- device_unregister(hsotg-gadget.dev);
return 0;
}
Looks good.
Reviewed-by: Tomasz Figa tomasz.f...@gmail.com
Best regards,
Tomasz Figa
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