On Wed, Feb 19, 2014 at 1:25 PM, Paul Walmsley p...@pwsan.com wrote:
Just FYI. Queued for v3.15 unless someone complains.
No complains but i wanted to point out that with some additional
changes it's possible
to consolidate AM335x (and AM437x) very nicely with the rest of OMAP4+
PRM/CM code.
On Wed, Feb 19, 2014 at 2:22 PM, Paul Walmsley p...@pwsan.com wrote:
On Wed, 19 Feb 2014, Vaibhav Bedia wrote:
On Wed, Feb 19, 2014 at 1:25 PM, Paul Walmsley p...@pwsan.com wrote:
Just FYI. Queued for v3.15 unless someone complains.
No complains but i wanted to point out that with some
Use the correct register offset for issuing the
reset command in OMAP5. Since dev_inst is set dynamically
OMAP4 should not be affected by this change.
Signed-off-by: Vaibhav Bedia vaibhav.be...@gmail.com
---
Applies on top of v3.14-rc3
arch/arm/mach-omap2/prminst44xx.c | 4 ++--
1 file changed
Hello,
Is there a specific reason why CONFIG_PREEMPT is not
enabled in omap2plus_defconfig?
Regards,
Vaibhav
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On Fri, Nov 22, 2013 at 2:50 PM, Ezequiel Garcia
ezequiel.gar...@free-electrons.com wrote:
[...]
And why specifically *2* seconds, instead of *1* or *33* ?
Sounds a bit like voodoo magic on this side :-)
Consider the scenario where the actual time is 00:00:01.95 secs.
Due to the 1 second
Hi Joel,
On Wed, Nov 6, 2013 at 12:36 PM, Joel Fernandes jo...@ti.com wrote:
Hi Vaibhav,
On 10/31/2013 05:25 PM, Vaibhav Bedia wrote:
Hi Daniel,
On Wed, Oct 30, 2013 at 4:21 PM, Daniel Mack zon...@gmail.com wrote:
[...]
+
+static SIMPLE_DEV_PM_OPS(edma_pm_ops, edma_pm_suspend
Hi Nishanth :)
On Thu, Nov 7, 2013 at 10:48 AM, Nishanth Menon n...@ti.com wrote:
On 11/07/2013 09:36 AM, Daniel Mack wrote:
On 11/07/2013 04:18 PM, Nishanth Menon wrote:
Tested this on a vendor V3.12 tag based kernel:
Test patch: http://pastebin.com/AmnktQ7B
test: echo -n
Hi Grygorii :)
On Thu, Nov 7, 2013 at 11:27 AM, Grygorii Strashko
grygorii.stras...@ti.com wrote:
On 11/07/2013 05:34 PM, Nishanth Menon wrote:
On 10/30/2013 03:21 PM, Daniel Mack wrote:
[...]
diff --git a/arch/arm/common/edma.c b/arch/arm/common/edma.c
index 8e1a024..f15cdb9 100644
---
Hi Daniel,
On Wed, Oct 30, 2013 at 4:21 PM, Daniel Mack zon...@gmail.com wrote:
[...]
+
+static SIMPLE_DEV_PM_OPS(edma_pm_ops, edma_pm_suspend, edma_pm_resume);
+
static struct platform_driver edma_driver = {
.driver = {
.name = edma,
+ .pm =
Hi Joel.
On Thu, Oct 10, 2013 at 1:32 AM, Joel Fernandes jo...@ti.com wrote:
On 10/09/2013 06:24 PM, Nishanth Menon wrote:
Call OMAP2+ generic lateinit hook from AM specific late init hook.
This allows the generic late initializations such as cpufreq hooks
to be active.
Cc: Benoit Cousson
(picking up an old thread, again)
On Thu, Aug 8, 2013 at 7:04 PM, Kevin Hilman khil...@linaro.org wrote:
I disagree here. I'm a firmware minimalist, and hiding bugs like this
in the firmware is wrong when Linux is otherwise managing these devices.
It also imposes criteria on the firmware of
On Tue, Aug 27, 2013 at 5:45 PM, Kevin Hilman khil...@linaro.org wrote:
[...]
Looking closer at this code as I'm trying to fully get my head around
all the IPC, I have some more comments.
I think the split between pm33xx.c and the M3 driver is still confusing
here. For example,
On Wed, Aug 21, 2013 at 3:13 AM, Rajendra Nayak rna...@ti.com wrote:
[...]
+/**
+ * omap4_cminst_clkdm_force_sleep - try to put a clockdomain to idle
+ * @part: PRCM partition ID that the clockdomain registers exist in
+ * @inst: CM instance register offset (*_INST macro)
+ * @cdoffs:
On Thu, Aug 29, 2013 at 5:33 PM, Kevin Hilman khil...@linaro.org wrote:
[...]
Maybe I'm getting confused, but the more you talk about the linux and
the firmware doing the same code, the more I think the firmware is
(trying) to do too much. If this is going to be understandable (and
rather heavy to do from the M3.
After the feedback Vaibhav Bedia received on v2 of his suspend/resume
patchset for am335x, he decided to move many of the operations from
sleep33xx.S into the M3 firmware.
See the commit message here:
http://arago-project.org/git/projects/?p=am33x-cm3.git
With all the minor issues addressed in previous patches
we can now safely migrate over AM335x to OMAP4 APIs and
get rid of the AM335x version of the same.
Signed-off-by: Vaibhav Bedia vaibhav.be...@ti.com
---
arch/arm/mach-omap2/cminst44xx.c | 7 ++
arch/arm/mach-omap2/io.c | 3
to be reworked since the OMAP4 code is moving to a different file.
Vaibhav Bedia (9):
ARM: OMAP2+: AM335X: Add a constant CM_INST for all the clkdomains
ARM: OMAP2+: CM code: Reintroduce SW_SLEEP for OMAP4 class of devices
ARM: OMAP2+: AM335X: Add a constant PRCM_PARITION for the pwrdomains
the API consistent with what
the comments states.
While here also fixup a trivial typo in the comment.
Signed-off-by: Vaibhav Bedia vaibhav.be...@ti.com
---
arch/arm/mach-omap2/cminst44xx.c | 18 --
1 file changed, 16 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-omap2
Reset status bits on AM335x have different masks and register
is not consistent across powerdomains. Generalize the OMAP4
reset handling code to take care of these.
Signed-off-by: Vaibhav Bedia vaibhav.be...@ti.com
---
arch/arm/mach-omap2/omap_hwmod.c | 7 +++
arch/arm/mach-omap2
Now that we have migrated AM335x over to use OMAP4 style
PRM, CM APIs we can delete the custom APIs
To avoid build breakage the reset function is reimplemented
in the same patch.
Signed-off-by: Vaibhav Bedia vaibhav.be...@ti.com
---
arch/arm/mach-omap2/Makefile | 3 +-
arch/arm/mach
Instead of hardcoded offsets of PWRSTCTRL and PWRSTST
use the offsets from the pwrdomain data. This helps
us in reusing the same code across OMAP4 and AM335x.
Signed-off-by: Vaibhav Bedia vaibhav.be...@ti.com
---
arch/arm/mach-omap2/prm44xx.c | 30 --
1 file changed
OMAP4 style PRM, CM APIs expect the pwrdomains to specify a
prcm_partition. Introduce a PRCM_PARTITION for the AM335x
pwrdomains so that we can eventually consolidate the code.
Signed-off-by: Vaibhav Bedia vaibhav.be...@ti.com
---
arch/arm/mach-omap2/powerdomains33xx_data.c | 6 ++
arch/arm
OMAP4 style PRM, CM APIs expect the clkdomains to specify a
cm_inst. Introduce a CM_INST for the AM335x clkdomains so that
we can eventually consolidate the code.
Signed-off-by: Vaibhav Bedia vaibhav.be...@ti.com
---
arch/arm/mach-omap2/clockdomains33xx_data.c | 18 ++
arch/arm
additional
fields pwrstctrl_offs and pwrstst_offs were introduced in
the pwrdomain data structure. To enable consolidation of
AM335x and OMAP4 lowlevel APIs add in the appropriate
offsets to the OMAP4 pwrdomains.
Signed-off-by: Vaibhav Bedia vaibhav.be...@ti.com
---
arch/arm/mach-omap2
API to avoid any regressions on AM335x
when it switches over to these APIs.
Signed-off-by: Vaibhav Bedia vaibhav.be...@ti.com
---
arch/arm/mach-omap2/cminst44xx.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/arch/arm/mach-omap2/cminst44xx.c b/arch/arm/mach-omap2/cminst44xx.c
index
of v3.8-rc5
v1-v2: Address the comments received from Sergei Shtylyov
and Peter Korsgaard.
v2-v3: Address an additional comment from Peter Korgaard
and add his Acked-by to the patches
Regards,
Vaibhav
[1] http://marc.info/?l=linux-arm-kernelm=135698501821074w=2
Vaibhav Bedia (9):
ARM: OMAP2
WKUP-M3 has a reset status bit (RM_WKUP_STST.WKUP_M3_LRST)
Update the WKUP-M3 hwmod data to reflect the same.
Signed-off-by: Vaibhav Bedia vaibhav.be...@ti.com
Acked-by: Peter Korsgaard jac...@sunsite.dk
---
v3: Add Peter's Acked-by
v2: No change
arch/arm/mach-omap2/omap_hwmod_33xx_data.c | 1
cm33xx.h unnecessarily includes a lot of header files.
Get rid of these and directly include iomap.h which
is needed to keep things compiling.
Signed-off-by: Vaibhav Bedia vaibhav.be...@ti.com
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
Acked-by: Peter Korsgaard jac...@sunsite.dk
---
v3
the clock to OCMC RAM as part of the
suspend process add the no_idle_on_suspend flag.
Signed-off-by: Vaibhav Bedia vaibhav.be...@ti.com
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
Acked-by: Peter Korsgaard jac...@sunsite.dk
---
v3: Update the compatible field as mentioned by Peter and his
OCMC RAM lies in the PER power domain and this memory
support retention.
Signed-off-by: Vaibhav Bedia vaibhav.be...@ti.com
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
Acked-by: Peter Korsgaard jac...@sunsite.dk
---
v3: Add Peter's Acked-by
v2: No change
arch/arm/mach-omap2
Add minimal APIs for writing to the IPC and the M3_TXEV registers
in the Control module. These will be used in a subsequent patch which
adds suspend-resume support for AM33XX.
Signed-off-by: Vaibhav Bedia vaibhav.be...@ti.com
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
Acked-by: Peter
Third Party Transfer Controller (TPTC0) needs to be idled and
put to standby under SW control. Add the appropriate flags in
the TPTC0 hwmod entry.
Signed-off-by: Vaibhav Bedia vaibhav.be...@ti.com
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
Acked-by: Peter Korsgaard jac...@sunsite.dk
accessing the wrong memory address for idle and standby
operations. Fix this by removing the ADDR_TYPE_RT flag from
the 1st memory region in CPGMAC0 hwmod entry.
Signed-off-by: Vaibhav Bedia vaibhav.be...@ti.com
Acked-by: Peter Korsgaard jac...@sunsite.dk
---
v3: Add Peter's Acked-by
v2: No change
This is necessary to ensure that macros declared here can
be reused from assembly files.
Signed-off-by: Vaibhav Bedia vaibhav.be...@ti.com
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
Acked-by: Peter Korsgaard jac...@sunsite.dk
---
v3: Add Peter's Acked-by
v2: No change
arch/arm/mach
WKUP-M3 has a reset status bit (RM_WKUP_STST.WKUP_M3_LRST)
Update the hardreset API to ensure that the reset line properly
deasserted.
Signed-off-by: Vaibhav Bedia vaibhav.be...@ti.com
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
Acked-by: Peter Korsgaard jac...@sunsite.dk
---
v3: Add
WKUP-M3 has a reset status bit (RM_WKUP_STST.WKUP_M3_LRST)
Update the WKUP-M3 hwmod data to reflect the same.
Signed-off-by: Vaibhav Bedia vaibhav.be...@ti.com
---
v2: No change
arch/arm/mach-omap2/omap_hwmod_33xx_data.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-omap2
This is necessary to ensure that macros declared here can
be reused from assembly files.
Signed-off-by: Vaibhav Bedia vaibhav.be...@ti.com
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
---
v2: No change
arch/arm/mach-omap2/cm33xx.h | 2 ++
arch/arm/mach-omap2/prm33xx.h | 2 ++
2 files
the comments
received from Sergei Shtylyov and Peter Korsgaard on the earlier
patchset [2].
These patches apply on top of v3.8-rc5
Regards,
Vaibhav
[1] http://marc.info/?l=linux-arm-kernelm=135698501821074w=2
[2] http://marc.info/?l=linux-omapm=135849360005657w=2
Vaibhav Bedia (9):
ARM: OMAP2+: AM33XX
cm33xx.h unnecessarily includes a lot of header files.
Get rid of these and directly include iomap.h which
is needed to keep things compiling.
Signed-off-by: Vaibhav Bedia vaibhav.be...@ti.com
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
---
v2: Reword the changelog
arch/arm/mach-omap2
Third Party Transfer Controller (TPTC0) needs to be idled and
put to standby under SW control. Add the appropriate flags in
the TPTC0 hwmod entry.
Signed-off-by: Vaibhav Bedia vaibhav.be...@ti.com
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
---
v2: Drop unnecessary parens
arch/arm/mach
the clock to OCMC RAM as part of the
suspend process add the no_idle_on_suspend flag.
Signed-off-by: Vaibhav Bedia vaibhav.be...@ti.com
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
---
v2: Add reg property
arch/arm/boot/dts/am33xx.dtsi | 14 ++
1 file changed, 14 insertions
accessing the wrong memory address for idle and standby
operations. Fix this by removing the ADDR_TYPE_RT flag from
the 1st memory region in CPGMAC0 hwmod entry.
Signed-off-by: Vaibhav Bedia vaibhav.be...@ti.com
---
v2: No change
arch/arm/mach-omap2/omap_hwmod_33xx_data.c | 1 -
1 file changed, 1
OCMC RAM lies in the PER power domain and this memory
support retention.
Signed-off-by: Vaibhav Bedia vaibhav.be...@ti.com
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
---
v2: No change
arch/arm/mach-omap2/omap_hwmod_33xx_data.c | 47 +-
1 file changed, 27
WKUP-M3 has a reset status bit (RM_WKUP_STST.WKUP_M3_LRST)
Update the hardreset API to ensure that the reset line properly
deasserted.
Signed-off-by: Vaibhav Bedia vaibhav.be...@ti.com
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
---
v2: No change
arch/arm/mach-omap2/omap_hwmod.c | 5
Add minimal APIs for writing to the IPC and the M3_TXEV registers
in the Control module. These will be used in a subsequent patch which
adds suspend-resume support for AM33XX.
Signed-off-by: Vaibhav Bedia vaibhav.be...@ti.com
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
---
v2: No change
Third Party Transfer Controller (TPTC0) needs to be idled and
put to standby under SW control. Add the appropriate flags in
the TPTC0 hwmod entry.
Signed-off-by: Vaibhav Bedia vaibhav.be...@ti.com
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
---
Change from RFC version:
Clarify
OCMC RAM lies in the PER power domain and this memory
support retention.
Signed-off-by: Vaibhav Bedia vaibhav.be...@ti.com
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
---
Change from RFC version:
No change
arch/arm/mach-omap2/omap_hwmod_33xx_data.c | 47
This is necessary to ensure that macros declared here can
be reused from assembly files.
Signed-off-by: Vaibhav Bedia vaibhav.be...@ti.com
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
---
Change from RFC version:
Get rid of extra lines
arch/arm/mach-omap2/cm33xx.h |2
WKUP-M3 has a reset status bit (RM_WKUP_STST.WKUP_M3_LRST)
Update the WKUP-M3 hwmod data to reflect the same.
Signed-off-by: Vaibhav Bedia vaibhav.be...@ti.com
---
Change from RFC version:
No change
arch/arm/mach-omap2/omap_hwmod_33xx_data.c |1 +
1 files changed, 1 insertions(+), 0
the clock to OCMC RAM as part of the
suspend process add the no_idle_on_suspend flag.
Signed-off-by: Vaibhav Bedia vaibhav.be...@ti.com
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
---
Change from RFC version:
No change
arch/arm/boot/dts/am33xx.dtsi | 11 +++
1 files
Some of the included header files are not needed so
remove them.
Signed-off-by: Vaibhav Bedia vaibhav.be...@ti.com
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
---
Change from RFC version:
No change
arch/arm/mach-omap2/cm33xx.h |7 +--
1 files changed, 1 insertions(+), 6
of v3.8-rc3
Regards,
Vaibhav
[1] http://marc.info/?l=linux-arm-kernelm=135698501821074w=2
Vaibhav Bedia (9):
ARM: OMAP2+: AM33XX: CM: Get rid of unncessary header inclusions
ARM: OMAP2+: AM33XX: CM/PRM: Use __ASSEMBLER__ macros in header files
ARM: OMAP2+: AM33XX: hwmod: Register OCMC RAM hwmod
WKUP-M3 has a reset status bit (RM_WKUP_STST.WKUP_M3_LRST)
Update the hardreset API to ensure that the reset line properly
deasserted.
Signed-off-by: Vaibhav Bedia vaibhav.be...@ti.com
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
---
Change from RFC version:
No change
arch/arm
Add minimal APIs for writing to the IPC and the M3_TXEV registers
in the Control module. These will be used in a subsequent patch which
adds suspend-resume support for AM33XX.
Signed-off-by: Vaibhav Bedia vaibhav.be...@ti.com
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
---
Change from
accessing the wrong memory address for idle and standby
operations. Fix this by removing the ADDR_TYPE_RT flag from
the 1st memory region in CPGMAC0 hwmod entry.
Signed-off-by: Vaibhav Bedia vaibhav.be...@ti.com
---
Change from RFC version:
No change
arch/arm/mach-omap2
/projects/?p=am33x-cm3.git;a=shortlog;h=refs/heads/next
Vaibhav Bedia (18):
mailbox: OMAP2+: Add support for AM33XX
mailbox: Add an API for flushing the FIFO
memory: emif: Move EMIF related header file to include/linux/
ARM: OMAP2+: AM33XX: CM: Get rid of unncessary header inclusions
ARM
Mailbox IP on AM33XX is the same as that present in OMAP4.
The single instance of Mailbox IP on AM33XX contains
8 sub-modules and facilitates communication between MPU,
PRUs and WKUP_M3.
The first mailbox sub-module is assigned for communication
between MPU and WKUP-M3.
Signed-off-by: Vaibhav
in the mailbox code which the MPU
can use to empty the FIFO by issuing a readback command.
Signed-off-by: Vaibhav Bedia vaibhav.be...@ti.com
Cc: Santosh Shilimkar santosh.shilim...@ti.com
---
Note: This patch which will be slightly reworked once the mailbox
driver changes are finalized.
drivers
Some of the included header files are not needed so
remove them.
Signed-off-by: Vaibhav Bedia vaibhav.be...@ti.com
Cc: Santosh Shilimkar santosh.shilim...@ti.com
Cc: Benoit Cousson b-cous...@ti.com
Cc: Paul Walmsley p...@pwsan.com
Cc: Kevin Hilman khil...@deeprootsystems.com
Cc: Vaibhav Hiremath
This is necessary to ensure that macros declared here can
be reused from assembly files.
Signed-off-by: Vaibhav Bedia vaibhav.be...@ti.com
Cc: Santosh Shilimkar santosh.shilim...@ti.com
Cc: Paul Walmsley p...@pwsan.com
Cc: Benoit Cousson b-cous...@ti.com
Cc: Kevin Hilman khil
OCMC RAM lies in the PER power domain and this memory
support retention.
Signed-off-by: Vaibhav Bedia vaibhav.be...@ti.com
Cc: Santosh Shilimkar santosh.shilim...@ti.com
Cc: Benoit Cousson b-cous...@ti.com
Cc: Paul Walmsley p...@pwsan.com
Cc: Kevin Hilman khil...@deeprootsystems.com
Cc: Vaibhav
TPTC0 needs to be idled and put to standby under SW control.
Add the appropriate flags in the TPTC0 hwmod entry.
Signed-off-by: Vaibhav Bedia vaibhav.be...@ti.com
Cc: Santosh Shilimkar santosh.shilim...@ti.com
Cc: Benoit Cousson b-cous...@ti.com
Cc: Paul Walmsley p...@pwsan.com
Cc: Kevin Hilman
accessing the wrong memory address for idle and standby
operations. Fix this by removing the ADDR_TYPE_RT flag from
the 1st memory region in CPGMAC0 hwmod entry.
Signed-off-by: Vaibhav Bedia vaibhav.be...@ti.com
Cc: Santosh Shilimkar santosh.shilim...@ti.com
Cc: Benoit Cousson b-cous...@ti.com
Cc
WKUP-M3 has a reset status bit (RM_WKUP_STST.WKUP_M3_LRST)
Update the WKUP-M3 hwmod data to reflect the same.
Signed-off-by: Vaibhav Bedia vaibhav.be...@ti.com
Cc: Santosh Shilimkar santosh.shilim...@ti.com
Cc: Benoit Cousson b-cous...@ti.com
Cc: Paul Walmsley p...@pwsan.com
Cc: Kevin Hilman khil
WKUP-M3 has a reset status bit (RM_WKUP_STST.WKUP_M3_LRST)
Update the hardreset API to ensure that the reset line properly
deasserted.
Signed-off-by: Vaibhav Bedia vaibhav.be...@ti.com
Cc: Santosh Shilimkar santosh.shilim...@ti.com
Cc: Benoit Cousson b-cous...@ti.com
Cc: Paul Walmsley p
the clock to OCMC RAM as part of the
suspend process add the no_idle_on_suspend flag.
Signed-off-by: Vaibhav Bedia vaibhav.be...@ti.com
Cc: Tony Lindgren t...@atomide.com
Cc: Santosh Shilimkar santosh.shilim...@ti.com
Cc: Benoit Cousson b-cous...@ti.com
Cc: Paul Walmsley p...@pwsan.com
Cc: Kevin
of clock event devices) introduced .suspend and .resume
callbacks for clock event devices. Leverages these
callbacks to have AM33XX clockevent timer which is
in not in WKUP domain to behave properly across system
suspend.
Signed-off-by: Vaibhav Bedia vaibhav.be...@ti.com
Cc: Santosh Shilimkar
on AM33XX so for now we go ahead with the interchange
of the the timers. If at a later point of time we do come up
with an approach which makes soc-idle possible on AM33XX, this
can be revisited.
Signed-off-by: Vaibhav Bedia vaibhav.be...@ti.com
Signed-off-by: Vaibhav Hiremath hvaib...@ti.com
Cc: Tony
Add minimal APIs for writing to the IPC and the M3_TXEV registers
in the Control module. These will be used in a subsequent patch which
adds suspend-resume support for AM33XX.
Signed-off-by: Vaibhav Bedia vaibhav.be...@ti.com
Cc: Tony Lingren t...@atomide.com
Cc: Santosh Shilimkar santosh.shilim
version
of the AM33XX suspend-resume support.
Signed-off-by: Vaibhav Bedia vaibhav.be...@ti.com
Cc: Tony Lingren t...@atomide.com
Cc: Santosh Shilimkar santosh.shilim...@ti.com
Cc: Benoit Cousson b-cous...@ti.com
Cc: Paul Walmsley p...@pwsan.com
Cc: Kevin Hilman khil...@deeprootsystems.com
---
v1-v2
With all the requisite changes in place we can now
enable basic PM support on AM33XX. This patch updates
the various OMAP files to enable suspend-resume on
AM33XX.
Signed-off-by: Vaibhav Bedia vaibhav.be...@ti.com
Cc: Tony Lingren t...@atomide.com
Cc: Santosh Shilimkar santosh.shilim...@ti.com
Cc
downs on the IOs to reduce leakage in low power state.
Signed-off-by: Vaibhav Bedia vaibhav.be...@ti.com
Cc: Santosh Shilimkar santosh.shilim...@ti.com
Cc: Kevin Hilman khil...@deeprootsystems.com
---
v1-v2:
This is a new patch in the series to keep the
assembly code additionl
.
The low level code in OCMC relocks the PLLs, enables access
to external RAM and then jumps to the cpu_resume code of
the kernel to finish the resume process.
Signed-off-by: Vaibhav Bedia vaibhav.be...@ti.com
Cc: Tony Lingren t...@atomide.com
Cc: Santosh Shilimkar santosh.shilim...@ti.com
Cc: Benoit
OMAP PM framework the PM code resides under
arch/arm/mach-omap2/. To enable reuse of the register defines move
the emif header file to include/linux so that both the EMIF driver
and the AM33XX PM code can benefit.
Signed-off-by: Vaibhav Bedia vaibhav.be...@ti.com
Cc: Santosh Shilimkar
'omap_pm_set_max_mpu_wakeup_lat'
make[1]: *** [arch/arm/mach-omap2/i2c.o] Error 1
...
Fix this by including the appropriate header file with the function prototype
Reported-by: Fengguang Wu fengguang...@intel.com
Signed-off-by: Vaibhav Bedia vaibhav.be...@ti.com
---
arch/arm/mach-omap2/i2c.c
'omap_pm_set_max_mpu_wakeup_lat'
make[1]: *** [arch/arm/mach-omap2/i2c.o] Error 1
...
Fix this by including the appropriate header file with the function prototype
Reported-by: Fengguang Wu fengguang...@intel.com
Signed-off-by: Vaibhav Bedia vaibhav.be...@ti.com
---
arch/arm/mach-omap2/i2c.c
in the mailbox code which the MPU
can use to empty the FIFO by issuing a readback command.
Signed-off-by: Vaibhav Bedia vaibhav.be...@ti.com
---
arch/arm/mach-omap2/mailbox.c | 42 -
arch/arm/plat-omap/include/plat/mailbox.h |3 ++
arch/arm/plat-omap
Add the reset status offset for WKUP_M3 in the hwmod data
Signed-off-by: Vaibhav Bedia vaibhav.be...@ti.com
---
arch/arm/mach-omap2/omap_hwmod_33xx_data.c |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
b/arch/arm/mach-omap2
/pdf/spruh73f
[2] http://arago-project.org/git/projects/?p=am33x-cm3.git;a=summary
[3] https://patchwork.kernel.org/patch/1661771/
Vaibhav Bedia (15):
ARM: OMAP2+: mailbox: Add an API for flushing the FIFO
ARM: OMAP2+: mailbox: Add support for AM33XX
ARM: OMAP: mailbox: Convert
These registers will be required in a subsequent
patch which adds basic suspend-resume support for
AM33XX.
Signed-off-by: Vaibhav Bedia vaibhav.be...@ti.com
---
arch/arm/mach-omap2/control.h | 29 +
1 files changed, 29 insertions(+), 0 deletions(-)
diff --git
Update the TPTC hwmod entry to reflect the fact that
the idle and standby transitions are s/w controlled.
Signed-off-by: Vaibhav Bedia vaibhav.be...@ti.com
---
arch/arm/mach-omap2/omap_hwmod_33xx_data.c |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2
Signed-off-by: Vaibhav Bedia vaibhav.be...@ti.com
---
arch/arm/boot/dts/am33xx.dtsi | 11 +++
1 files changed, 11 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index bb31bff..e2cbf24 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
The first entry for CPGMAC0 should be ADDR_MAP_ON_INIT
instead of ADDR_TYPE_RT to ensure the omap hwmod code
maps the memory space at init and writes to the SYSCONFIG
registers.
Signed-off-by: Vaibhav Bedia vaibhav.be...@ti.com
---
arch/arm/mach-omap2/omap_hwmod_33xx_data.c |2 +-
1 files
The power management code for AM33XX is a late_initcall
and the PM features depend on the mailbox for IPC.
In preparation for this, convert the mailbox init to
a device_initcall.
Signed-off-by: Vaibhav Bedia vaibhav.be...@ti.com
---
arch/arm/mach-omap2/mailbox.c |2 +-
1 files changed, 1
Get rid of some unnecessary header file inclusions
and also use __ASSEMBLER__ macros to allow the
various register offsets from PM assembly code
which be added in a subsequent patch.
Signed-off-by: Vaibhav Bedia vaibhav.be...@ti.com
---
arch/arm/mach-omap2/clock33xx_data.c |1 +
arch/arm
AM33XX PM code depends on Mailbox module for IPC
between MPU and WKUP_M3.
Signed-off-by: Vaibhav Bedia vaibhav.be...@ti.com
---
arch/arm/configs/omap2plus_defconfig |2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/arch/arm/configs/omap2plus_defconfig
b/arch/arm/configs
The hwmod data for OCMCRAM in AM33XX was commented out.
This data is needed by the power management code, hence
uncomment the same and register the OCP interface for it.
Signed-off-by: Vaibhav Bedia vaibhav.be...@ti.com
---
arch/arm/mach-omap2/omap_hwmod_33xx_data.c | 11 ++-
1 files
WKUP-M3 has a reset status bit (RM_WKUP_STST.WKUP_M3_LRST)
Update the hardreset API to take care of the same to ensure
that the reset line properly deasserted.
Signed-off-by: Vaibhav Bedia vaibhav.be...@ti.com
---
arch/arm/mach-omap2/omap_hwmod.c |5 +
arch/arm/mach-omap2/prm33xx.c
hvaib...@ti.com
Signed-off-by: Vaibhav Bedia vaibhav.be...@ti.com
---
arch/arm/mach-omap2/timer.c | 31 +++
1 files changed, 31 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 6584ee0..e8781fd 100644
--- a/arch
access
to external RAM and then jumps to the cpu_resume code of
the kernel to finish the resume process.
Signed-off-by: Vaibhav Bedia vaibhav.be...@ti.com
---
arch/arm/mach-omap2/Makefile|2 +
arch/arm/mach-omap2/board-generic.c |1 +
arch/arm/mach-omap2/common.h| 10 +
arch
this, interchange
the timers used as clocksource and clockevent for
AM33XX. A subsequent patch will add suspend-resume
support for the clockevent to ensure that there are
no issues with timekeeping.
Signed-off-by: Vaibhav Bedia vaibhav.be...@ti.com
---
arch/arm/mach-omap2/timer.c |2 +-
1 files
Mailbox IP on AM33XX, is the same as that present
in OMAP4. The single instance of Mailbox module
contains 8 sub-modules and facilitates communication
between MPU, PRUs and WKUP_M3.
The first mailbox sub-module is assigned for
communication between MPU and WKUP-M3.
Signed-off-by: Vaibhav Bedia
-off-by: Vaibhav Bedia vaibhav.be...@ti.com
---
arch/arm/mach-omap2/omap_hwmod.c | 11 ++-
1 files changed, 10 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 6ca8e51..90e2306 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
on the check
for DT blob. Since the suspend-resume operation should not
really be dependent on the usage of DT remove this dependency
by wrapping the PMIC and SR init under the DT check.
Signed-off-by: Vaibhav Bedia vaibhav.be...@ti.com
---
v2-v1
- As suggested by Paul, Instead of moving around
on the check
for DT blob. Since the suspend-resume operation should not
really be dependent on the usage of DT, move the suspend ops
registration before the check for DT.
Signed-off-by: Vaibhav Bedia vaibhav.be...@ti.com
---
arch/arm/mach-omap2/pm.c |8
1 files changed, 4 insertions(+), 4
skipping the autoidle_reg entry in the DPLL data
is sufficient.
Signed-off-by: Vaibhav Bedia vaibhav.be...@ti.com
---
This change is needed for AM33xx, which does not support
autoidle mode for the DPLLs.
arch/arm/mach-omap2/dpll3xxx.c | 23 ++-
1 files changed, 18 insertions(+), 5
skipping the autoidle_reg entry in the DPLL data
is sufficient.
Signed-off-by: Vaibhav Bedia vaibhav.be...@ti.com
---
arch/arm/mach-omap2/dpll3xxx.c | 23 ++-
1 files changed, 18 insertions(+), 5 deletions(-)
diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2
The call to pwrdm_wait_transition() in clkdm_clk_enable()
is redundant since the function pwrdm_clkdm_state_switch()
which is called next also does the same thing.
Signed-off-by: Vaibhav Bedia vaibhav.be...@ti.com
---
arch/arm/mach-omap2/clockdomain.c |1 -
1 files changed, 0 insertions
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