On Fri, 27 Apr 2012, Rajendra Nayak wrote:
> The register bits for MPU_CLK_SRC and IVA2_CLK_SRC
> in CM_CLKSEL1_PLL register are 3 bits wide.
> Fix the MASK definition accordingly.
>
> Signed-off-by: Rajendra Nayak
Thanks, queued for 3.5.
- Paul
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The register bits for MPU_CLK_SRC and IVA2_CLK_SRC
in CM_CLKSEL1_PLL register are 3 bits wide.
Fix the MASK definition accordingly.
Signed-off-by: Rajendra Nayak
---
arch/arm/mach-omap2/cm-regbits-34xx.h |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-om