Hi Santosh,
On Tue, Aug 13, 2013 at 02:31:04PM +0100, Santosh Shilimkar wrote:
On Tuesday 13 August 2013 07:19 AM, Will Deacon wrote:
On Mon, Aug 12, 2013 at 07:34:13PM +0100, Santosh Shilimkar wrote:
On Friday 02 August 2013 11:48 AM, Will Deacon wrote:
I think this an A9-specific
-0400
Subject: [PATCH] ARM: Update SMP_ON_UP code to detect A9MPCore with 1 CPU
devices
The generic code is well equipped to differentiate between
SMP and UP configurations.However, there are some devices which
use Cortex-A9 MP core IP with 1 CPU as configuration. To let
these SOCs to co-exist
On 8/13/2013 7:01 PM, Santosh Shilimkar wrote:
On Tuesday 13 August 2013 07:19 AM, Will Deacon wrote:
On Mon, Aug 12, 2013 at 07:34:13PM +0100, Santosh Shilimkar wrote:
On Friday 02 August 2013 11:48 AM, Will Deacon wrote:
I think this an A9-specific register, which reads as 0 on UP A9 and
On Friday 23 August 2013 01:08 PM, Sekhar Nori wrote:
On 8/13/2013 7:01 PM, Santosh Shilimkar wrote:
On Tuesday 13 August 2013 07:19 AM, Will Deacon wrote:
On Mon, Aug 12, 2013 at 07:34:13PM +0100, Santosh Shilimkar wrote:
On Friday 02 August 2013 11:48 AM, Will Deacon wrote:
I think this an
On 8/23/2013 10:47 PM, Santosh Shilimkar wrote:
On Friday 23 August 2013 01:08 PM, Sekhar Nori wrote:
On 8/13/2013 7:01 PM, Santosh Shilimkar wrote:
On Tuesday 13 August 2013 07:19 AM, Will Deacon wrote:
On Mon, Aug 12, 2013 at 07:34:13PM +0100, Santosh Shilimkar wrote:
On Friday 02 August
On Mon, Aug 12, 2013 at 07:34:13PM +0100, Santosh Shilimkar wrote:
On Friday 02 August 2013 11:48 AM, Will Deacon wrote:
I think this an A9-specific register, which reads as 0 on UP A9 and reads as
some form of PERIPH_BASE for SMP parts. The issue I have is when PERIPH_BASE
is zero.
On Tuesday 13 August 2013 07:19 AM, Will Deacon wrote:
On Mon, Aug 12, 2013 at 07:34:13PM +0100, Santosh Shilimkar wrote:
On Friday 02 August 2013 11:48 AM, Will Deacon wrote:
I think this an A9-specific register, which reads as 0 on UP A9 and reads as
some form of PERIPH_BASE for SMP parts.
Will,
On Friday 02 August 2013 11:48 AM, Will Deacon wrote:
On Fri, Aug 02, 2013 at 04:45:46PM +0100, Sudeep KarkadaNagesha wrote:
On 02/08/13 16:22, Santosh Shilimkar wrote:
+ @ Core indicates it is SMP. Check for Aegis SOC where a single
+ @ Cortex-A9 CPU is present but SMP operations
On Thu, Aug 01, 2013 at 07:17:13PM +0100, Santosh Shilimkar wrote:
From: Vaibhav Bedia vaibhav.be...@ti.com
The generic code is well equipped to differentiate between
SMP and UP configurations.However, there are some devices which
use Cortex-A9 MP core IP with 1 CPU as configuration. To let
On Friday 02 August 2013 05:53 AM, Will Deacon wrote:
On Thu, Aug 01, 2013 at 07:17:13PM +0100, Santosh Shilimkar wrote:
From: Vaibhav Bedia vaibhav.be...@ti.com
The generic code is well equipped to differentiate between
SMP and UP configurations.However, there are some devices which
use
On Thu, Aug 01, 2013 at 02:17:13PM -0400, Santosh Shilimkar wrote:
From: Vaibhav Bedia vaibhav.be...@ti.com
The generic code is well equipped to differentiate between
SMP and UP configurations.However, there are some devices which
use Cortex-A9 MP core IP with 1 CPU as configuration. To let
On 01/08/13 19:17, Santosh Shilimkar wrote:
From: Vaibhav Bedia vaibhav.be...@ti.com
The generic code is well equipped to differentiate between
SMP and UP configurations.However, there are some devices which
use Cortex-A9 MP core IP with 1 CPU as configuration. To let
these SOCs to co-exist
On Friday 02 August 2013 10:18 AM, Dave Martin wrote:
On Thu, Aug 01, 2013 at 02:17:13PM -0400, Santosh Shilimkar wrote:
From: Vaibhav Bedia vaibhav.be...@ti.com
The generic code is well equipped to differentiate between
SMP and UP configurations.However, there are some devices which
use
On Friday 02 August 2013 10:45 AM, Sudeep KarkadaNagesha wrote:
On 01/08/13 19:17, Santosh Shilimkar wrote:
From: Vaibhav Bedia vaibhav.be...@ti.com
The generic code is well equipped to differentiate between
SMP and UP configurations.However, there are some devices which
use Cortex-A9 MP
On 02/08/13 16:22, Santosh Shilimkar wrote:
On Friday 02 August 2013 10:45 AM, Sudeep KarkadaNagesha wrote:
On 01/08/13 19:17, Santosh Shilimkar wrote:
From: Vaibhav Bedia vaibhav.be...@ti.com
The generic code is well equipped to differentiate between
SMP and UP configurations.However, there
On Fri, Aug 02, 2013 at 04:45:46PM +0100, Sudeep KarkadaNagesha wrote:
On 02/08/13 16:22, Santosh Shilimkar wrote:
+ @ Core indicates it is SMP. Check for Aegis SOC where a single
+ @ Cortex-A9 CPU is present but SMP operations fault.
+ mov r4, #0x4100
+ orr r4, r4,
From: Vaibhav Bedia vaibhav.be...@ti.com
The generic code is well equipped to differentiate between
SMP and UP configurations.However, there are some devices which
use Cortex-A9 MP core IP with 1 CPU as configuration. To let
these SOCs to co-exist in a CONFIG_SMP=y build by leveraging
the
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