On Thu, Sep 8, 2011 at 3:41 PM, Mark Salter msal...@redhat.com wrote:
On Wed, 2011-08-31 at 20:35 +0100, Will Deacon wrote:
On Wed, Aug 31, 2011 at 07:19:33PM +0100, Rob Herring wrote:
On 08/31/2011 12:51 PM, Will Deacon wrote:
Another thing that Marc and I tried on OMAP4 was not bringing
On Wed, 2011-08-31 at 20:35 +0100, Will Deacon wrote:
On Wed, Aug 31, 2011 at 07:19:33PM +0100, Rob Herring wrote:
On 08/31/2011 12:51 PM, Will Deacon wrote:
Another thing that Marc and I tried on OMAP4 was not bringing up the
secondary
CPU during boot (by commenting out most of
On 01/09/11 20:08, Stephen Warren wrote:
Marc Dietich wrote at Thursday, September 01, 2011 5:14 AM:
I'll add Stephen Warren from NVIDIA to the CC list. He has more HW to test
on.
Here are the results I found:
Harmony:
Tegra USB3 - SMSC9514 hub: NOT affected
(Unplugging LAN cable, or
just another measurement point
Stephen Warren wrote at Thursday:
Here are the results I found:
Harmony:
Tegra USB3 - SMSC9514 hub: NOT affected
(Unplugging LAN cable, or disabling SMSC9514 LAN driver doesn't change
this)
Seaboard (springbank; clamshell):
Tegra USB1 - no hub: Affected
Marc Zyngier wrote at Friday, September 02, 2011 3:51 AM:
On 01/09/11 20:08, Stephen Warren wrote:
Marc Dietich wrote at Thursday, September 01, 2011 5:14 AM:
I'll add Stephen Warren from NVIDIA to the CC list. He has more HW to test
on.
Here are the results I found:
Harmony:
Hi Marc,
On 31/08/11 17:55, Marc Dietrich wrote:
Am Mittwoch 31 August 2011, 18:12:48 schrieb Marc Zyngier:
[...]
Oddly enough, this patch doesn't do anything on my Tegra setup. In both
cases, I get around 17MB/s from a crap SD card plugged in a USB reader.
This leads me to suspect that
Hi Marc,
^dito,
On 31/08/11 17:55, Marc Dietrich wrote:
Am Mittwoch 31 August 2011, 18:12:48 schrieb Marc Zyngier:
[...]
Oddly enough, this patch doesn't do anything on my Tegra setup. In both
cases, I get around 17MB/s from a crap SD card plugged in a USB reader.
This leads me to
Marc Dietich wrote at Thursday, September 01, 2011 5:14 AM:
I'll add Stephen Warren from NVIDIA to the CC list. He has more HW to test on.
Here are the results I found:
Harmony:
Tegra USB3 - SMSC9514 hub: NOT affected
(Unplugging LAN cable, or disabling SMSC9514 LAN driver doesn't change this)
Mark Salter msalter at redhat.com writes:
On Wed, 2011-08-31 at 00:03 +0800, ming.lei at canonical.com wrote:
...
+#ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
+static inline void ehci_sync_mem()
+{
+ mb();
+}
+#else
+static inline void ehci_sync_mem()
+{
+}
+#endif
...
On Wed, Aug 31, 2011 at 01:23:47AM +0100, Chen Peter-B29397 wrote:
One question: why this write buffer issue did not happen at UP ARM V7
platform, whose dma buffer
also uncache, but bufferable?
Which CPU was on this platform?
Will
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Best Regard,
Peter Chen
On Aug 31, 2011, at 4:49 PM, Will Deacon wrote:
On Wed, Aug 31, 2011 at 01:23:47AM +0100, Chen Peter-B29397 wrote:
One question: why this write buffer issue did not happen at UP ARM V7
platform, whose dma buffer
also uncache, but bufferable?
Which CPU was on
On Wed, 2011-08-31 at 09:49 +0100, Will Deacon wrote:
On Wed, Aug 31, 2011 at 01:23:47AM +0100, Chen Peter-B29397 wrote:
One question: why this write buffer issue did not happen at UP ARM V7
platform, whose dma buffer
also uncache, but bufferable?
Which CPU was on this platform?
Using
On Wed, Aug 31, 2011 at 02:43:33PM +0100, Mark Salter wrote:
On Wed, 2011-08-31 at 09:49 +0100, Will Deacon wrote:
On Wed, Aug 31, 2011 at 01:23:47AM +0100, Chen Peter-B29397 wrote:
One question: why this write buffer issue did not happen at UP ARM V7
platform, whose dma buffer
also
On Wed, 2011-08-31 at 16:21 +0100, Will Deacon wrote:
On Wed, Aug 31, 2011 at 02:43:33PM +0100, Mark Salter wrote:
On Wed, 2011-08-31 at 09:49 +0100, Will Deacon wrote:
On Wed, Aug 31, 2011 at 01:23:47AM +0100, Chen Peter-B29397 wrote:
One question: why this write buffer issue did not
On 31/08/11 16:27, Mark Salter wrote:
On Wed, 2011-08-31 at 16:21 +0100, Will Deacon wrote:
On Wed, Aug 31, 2011 at 02:43:33PM +0100, Mark Salter wrote:
On Wed, 2011-08-31 at 09:49 +0100, Will Deacon wrote:
On Wed, Aug 31, 2011 at 01:23:47AM +0100, Chen Peter-B29397 wrote:
One question: why
Am Mittwoch 31 August 2011, 18:12:48 schrieb Marc Zyngier:
[...]
Oddly enough, this patch doesn't do anything on my Tegra setup. In both
cases, I get around 17MB/s from a crap SD card plugged in a USB reader.
This leads me to suspect that this issue is very much OMAP4 specific.
Can anyone
On Wed, 31 Aug 2011, Will Deacon wrote:
On Wed, Aug 31, 2011 at 02:43:33PM +0100, Mark Salter wrote:
On Wed, 2011-08-31 at 09:49 +0100, Will Deacon wrote:
On Wed, Aug 31, 2011 at 01:23:47AM +0100, Chen Peter-B29397 wrote:
One question: why this write buffer issue did not happen at UP
On 08/31/2011 12:51 PM, Will Deacon wrote:
On Wed, Aug 31, 2011 at 06:46:50PM +0100, Nicolas Pitre wrote:
On Wed, 31 Aug 2011, Will Deacon wrote:
On Wed, Aug 31, 2011 at 02:43:33PM +0100, Mark Salter wrote:
On Wed, 2011-08-31 at 09:49 +0100, Will Deacon wrote:
On Wed, Aug 31, 2011 at
On Wed, 2011-08-31 at 13:49 -0500, Rob Herring wrote:
An outer_sync will only drain the write buffer of the L2. It does not
flush the cache though. If the write buffer does in fact keep data as
long as possible (until it needs a free slot or the line is full), then
long delays to write out
From: Ming Lei ming@canonical.com
This patch introduces the helper of ehci_sync_mem to flush
qtd/qh into memory immediately on some ARM, so that HC can
see the up-to-date qtd/qh descriptor asap.
This patch fixs one performance bug on ARM Cortex A9 dual core
platform, which has been reported
On Wed, 31 Aug 2011 ming@canonical.com wrote:
From: Ming Lei ming@canonical.com
This patch introduces the helper of ehci_sync_mem to flush
qtd/qh into memory immediately on some ARM, so that HC can
see the up-to-date qtd/qh descriptor asap.
This patch fixs one performance bug on
On Wed, 2011-08-31 at 00:03 +0800, ming@canonical.com wrote:
+/*
+ * Writing to dma coherent memory on ARM may be delayed via L2
+ * writing buffer, so introduce the helper which can flush L2 writing
+ * buffer into memory immediately, especially used to flush ehci
+ * descriptor to
On Tue, 30 Aug 2011, Mark Salter wrote:
On Wed, 2011-08-31 at 00:03 +0800, ming@canonical.com wrote:
+/*
+ * Writing to dma coherent memory on ARM may be delayed via L2
+ * writing buffer, so introduce the helper which can flush L2 writing
+ * buffer into memory immediately,
On Tue, Aug 30, 2011 at 05:38:30PM +0100, Mark Salter wrote:
On Wed, 2011-08-31 at 00:03 +0800, ming@canonical.com wrote:
+/*
+ * Writing to dma coherent memory on ARM may be delayed via L2
+ * writing buffer, so introduce the helper which can flush L2 writing
+ * buffer into memory
On Tue, Aug 30, 2011 at 06:26:42PM +0100, Will Deacon wrote:
On Tue, Aug 30, 2011 at 05:38:30PM +0100, Mark Salter wrote:
On Wed, 2011-08-31 at 00:03 +0800, ming@canonical.com wrote:
+/*
+ * Writing to dma coherent memory on ARM may be delayed via L2
+ * writing buffer, so
On Tue, Aug 30, 2011 at 06:48:59PM +0100, Greg KH wrote:
On Tue, Aug 30, 2011 at 06:26:42PM +0100, Will Deacon wrote:
On Tue, Aug 30, 2011 at 05:38:30PM +0100, Mark Salter wrote:
On Wed, 2011-08-31 at 00:03 +0800, ming@canonical.com wrote:
+/*
+ * Writing to dma coherent memory
On Tue, 2011-08-30 at 13:15 -0400, Alan Stern wrote:
On Tue, 30 Aug 2011, Mark Salter wrote:
On Wed, 2011-08-31 at 00:03 +0800, ming@canonical.com wrote:
+/*
+ * Writing to dma coherent memory on ARM may be delayed via L2
+ * writing buffer, so introduce the helper which can
On Aug 31, 2011, at 1:54 AM, Will Deacon wrote:
On Tue, Aug 30, 2011 at 06:48:59PM +0100, Greg KH wrote:
On Tue, Aug 30, 2011 at 06:26:42PM +0100, Will Deacon wrote:
On Tue, Aug 30, 2011 at 05:38:30PM +0100, Mark Salter wrote:
On Wed, 2011-08-31 at 00:03 +0800, ming@canonical.com wrote:
On Wed, Aug 31, 2011 at 1:54 AM, Will Deacon will.dea...@arm.com wrote:
Although this doesn't have anything to do with ordering; it's all to do with
immediacy so I think we should try to avoiding using the term `barrier'. If
this can be made part of the coherent DMA API, that might be the best
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