On Sun, Jan 18, 2015 at 09:52:14AM +, Lee Jones wrote:
On Fri, 26 Dec 2014, Felipe Balbi wrote:
STATUS register can be modified by the HW, so we
should bypass cache because of that.
In the case of INT[12] registers, they are the ones
that actually clear the IRQ source at the time
On Fri, 26 Dec 2014, Felipe Balbi wrote:
STATUS register can be modified by the HW, so we
should bypass cache because of that.
In the case of INT[12] registers, they are the ones
that actually clear the IRQ source at the time they
are read. If we rely on the cache for them, we will
never
Hi,
On Wed, Jan 14, 2015 at 09:07:17AM -0800, Tony Lindgren wrote:
STATUS register can be modified by the HW, so we
should bypass cache because of that.
In the case of INT[12] registers, they are the ones
that actually clear the IRQ source at the time they
are read.
* Felipe Balbi ba...@ti.com [150112 08:50]:
Hi,
On Thu, Jan 08, 2015 at 10:25:12AM -0600, Felipe Balbi wrote:
On Tue, Jan 06, 2015 at 11:37:34AM -0600, Felipe Balbi wrote:
On Fri, Dec 26, 2014 at 01:28:20PM -0600, Felipe Balbi wrote:
STATUS register can be modified by the HW, so we
Hi,
On Thu, Jan 08, 2015 at 10:25:12AM -0600, Felipe Balbi wrote:
On Tue, Jan 06, 2015 at 11:37:34AM -0600, Felipe Balbi wrote:
On Fri, Dec 26, 2014 at 01:28:20PM -0600, Felipe Balbi wrote:
STATUS register can be modified by the HW, so we
should bypass cache because of that.
In
On Tue, Jan 06, 2015 at 11:37:34AM -0600, Felipe Balbi wrote:
On Fri, Dec 26, 2014 at 01:28:20PM -0600, Felipe Balbi wrote:
STATUS register can be modified by the HW, so we
should bypass cache because of that.
In the case of INT[12] registers, they are the ones
that actually clear the
On Fri, Dec 26, 2014 at 01:28:20PM -0600, Felipe Balbi wrote:
STATUS register can be modified by the HW, so we
should bypass cache because of that.
In the case of INT[12] registers, they are the ones
that actually clear the IRQ source at the time they
are read. If we rely on the cache for
STATUS register can be modified by the HW, so we
should bypass cache because of that.
In the case of INT[12] registers, they are the ones
that actually clear the IRQ source at the time they
are read. If we rely on the cache for them, we will
never be able to clear the interrupt, which will cause
