Re: [PATCH v2 2/5] ARM: OMAP2+: DRA7: Add hwmod entries for PWMSS

2015-08-31 Thread Paul Walmsley
Hi On Thu, 16 Jul 2015, R, Vignesh wrote: > On 07/16/2015 03:24 AM, Paul Walmsley wrote: > > > > On Wed, 3 Jun 2015, Vignesh R wrote: > > > >> Add hwmod entries for the PWMSS on DRA7. > >> > >> Set l4_root_clk_div as the main_clk of PWMSS. It is fixed-factored clock > >> equal to L4PER2_L3_GICL

Re: [PATCH v2 2/5] ARM: OMAP2+: DRA7: Add hwmod entries for PWMSS

2015-07-28 Thread Vignesh R
On 07/23/2015 09:05 PM, R, Vignesh wrote: > > > On 7/16/2015 9:01 PM, R, Vignesh wrote: >> Hi, >> >> On 07/16/2015 03:24 AM, Paul Walmsley wrote: >>> Hi, >>> >>> some comments. >>> >>> On Wed, 3 Jun 2015, Vignesh R wrote: >>> Add hwmod entries for the PWMSS on DRA7. Set l4_root_c

Re: [PATCH v2 2/5] ARM: OMAP2+: DRA7: Add hwmod entries for PWMSS

2015-07-23 Thread R, Vignesh
On 7/16/2015 9:01 PM, R, Vignesh wrote: > Hi, > > On 07/16/2015 03:24 AM, Paul Walmsley wrote: >> Hi, >> >> some comments. >> >> On Wed, 3 Jun 2015, Vignesh R wrote: >> >>> Add hwmod entries for the PWMSS on DRA7. >>> >>> Set l4_root_clk_div as the main_clk of PWMSS. It is fixed-factored clock >

Re: [PATCH v2 2/5] ARM: OMAP2+: DRA7: Add hwmod entries for PWMSS

2015-07-16 Thread R, Vignesh
Hi, On 07/16/2015 03:24 AM, Paul Walmsley wrote: > Hi, > > some comments. > > On Wed, 3 Jun 2015, Vignesh R wrote: > >> Add hwmod entries for the PWMSS on DRA7. >> >> Set l4_root_clk_div as the main_clk of PWMSS. It is fixed-factored clock >> equal to L4PER2_L3_GICLK/2(l3_iclk_div/2). >> As per

Re: [PATCH v2 2/5] ARM: OMAP2+: DRA7: Add hwmod entries for PWMSS

2015-07-15 Thread Paul Walmsley
Hi, some comments. On Wed, 3 Jun 2015, Vignesh R wrote: > Add hwmod entries for the PWMSS on DRA7. > > Set l4_root_clk_div as the main_clk of PWMSS. It is fixed-factored clock > equal to L4PER2_L3_GICLK/2(l3_iclk_div/2). > As per AM57x TRM SPRUHZ6[1], October 2014, Section 29.1.3 Table 29-4, >

[PATCH v2 2/5] ARM: OMAP2+: DRA7: Add hwmod entries for PWMSS

2015-06-03 Thread Vignesh R
Add hwmod entries for the PWMSS on DRA7. Set l4_root_clk_div as the main_clk of PWMSS. It is fixed-factored clock equal to L4PER2_L3_GICLK/2(l3_iclk_div/2). As per AM57x TRM SPRUHZ6[1], October 2014, Section 29.1.3 Table 29-4, clock source to PWMSS is L4PER2_L3_GICLK. But it is actually L4PER2_L3_