Re: [PATCH v3 1/4] omap3: nand: prefetch in irq mode support

2010-08-02 Thread Tony Lindgren 
* Sukumar Ghorai s-gho...@ti.com [100713 07:39]:
 This patch enable prefetch-irq mode for NAND.

snip

 --- a/arch/arm/mach-omap2/board-flash.c
 +++ b/arch/arm/mach-omap2/board-flash.c
 @@ -133,6 +133,7 @@ static struct omap_nand_platform_data board_nand_data = {
   .nand_setup = NULL,
   .gpmc_t = nand_timings,
   .dma_channel= -1,   /* disable DMA in OMAP NAND driver */
 + .gpmc_irq   = GPMC_IRQ_NUMBER,
   .dev_ready  = NULL,
   .devsize= 0,/* '0' for 8-bit, '1' for 16-bit device */
  };
 --- a/arch/arm/mach-omap2/include/mach/board-flash.h
 +++ b/arch/arm/mach-omap2/include/mach/board-flash.h
 @@ -19,6 +19,9 @@
  #define PDC_ONENAND  3
  #define DBG_MPDB 4
  
 +/* Interrupt number to the MPU Subsystem for GPMC */
 +#define GPMC_IRQ_NUMBER  20
 +

This does not look right for the IRQ. Please add it to the irqs.h and 34xx,
then set it dynamically during the init just like we handle the other
interrupt numbers.

This is because the irq numbers can change between omaps, like irqs-44xx.h
already has

#define OMAP44XX_IRQ_GPMC   (20 + OMAP44XX_IRQ_GIC_START)

 @@ -130,6 +141,13 @@ struct omap_nand_info {
   unsigned long   phys_base;
   struct completion   comp;
   int dma_ch;
 + int gpmc_irq;
 + enum {
 + NAND_IO_READ = 0,   /* read */
 + NAND_IO_WRITE,  /* write */
 + } iomode;
 + u_char  *buf;
 + int buf_len;
  };

These should probably be OMAP_NAND_IO_READ and OMAP_NAND_IO_WRITE?

Regards,

Tony
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RE: [PATCH v3 1/4] omap3: nand: prefetch in irq mode support

2010-08-02 Thread Ghorai, Sukumar 


 -Original Message-
 From: Tony Lindgren [mailto:t...@atomide.com]
 Sent: Monday, August 02, 2010 6:33 PM
 To: Ghorai, Sukumar
 Cc: linux-omap@vger.kernel.org; linux-...@lists.infradead.org; linux-arm-
 ker...@lists.infradead.org; Vimal Singh
 Subject: Re: [PATCH v3 1/4] omap3: nand: prefetch in irq mode support
 
 * Sukumar Ghorai s-gho...@ti.com [100713 07:39]:
  This patch enable prefetch-irq mode for NAND.
 
 snip
 
  --- a/arch/arm/mach-omap2/board-flash.c
  +++ b/arch/arm/mach-omap2/board-flash.c
  @@ -133,6 +133,7 @@ static struct omap_nand_platform_data
 board_nand_data = {
  .nand_setup = NULL,
  .gpmc_t = nand_timings,
  .dma_channel= -1,   /* disable DMA in OMAP NAND driver */
  +   .gpmc_irq   = GPMC_IRQ_NUMBER,
  .dev_ready  = NULL,
  .devsize= 0,/* '0' for 8-bit, '1' for 16-bit device */
   };
  --- a/arch/arm/mach-omap2/include/mach/board-flash.h
  +++ b/arch/arm/mach-omap2/include/mach/board-flash.h
  @@ -19,6 +19,9 @@
   #define PDC_ONENAND3
   #define DBG_MPDB   4
 
  +/* Interrupt number to the MPU Subsystem for GPMC */
  +#define GPMC_IRQ_NUMBER20
  +
 
 This does not look right for the IRQ. Please add it to the irqs.h and 34xx,
 then set it dynamically during the init just like we handle the other
 interrupt numbers.
 
 This is because the irq numbers can change between omaps, like irqs-44xx.h
 already has
 
 #define OMAP44XX_IRQ_GPMC   (20 +
 OMAP44XX_IRQ_GIC_START)
 
  @@ -130,6 +141,13 @@ struct omap_nand_info {
  unsigned long   phys_base;
  struct completion   comp;
  int dma_ch;
  +   int gpmc_irq;
  +   enum {
  +   NAND_IO_READ = 0,   /* read */
  +   NAND_IO_WRITE,  /* write */
  +   } iomode;
  +   u_char  *buf;
  +   int buf_len;
   };
 
 These should probably be OMAP_NAND_IO_READ and OMAP_NAND_IO_WRITE?
[Ghorai] Thanks. I understand all your comments. I will rework and submit 
again. 

Regards,
Ghorai

 
 Regards,
 
 Tony
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[PATCH v3 1/4] omap3: nand: prefetch in irq mode support

2010-07-12 Thread Sukumar Ghorai 
This patch enable prefetch-irq mode for NAND.

Signed-off-by: Vimal Singh vimalsi...@ti.com
Signed-off-by: Sukumar Ghorai s-gho...@ti.com
---
 arch/arm/mach-omap2/board-flash.c  |1 +
 arch/arm/mach-omap2/gpmc.c |4 +
 arch/arm/mach-omap2/include/mach/board-flash.h |3 +
 arch/arm/plat-omap/include/plat/gpmc.h |4 +
 arch/arm/plat-omap/include/plat/nand.h |1 +
 drivers/mtd/nand/Kconfig   |   14 ++-
 drivers/mtd/nand/omap2.c   |  196 +++-
 7 files changed, 217 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-omap2/board-flash.c 
b/arch/arm/mach-omap2/board-flash.c
index ac834aa..c6a07dd 100644
--- a/arch/arm/mach-omap2/board-flash.c
+++ b/arch/arm/mach-omap2/board-flash.c
@@ -133,6 +133,7 @@ static struct omap_nand_platform_data board_nand_data = {
.nand_setup = NULL,
.gpmc_t = nand_timings,
.dma_channel= -1,   /* disable DMA in OMAP NAND driver */
+   .gpmc_irq   = GPMC_IRQ_NUMBER,
.dev_ready  = NULL,
.devsize= 0,/* '0' for 8-bit, '1' for 16-bit device */
 };
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index e301e7e..2c100e4 100755
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -487,6 +487,10 @@ int gpmc_cs_configure(int cs, int cmd, int wval)
u32 regval = 0;
 
switch (cmd) {
+   case GPMC_ENABLE_IRQ:
+   gpmc_write_reg(GPMC_IRQENABLE, wval);
+   break;
+
case GPMC_SET_IRQ_STATUS:
gpmc_write_reg(GPMC_IRQSTATUS, wval);
break;
diff --git a/arch/arm/mach-omap2/include/mach/board-flash.h 
b/arch/arm/mach-omap2/include/mach/board-flash.h
index b2242ae..37567a7 100644
--- a/arch/arm/mach-omap2/include/mach/board-flash.h
+++ b/arch/arm/mach-omap2/include/mach/board-flash.h
@@ -19,6 +19,9 @@
 #define PDC_ONENAND3
 #define DBG_MPDB   4
 
+/* Interrupt number to the MPU Subsystem for GPMC */
+#define GPMC_IRQ_NUMBER20
+
 struct flash_partitions {
struct mtd_partition *parts;
int nr_parts;
diff --git a/arch/arm/plat-omap/include/plat/gpmc.h 
b/arch/arm/plat-omap/include/plat/gpmc.h
index 9fd99b9..054e704 100644
--- a/arch/arm/plat-omap/include/plat/gpmc.h
+++ b/arch/arm/plat-omap/include/plat/gpmc.h
@@ -41,6 +41,8 @@
 #define GPMC_NAND_ADDRESS  0x000b
 #define GPMC_NAND_DATA 0x000c
 
+#define GPMC_ENABLE_IRQ0x000d
+
 /* ECC commands */
 #define GPMC_ECC_READ  0 /* Reset Hardware ECC for read */
 #define GPMC_ECC_WRITE 1 /* Reset Hardware ECC for write */
@@ -78,6 +80,8 @@
 #define WR_RD_PIN_MONITORING   0x0060
 #define GPMC_PREFETCH_STATUS_FIFO_CNT(val) ((val  24)  0x7F)
 #define GPMC_PREFETCH_STATUS_COUNT(val)(val  0x3fff)
+#define GPMC_IRQ_FIFOEVENTENABLE   0x01
+#define GPMC_IRQ_COUNT_EVENT   0x02
 
 /*
  * Note that all values in this struct are in nanoseconds, while
diff --git a/arch/arm/plat-omap/include/plat/nand.h 
b/arch/arm/plat-omap/include/plat/nand.h
index 6562cd0..5e69463 100644
--- a/arch/arm/plat-omap/include/plat/nand.h
+++ b/arch/arm/plat-omap/include/plat/nand.h
@@ -20,6 +20,7 @@ struct omap_nand_platform_data {
int (*nand_setup)(void);
int (*dev_ready)(struct omap_nand_platform_data *);
int dma_channel;
+   int gpmc_irq;
unsigned long   phys_base;
int devsize;
 };
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index ffc3720..46361ef 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -112,6 +112,9 @@ config MTD_NAND_OMAP_PREFETCH
help
 The NAND device can be accessed for Read/Write using GPMC PREFETCH 
engine
 to improve the performance.
+GPMC PREFETCH can be configured eigther in MPU interrupt mode or in DMA
+interrupt mode. If not selected any of them prefetch will be used in
+polling mode.
 
 config MTD_NAND_OMAP_PREFETCH_DMA
depends on MTD_NAND_OMAP_PREFETCH
@@ -120,7 +123,16 @@ config MTD_NAND_OMAP_PREFETCH_DMA
help
 The GPMC PREFETCH engine can be configured eigther in MPU interrupt 
mode
 or in DMA interrupt mode.
-Say y for DMA mode or MPU mode will be used
+Say y for DMA mode
+
+config MTD_NAND_OMAP_PREFETCH_IRQ
+   depends on MTD_NAND_OMAP_PREFETCH  !MTD_NAND_OMAP_PREFETCH_DMA
+   bool IRQ mode
+   default n
+   help
+The GPMC PREFETCH engine can be configured eigther in MPU interrupt 
mode
+or in DMA interrupt mode.
+Say y for IRQ mode
 
 config MTD_NAND_IDS
tristate
diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c
index 133d515..6a57743 100644
---