* Vignesh R [151209 21:05]:
>
>
> On 12/03/2015 03:51 PM, Vignesh R wrote:
> >
> >
> > On 12/01/2015 10:09 PM, Tony Lindgren wrote:
> >> * Vignesh R [151130 20:46]:
> >>> On 12/01/2015 04:04 AM, Tony Lindgren wrote:
>
> ...
> >>
> >> OK. They are both
On 12/03/2015 03:51 PM, Vignesh R wrote:
>
>
> On 12/01/2015 10:09 PM, Tony Lindgren wrote:
>> * Vignesh R [151130 20:46]:
>>> On 12/01/2015 04:04 AM, Tony Lindgren wrote:
...
>>
>> OK. They are both on L3 main so that won't cause any issues for separate
>> interconnect
On 12/01/2015 10:09 PM, Tony Lindgren wrote:
> * Vignesh R [151130 20:46]:
>> On 12/01/2015 04:04 AM, Tony Lindgren wrote:
>>>
>>> Actually none of the IO areas above are within the same interconnect target:
>>>
>>> 0x4b30 QSPI0 address space in L3 main interconnect
>>>
* Vignesh R [151130 20:46]:
> On 12/01/2015 04:04 AM, Tony Lindgren wrote:
> >
> > Actually none of the IO areas above are within the same interconnect target:
> >
> > 0x4b30 QSPI0 address space in L3 main interconnect
> > 0x5c00 QSPI1 address space in L3 main
* Vignesh R [151129 21:16]:
> Add qspi memory mapped region entries for DRA7xx based SoCs. Also,
> update the binding documents for the controller to document this change.
>
> Acked-by: Rob Herring
> Signed-off-by: Vignesh R
> ---
>
> v4: No
* Tony Lindgren [151130 14:03]:
> * Vignesh R [151129 21:16]:
> > Add qspi memory mapped region entries for DRA7xx based SoCs. Also,
> > update the binding documents for the controller to document this change.
> >
> > Acked-by: Rob Herring
>
* Vignesh R [151129 21:16]:
> Add qspi memory mapped region entries for DRA7xx based SoCs. Also,
> update the binding documents for the controller to document this change.
>
> Acked-by: Rob Herring
> Signed-off-by: Vignesh R
...
> ---
On 12/01/2015 04:04 AM, Tony Lindgren wrote:
> * Vignesh R [151129 21:16]:
>> Add qspi memory mapped region entries for DRA7xx based SoCs. Also,
>> update the binding documents for the controller to document this change.
>>
>> Acked-by: Rob Herring
>>
Add qspi memory mapped region entries for DRA7xx based SoCs. Also,
update the binding documents for the controller to document this change.
Acked-by: Rob Herring
Signed-off-by: Vignesh R
---
v4: No changes.
Documentation/devicetree/bindings/spi/ti_qspi.txt |