Hello Vishwanath,
some more comments:
On Thu, 7 Jan 2010, Vishwanath BS wrote:
In 3630, DPLL4M2 o/p can be 96MH or 192MHz (for SGX to run at 192). This
patch has changes to support this feature. 96MHz clock is generated by
dividing 192Mhz clock by 2 using CM_CLKSEL_CORE register.
SGX can
In 3630, DPLL4M2 o/p can be 96MH or 192MHz (for SGX to run at 192). This
patch has changes to support this feature. 96MHz clock is generated by
dividing 192Mhz clock by 2 using CM_CLKSEL_CORE register.
SGX can select Core Clock, 192MHz clock or CM_96M_FCLK as it's
functional clock. In summary
