Quoting Tomi Valkeinen (2015-05-06 03:08:58)
DESHDCP clock is needed on DRA7 based SoCs to enable the DSS IP. That
clock is an odd one, as it is not supposed to be any kind of core clock
for DSS, and we don't even support HDCP, but the clock is still needed
even for the HWMOD framework to be
On 05/28, Tero Kristo wrote:
On 05/28/2015 07:22 AM, Michael Turquette wrote:
Just chiming in on the critical clock discussion. I'm not planning to
merge something that lets Devicetree nodes call clk_enable on a clock.
That's what drivers are for.
The assigned-rate and assigned-parent stuff
On 05/28/2015 07:22 AM, Michael Turquette wrote:
Quoting Stephen Boyd (2015-05-20 12:34:23)
On 05/20/15 04:50, Tero Kristo wrote:
@@ -348,5 +348,10 @@ int __init dra7xx_dt_clk_init(void)
if (rc)
pr_err(%s: failed to set USB_DPLL M2 OUT\n, __func__);
+hdcp_ck =
On 20/05/15 14:47, Tero Kristo wrote:
On 05/06/2015 01:08 PM, Tomi Valkeinen wrote:
DESHDCP clock is needed on DRA7 based SoCs to enable the DSS IP. That
clock is an odd one, as it is not supposed to be any kind of core clock
for DSS, and we don't even support HDCP, but the clock is still
Quoting Stephen Boyd (2015-05-20 12:34:23)
On 05/20/15 04:50, Tero Kristo wrote:
@@ -348,5 +348,10 @@ int __init dra7xx_dt_clk_init(void)
if (rc)
pr_err(%s: failed to set USB_DPLL M2 OUT\n, __func__);
+hdcp_ck = clk_get_sys(NULL, dss_deshdcp_clk);
+rc =
On 21/05/15 06:06, Paul Walmsley wrote:
Enable falls under the critical clocks discussion that is ongoing. I
assume that this is some sort of critical clock that can't be turned off?
It only needs to be enabled for this particular display IP subsystem to
function:
On 05/20/2015 02:47 PM, Tero Kristo wrote:
On 05/06/2015 01:08 PM, Tomi Valkeinen wrote:
DESHDCP clock is needed on DRA7 based SoCs to enable the DSS IP. That
clock is an odd one, as it is not supposed to be any kind of core clock
for DSS, and we don't even support HDCP, but the clock is still
On 05/20/15 04:50, Tero Kristo wrote:
@@ -348,5 +348,10 @@ int __init dra7xx_dt_clk_init(void)
if (rc)
pr_err(%s: failed to set USB_DPLL M2 OUT\n, __func__);
+hdcp_ck = clk_get_sys(NULL, dss_deshdcp_clk);
+rc = clk_prepare_enable(hdcp_ck);
+if (rc)
+
On Wed, 20 May 2015, Stephen Boyd wrote:
On 05/20/15 04:50, Tero Kristo wrote:
@@ -348,5 +348,10 @@ int __init dra7xx_dt_clk_init(void)
if (rc)
pr_err(%s: failed to set USB_DPLL M2 OUT\n, __func__);
+hdcp_ck = clk_get_sys(NULL, dss_deshdcp_clk);
+rc =
DESHDCP clock is needed on DRA7 based SoCs to enable the DSS IP. That
clock is an odd one, as it is not supposed to be any kind of core clock
for DSS, and we don't even support HDCP, but the clock is still needed
even for the HWMOD framework to be able to reset the DSS IP.
As there's no support
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