Hello,
A quick update on the CORE DPLL M2 divider change patches; they seem to
work okay on the BeagleBoard here. (The rate tables need minor tweaks to
match the Beagle DPLL clock rates set up by u-boot.)
Not sure what's going on with the 3430SDP. I suspect there are some PRCM
register
On Tue, 8 Jul 2008, Rajendra Nayak wrote:
From: Paul Walmsley [mailto:[EMAIL PROTECTED]
A few notes:
- The M2 divider switch does not seem to work consistently on the
3430SDP I use to test. In particular, the switch back to
M2=1 results
in a hung console.
SRAM being
Hi Paul,
SRAM being mapped as cacheable could be a possible reason for this.
Second this.
Certainly possible, and that change needs to be included. But why
would
it only happen on the M2 2 - 1 transition?
Can you ping the board by chance when you are locked? Is only user space
locked
On Tue, 8 Jul 2008, Woodruff, Richard wrote:
SRAM being mapped as cacheable could be a possible reason for this.
Second this.
Yeah, agreed that it needs to be done, but SRAM in CDP 12.17 is still
marked cacheable too, right? Did CORE M2 divider changes work in CDP
12.17?
Also still
SRAM being mapped as cacheable could be a possible reason for
this.
Second this.
Yeah, agreed that it needs to be done, but SRAM in CDP 12.17 is still
marked cacheable too, right? Did CORE M2 divider changes work in CDP
12.17?
No CDP has it marked strongly order for a while now.
Hello Richard,
On Tue, 8 Jul 2008, Woodruff, Richard wrote:
If say your I2C failed to raise the voltage or you didn't program in
enough setup time into volt control you might try and go fast with out
having proper voltage yet.
Thanks for the ideas. Unfortunately, no access to an SDP with
-Original Message-
From: Paul Walmsley [mailto:[EMAIL PROTECTED]
Sent: Wednesday, July 09, 2008 5:17 AM
To: Woodruff, Richard
Cc: Nayak, Rajendra; linux-omap@vger.kernel.org; 'Igor Stoppa'
Subject: RE: [PATCH 0/9] OMAP2/3 SDRC/clock: control CORE M2
divider, clean up SDRC
