Add the omap3_core_dpll_m2_set_rate() function to the OMAP3 clock code,
which calls into the SRAM function omap3_sram_configure_core_dpll() to
change the CORE DPLL M2 divider. (SRAM code is necessary since rate changes
on clocks upstream from the SDRC can glitch SDRAM accesses.)
Use this
By the way, this last patch will need to be hand-edited to
remove the following part to apply cleanly on mainline. I'll post a
refreshed series later for merging.
- Paul
On Mon, 7 Jul 2008, Paul Walmsley wrote:
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
