On Thu, Jul 19, 2012 at 04:59:06PM -0600, Paul Walmsley wrote:
+ Ilya
Hi Mark
Maybe try something like this on top of the patch that disables the
MPU DPLL autoidle?
I don't know what am35xx_enable_emac_int() is supposed to do. It seems
strange to clear the interrupt status bits when
On Wed, Jul 18, 2012 at 05:25:16PM -0600, Paul Walmsley wrote:
On Wed, 18 Jul 2012, Mark A. Greer wrote:
On Tue, Jul 17, 2012 at 09:54:53PM -0600, Paul Walmsley wrote:
Want to try something like this? It's your patch but modified to not use
disable/enable_hlt(). If it doesn't work
On Thu, 19 Jul 2012, Mark A. Greer wrote:
...and, unfortunately, it didnt' work in either case.
OK thanks for the tests. Is the EMAC/MDIO really active and asserting
interrupts while all this is happening? Or has that driver called
pm_runtime_put*(), and so the EMAC/MDIO isn't waking up?
On Thu, Jul 19, 2012 at 01:19:13PM -0600, Paul Walmsley wrote:
On Thu, 19 Jul 2012, Mark A. Greer wrote:
...and, unfortunately, it didnt' work in either case.
OK thanks for the tests. Is the EMAC/MDIO really active and asserting
interrupts while all this is happening?
I should be
+ Ilya
Hi Mark
Maybe try something like this on top of the patch that disables the
MPU DPLL autoidle?
I don't know what am35xx_enable_emac_int() is supposed to do. It seems
strange to clear the interrupt status bits when one is supposed to enable
the interrupts. Maybe Ilya can shed some
On Tue, Jul 17, 2012 at 09:54:53PM -0600, Paul Walmsley wrote:
Hi
Hi Paul.
From the patch description, it doesn't sound like it's WFI entry that's
the problem. The EMAC can assert its interrupt lines to the INTC, since
the EMAC is active. If the MPU and CORE powerdomains are ON, then the
On Wed, 18 Jul 2012, Mark A. Greer wrote:
On Tue, Jul 17, 2012 at 09:54:53PM -0600, Paul Walmsley wrote:
Want to try something like this? It's your patch but modified to not use
disable/enable_hlt(). If it doesn't work in your test case, maybe
try uncommenting that second set of
Hi
just a quick comment on this one.
On Fri, 11 May 2012, Mark A. Greer wrote:
From: Mark A. Greer mgr...@animalcreek.com
The am35x family of SoCs has a Davinci EMAC ethernet
controller on-chip. Unfortunately, the EMAC is unable
to wake the PRCM when there is network activity which
On 05/15/12 00:32, Kevin Hilman wrote:
Mark A. Greer mgr...@animalcreek.com writes:
On Mon, May 14, 2012 at 11:20:58AM +0300, Igor Grinberg wrote:
Hi Mark,
Hi Igor.
Thanks for the great work!
On 05/12/12 00:12, Mark A. Greer wrote:
From: Mark A. Greer mgr...@animalcreek.com
The am35x
On Tue, May 15, 2012 at 03:42:09PM +0300, Igor Grinberg wrote:
On 05/15/12 00:32, Kevin Hilman wrote:
Mark A. Greer mgr...@animalcreek.com writes:
On Mon, May 14, 2012 at 11:20:58AM +0300, Igor Grinberg wrote:
Hi Mark,
Hi Igor.
Thanks for the great work!
On 05/12/12 00:12,
Hi Mark,
Thanks for the great work!
On 05/12/12 00:12, Mark A. Greer wrote:
From: Mark A. Greer mgr...@animalcreek.com
The am35x family of SoCs has a Davinci EMAC ethernet
controller on-chip. Unfortunately, the EMAC is unable
to wake the PRCM when there is network activity which
leads to
On Mon, May 14, 2012 at 11:20:58AM +0300, Igor Grinberg wrote:
Hi Mark,
Hi Igor.
Thanks for the great work!
On 05/12/12 00:12, Mark A. Greer wrote:
From: Mark A. Greer mgr...@animalcreek.com
The am35x family of SoCs has a Davinci EMAC ethernet
controller on-chip. Unfortunately,
Mark A. Greer mgr...@animalcreek.com writes:
On Mon, May 14, 2012 at 11:20:58AM +0300, Igor Grinberg wrote:
Hi Mark,
Hi Igor.
Thanks for the great work!
On 05/12/12 00:12, Mark A. Greer wrote:
From: Mark A. Greer mgr...@animalcreek.com
The am35x family of SoCs has a Davinci EMAC
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