On 10/8/06, Neil Brown [EMAIL PROTECTED] wrote:
On Monday September 11, [EMAIL PROTECTED] wrote:
Neil,
The following patches implement hardware accelerated raid5 for the Intel
Xscale(r) series of I/O Processors. The MD changes allow stripe
operations to run outside the spin lock in a
On 9/14/06, Jakob Oestergaard [EMAIL PROTECTED] wrote:
On Wed, Sep 13, 2006 at 12:17:55PM -0700, Dan Williams wrote:
...
Out of curiosity; how does accelerated compare to non-accelerated?
One quick example:
4-disk SATA array rebuild on iop321 without acceleration - 'top'
reports md0_resync
On Monday September 11, [EMAIL PROTECTED] wrote:
Neil,
The following patches implement hardware accelerated raid5 for the Intel
Xscale® series of I/O Processors. The MD changes allow stripe
operations to run outside the spin lock in a work queue. Hardware
acceleration is achieved by
On Wed, Sep 13, 2006 at 12:17:55PM -0700, Dan Williams wrote:
...
Out of curiosity; how does accelerated compare to non-accelerated?
One quick example:
4-disk SATA array rebuild on iop321 without acceleration - 'top'
reports md0_resync and md0_raid5 dueling for the CPU each at ~50%
On Mon, Sep 11, 2006 at 04:00:32PM -0700, Dan Williams wrote:
Neil,
...
Concerning the context switching performance concerns raised at the
previous release, I have observed the following. For the hardware
accelerated case it appears that performance is always better with the
work queue
On 9/13/06, Jakob Oestergaard [EMAIL PROTECTED] wrote:
On Mon, Sep 11, 2006 at 04:00:32PM -0700, Dan Williams wrote:
Neil,
...
Concerning the context switching performance concerns raised at the
previous release, I have observed the following. For the hardware
accelerated case it appears
Dan Williams wrote:
On 9/11/06, Jeff Garzik [EMAIL PROTECTED] wrote:
Dan Williams wrote:
This is a frequently asked question, Alan Cox had the same one at OLS.
The answer is probably. The only complication I currently see is
where/how the stripe cache is maintained. With the IOPs its easy
Neil,
The following patches implement hardware accelerated raid5 for the Intel
Xscale® series of I/O Processors. The MD changes allow stripe
operations to run outside the spin lock in a work queue. Hardware
acceleration is achieved by using a dma-engine-aware work queue routine
instead of the
Dan Williams wrote:
Neil,
The following patches implement hardware accelerated raid5 for the Intel
Xscale® series of I/O Processors. The MD changes allow stripe
operations to run outside the spin lock in a work queue. Hardware
acceleration is achieved by using a dma-engine-aware work queue
On 9/11/06, Jeff Garzik [EMAIL PROTECTED] wrote:
Dan Williams wrote:
Neil,
The following patches implement hardware accelerated raid5 for the Intel
Xscale(r) series of I/O Processors. The MD changes allow stripe
operations to run outside the spin lock in a work queue. Hardware
Dan Williams wrote:
This is a frequently asked question, Alan Cox had the same one at OLS.
The answer is probably. The only complication I currently see is
where/how the stripe cache is maintained. With the IOPs its easy
because the DMA engines operate directly on kernel memory. With the
On 9/11/06, Jeff Garzik [EMAIL PROTECTED] wrote:
Dan Williams wrote:
This is a frequently asked question, Alan Cox had the same one at OLS.
The answer is probably. The only complication I currently see is
where/how the stripe cache is maintained. With the IOPs its easy
because the DMA
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