Re: [PATCH RFC 1/2] IB/core: Introduce Fast Indirect Memory Registration verbs API

2014-10-13 Thread Sagi Grimberg
On 10/8/2014 4:54 PM, Steve Wise wrote: @@ -1056,6 +1067,14 @@ struct ib_send_wr { intaccess_flags; struct ib_sge *prot; } sig_handover; +struct { +u64iova_start; +struct

Re: [PATCH RFC 0/2] Indirect Fast Memory registration support

2014-10-13 Thread Sagi Grimberg
On 10/8/2014 2:06 PM, Devesh Sharma wrote: -Original Message- From: linux-rdma-ow...@vger.kernel.org [mailto:linux-rdma- ow...@vger.kernel.org] On Behalf Of Sagi Grimberg Sent: Tuesday, October 07, 2014 8:18 PM To: linux-rdma@vger.kernel.org Cc: bvanass...@acm.org; rol...@kernel.org;

Re: [PATCH RFC 1/2] IB/core: Introduce Fast Indirect Memory Registration verbs API

2014-10-13 Thread Sagi Grimberg
On 10/9/2014 11:13 PM, Or Gerlitz wrote: On Tue, Oct 7, 2014, Sagi Grimberg sa...@mellanox.com wrote: [...] enum ib_signature_prot_cap { @@ -182,6 +183,7 @@ struct ib_device_attr { int max_srq_wr; int max_srq_sge; unsigned int

Re: [PATCH 1/1] IB/iser: Remove hard coded values for cqe and send_wr

2014-10-13 Thread Sagi Grimberg
On 10/9/2014 8:14 AM, Jayamohan.K wrote: SNIP Hi Minh and Jayamohan, So I agree that we would want to take device capabilities into account here, but we need to be able to adjust scsi_cmds_max (can_queue) in case the max wqe supported is lower than scsi_cmds_max *

Re: [PATCH 8/8] IB/srp: Add multichannel support

2014-10-13 Thread Sagi Grimberg
On 10/7/2014 3:51 PM, Bart Van Assche wrote: On 09/23/14 18:32, Sagi Grimberg wrote: Since you don't seem to negotiate/declare multichannel with the target, did you test this code with some target implementations other than SCST that happen to be out there? (replying to an e-mail of two weeks

Re: [PATCH RFC 1/2] IB/core: Introduce Fast Indirect Memory Registration verbs API

2014-10-13 Thread Sagi Grimberg
On 10/9/2014 11:13 PM, Or Gerlitz wrote: On Tue, Oct 7, 2014, Sagi Grimberg sa...@mellanox.com wrote: [...] enum ib_signature_prot_cap { @@ -182,6 +183,7 @@ struct ib_device_attr { int max_srq_wr; int max_srq_sge; unsigned int

Re: [PATCH RFC 2/2] IB/mlx5: Implement Fast Indirect Memory Registration Feature

2014-10-13 Thread Sagi Grimberg
On 10/12/2014 10:39 PM, Or Gerlitz wrote: On 10/7/2014 4:48 PM, Sagi Grimberg wrote: * Nit change in mr_align() static routine to handle void* instead of __be64. nit comment... any reason not to put in different and unrelated to this series patch? I can, But there is no use for this out

Re: [PATCH 1/3] s390/kernel: add system calls for access PCI memory

2014-10-13 Thread Martin Schwidefsky
On Sun, 12 Oct 2014 11:52:55 + Shachar Raindel rain...@mellanox.com wrote: + switch (length) { + case 1: + ret = get_user(value.buf8, ((u8 *)user_buffer)); This cast (and similar casts across the code) kills the __user annotation of the user buffer pointer. First -

Re: [PATCH RFC 0/2] Indirect Fast Memory registration support

2014-10-13 Thread Bart Van Assche
On 10/12/14 21:43, Or Gerlitz wrote: Sean, Bart - any comment on the API before Sagi sits down to code the iSER changes? Hello Or, Will this API ever be supported by other Mellanox RDMA drivers than mlx5, e.g. mlx4 ? Will this API ever be supported by a Mellanox HCA that supports RoCE ?

Re: [PATCH 8/8] IB/srp: Add multichannel support

2014-10-13 Thread Bart Van Assche
On 10/13/14 10:17, Sagi Grimberg wrote: On 10/7/2014 3:51 PM, Bart Van Assche wrote: On 09/23/14 18:32, Sagi Grimberg wrote: Since you don't seem to negotiate/declare multichannel with the target, did you test this code with some target implementations other than SCST that happen to be out

Re: [PATCH v2 02/12] blk-mq: Add blk_mq_unique_tag()

2014-10-13 Thread Bart Van Assche
On 10/11/14 13:08, Christoph Hellwig wrote: +static inline u32 blk_mq_build_unique_tag(int hwq, int tag) +{ + return (hwq BLK_MQ_UNIQUE_TAG_BITS) | (tag BLK_MQ_UNIQUE_TAG_MASK); +} Is there any value in having this as a separate helper? Hello Christoph, With the approach for block

Re: [PATCH v2 01/12] blk-mq: Use all available hardware queues

2014-10-13 Thread Bart Van Assche
On 10/11/14 13:11, Christoph Hellwig wrote: On Wed, Oct 08, 2014 at 03:21:56PM +0200, Bart Van Assche wrote: On 10/07/14 16:37, Jens Axboe wrote: Lets do this separate, as explained last time, it needs to be evaluated on its own and doesn't really belong in this series of patches. Hello

Re: [PATCH v2 02/12] blk-mq: Add blk_mq_unique_tag()

2014-10-13 Thread Christoph Hellwig
On Mon, Oct 13, 2014 at 11:21:54AM +0200, Bart Van Assche wrote: With the approach for block layer tag management proposed in this patch series SCSI LLDs no longer need to call this function. This means that the blk_mq_build_unique_tag() function can be eliminated by inlining it into

Re: [PATCH V1 for-next 1/9] IB/core: Introduce peer client interface

2014-10-13 Thread Bart Van Assche
On 10/12/14 14:03, Shachar Raindel wrote: The kernel-doc output for the above comment block is incomplete. Please fix this, and please also fix the warnings reported by the kernel-doc We are not sure what is the best way to document an operations struct using nanodocs. Looking at

Re: [PATCH RFC 0/2] Indirect Fast Memory registration support

2014-10-13 Thread Sagi Grimberg
On 10/13/2014 11:48 AM, Bart Van Assche wrote: On 10/12/14 21:43, Or Gerlitz wrote: Sean, Bart - any comment on the API before Sagi sits down to code the iSER changes? Hello Or, Hey Bart, Will this API ever be supported by other Mellanox RDMA drivers than mlx5, e.g. mlx4 ? Well,

Re: [PATCH RFC 2/2] IB/mlx5: Implement Fast Indirect Memory Registration Feature

2014-10-13 Thread Or Gerlitz
On 10/13/2014 11:32 AM, Sagi Grimberg wrote: mask = MLX5_MKEY_MASK_LEN| +MLX5_MKEY_MASK_PAGE_SIZE| +MLX5_MKEY_MASK_START_ADDR| +MLX5_MKEY_MASK_EN_RINVAL| +MLX5_MKEY_MASK_KEY| +MLX5_MKEY_MASK_LR| +

Re: [PATCH RFC 2/2] IB/mlx5: Implement Fast Indirect Memory Registration Feature

2014-10-13 Thread Or Gerlitz
On 10/13/2014 11:32 AM, Sagi Grimberg wrote: n 10/12/2014 10:39 PM, Or Gerlitz wrote: On 10/7/2014 4:48 PM, Sagi Grimberg wrote: * Nit change in mr_align() static routine to handle void* instead of __be64. nit comment... any reason not to put in different and unrelated to this series

RE: [PATCH RFC 1/2] IB/core: Introduce Fast Indirect Memory Registration verbs API

2014-10-13 Thread Steve Wise
On 10/8/2014 4:54 PM, Steve Wise wrote: @@ -1056,6 +1067,14 @@ struct ib_send_wr { intaccess_flags; struct ib_sge *prot; } sig_handover; +struct { +u64iova_start; +struct

Re: [PATCH RFC 0/2] Indirect Fast Memory registration support

2014-10-13 Thread Steve Wise
On 10/13/2014 6:18 AM, Sagi Grimberg wrote: On 10/13/2014 11:48 AM, Bart Van Assche wrote: On 10/12/14 21:43, Or Gerlitz wrote: Sean, Bart - any comment on the API before Sagi sits down to code the iSER changes? Hello Or, Hey Bart, Will this API ever be supported by other Mellanox RDMA

[PATCH 1/3] RDMA/core: Enable the iWarp Port Mapper to provide the actual address of the remote connecting peer

2014-10-13 Thread Tatyana Nikolova
Add functionality to allow the port mapper to provide to its client the actual (non-mapped) ip/tcp address information of the remote connecting peer Signed-off-by: Tatyana Nikolova tatyana.e.nikol...@intel.com Reviewed-by: Steve Wise sw...@opengridcomputing.com ---

[PATCH 2/3] RDMA/nes: Report the actual address of the remote connecting peer

2014-10-13 Thread Tatyana Nikolova
Get the actual (non-mapped) ip/tcp address of the remote connecting peer from the port mapper and report the address info to the user space application at the time of connection establishment Signed-off-by: Tatyana Nikolova tatyana.e.nikol...@intel.com --- drivers/infiniband/hw/nes/nes.c|

[PATCH 3/3] RDMA/cxgb4: Report the actual address of the remote connecting peer

2014-10-13 Thread Tatyana Nikolova
From: Steve Wise sw...@opengridcomputing.com When iWARP port mapping is being done, the passive side of a connection only knows the mapped address/port of the peer. So now query the IWPM to get the actual address/port of the peer. Also setup the passive side endpoint to correctly display the

Re: [PATCH 1/1] IB/iser: Remove hard coded values for cqe and send_wr

2014-10-13 Thread Jayamohan Kallickal
On Tue, Oct 7, 2014 at 10:58 PM, Sagi Grimberg sa...@dev.mellanox.co.il wrote: On 10/8/2014 3:41 AM, Jay Kallickal wrote: From: Jayamohan Kallickal jayamoh...@gmail.com This patch allows the underlying hardware to choose values other than hard coded max values for cqe and send_wr while

Re: [PATCH RFC 1/2] IB/core: Introduce Fast Indirect Memory Registration verbs API

2014-10-13 Thread Bart Van Assche
On 10/07/14 16:48, Sagi Grimberg wrote: In order to support that we provide the user with an interface to pass a scattered list of buffers to the IB core layer called ib_indir_reg_list and provide the a new send work request opcode called IB_WR_REG_INDIR_MR. We extend wr union with a new type of

Re: [PATCH RFC 2/2] IB/mlx5: Implement Fast Indirect Memory Registration Feature

2014-10-13 Thread Bart Van Assche
On 10/07/14 16:48, Sagi Grimberg wrote: -static __be64 *mr_align(__be64 *ptr, int align) +static void *mr_align(void *ptr, int align) { unsigned long mask = align - 1; - return (__be64 *)(((unsigned long)ptr + mask) ~mask); + return (void *)(((unsigned long)ptr + mask)