From: Dean Luick <dean.lu...@intel.com>
Correctly reduce the number of VLs when limited by the number
of SDMA engines.
The hardware has multiple egress mechanisms, SDMA and pio, and multiples
of those. These mechanisms are chosen using the VL (8)
The fix corrects a panic issue with one of the platforms that doesn't have
enough SDMA (4) mechanisms for the typical number of VLs.
Reviewed-by: Mike Marciniszyn <mike.marcinis...@intel.com>
Signed-off-by: Dean Luick <dean.lu...@intel.com>
Signed-off-by: Jubin John <jubin.j...@intel.com>
---
Changes in v2:
- Added more information in commit message
drivers/staging/rdma/hfi1/chip.c | 6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/staging/rdma/hfi1/chip.c b/drivers/staging/rdma/hfi1/chip.c
index d9bb389..d17fd29 100644
--- a/drivers/staging/rdma/hfi1/chip.c
+++ b/drivers/staging/rdma/hfi1/chip.c
@@ -10610,9 +10610,9 @@ struct hfi1_devdata *hfi1_init_dd(struct pci_dev *pdev,
/* insure num_vls isn't larger than number of sdma engines */
if (HFI1_CAP_IS_KSET(SDMA) && num_vls > dd->chip_sdma_engines) {
dd_dev_err(dd, "num_vls %u too large, using %u VLs\n",
- num_vls, HFI1_MAX_VLS_SUPPORTED);
- ppd->vls_supported = num_vls = HFI1_MAX_VLS_SUPPORTED;
- ppd->vls_operational = ppd->vls_supported;
+ num_vls, dd->chip_sdma_engines);
+ num_vls = dd->chip_sdma_engines;
+ ppd->vls_supported = dd->chip_sdma_engines;
}
/*
--
1.7.1
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