[PATCH v2 2/2] clk: renesas: cpg-mssr: add R8A7745 support

Add RZ/G1E (R8A7745) Clock Pulse Generator / Module Standby and Software Reset support, using the CPG/MSSR driver core and the common R-Car Gen2 (and RZ/G) code. Based on the proof-of-concept R8A7791 CPG/MSSR patch by Geert Uytterhoeven . Signed-off-by: Sergei Shtylyov --- Changes in version 2

[PATCH v2 1/2] ARM: shmobile: r8a7745: add CPG clock index macros

Add macros usable by the device tree sources to reference the R8A7745 CPG clocks by index. The data comes from the table 7.2c in the revision 0.50 of the RZ/G Series User's Manual. Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven --- Changes in version 2: - added Geert's tag.

[PATCH v2 0/2] Renesas R8A7745 CPG/MSSR clock support

Hello. Here's the set of 2 patches against the 'clk-next' branch of CLK group's 'linux.git' repo plus the R8A7743 CPG/MSSR patches just re-posted. They also depend on the common R-Car Gen2 support patch. As the DT patches in the R8A7745/SK-RZG1E board support series depend on the patch #1 of th

[PATCH v2] ARM: DTS: r8a7794: alt: Fix PFC names for DU

Update the PFC pin groups and function names of DU interface for r8a7794 ALT board. The currently specified pin groups and function names prevented PFC and DU interfaces from being correctly configured: sh-pfc e606.pin-controller: function 'du' not supported sh-pfc e606.pin-controller: in

[PATCH v3 RESEND] clk: renesas: cpg-mssr: add common R-Car Gen2 support

Add the common R-Car Gen2 (and RZ/G) Clock Pulse Generator / Module Standby and Software Reset support code, using the CPG/MSSR driver core. Based on the proof-of-concept R8A7791 CPG/MSSR patch by Geert Uytterhoeven . Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven --- This pa

Re: [RFC 5/5] doc_rst: media: New SDR formats SC16, SC18 & SC20

Hello On 11/02/2016 10:58 PM, Laurent Pinchart wrote: Hi Ramesh, On Wednesday 02 Nov 2016 09:00:00 Ramesh Shanmugasundaram wrote: Hi Laurent, Any further thoughts on the SDR format please (especially the comment below). I would appreciate your feedback. On Wednesday 12 Oct 2016 15:10:29 Ram

Re: [PATCH 2/2] pinctrl: sh-pfc: r8a7795: Use lookup function for bias data

Hi Laurent, On 2016-11-03 19:10:06 +0200, Laurent Pinchart wrote: > Hi Niklas, > > Thank you for thr patch. Thanks for your feedback. > > On Thursday 03 Nov 2016 16:34:21 Niklas Söderlund wrote: > > There is a bug in the r8a7795 bias code where a WARN() is trigged > > anytime a pin from PUEN0/

[PATCH 7/9] arm64: dts: m3ulcb: enable EXTALR clk

This enables EXTALR clock that can be used for the watchdog. Signed-off-by: Vladimir Barinov --- arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts | 4 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts

[PATCH 8/9] arm64: dts: m3ulcb: enable WDT

This supports watchdog timer for M3ULCB board Signed-off-by: Vladimir Barinov --- arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts | 5 + 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts index 6936288

[PATCH 9/9] arm64: dts: m3ulcb: enable SDHI2

This supports SDHI2 for M3ULCB onboard eMMC Signed-off-by: Vladimir Barinov --- arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts | 43 ++ 1 file changed, 43 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7796-m3u

[PATCH 6/9] arm64: dts: m3ulcb: enable SDHI0

This supports SDHI0 on M3ULCB board SD card slot Signed-off-by: Vladimir Barinov --- arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts | 48 ++ 1 file changed, 48 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a779

[PATCH 4/9] arm64: dts: m3ulcb: enable GPIO leds

This supports GPIO leds on M3ULCB board Signed-off-by: Vladimir Barinov --- arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts | 13 + 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts index fb6

[PATCH 5/9] arm64: dts: m3ulcb: enable GPIO keys

This supports GPIO keys on M3ULCB board Signed-off-by: Vladimir Barinov --- arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts | 14 + 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts index fb6

[PATCH 2/9] arm64: dts: m3ulcb: initial device tree

Add the initial device tree for the R8A7796 SoC based M3ULCB low cost board (R-Car Starter Kit Pro) This commit supports the following peripherals: - SCIF (console) Signed-off-by: Vladimir Barinov --- arch/arm64/boot/dts/renesas/Makefile | 2 +- arch/arm64/boot/dts/renesas/r8a7796-m3

[PATCH 3/9] arm64: dts: m3ulcb: enable SCIF clk and pins

This enables the external crystal for the SCIF_CLK and its pinctrl, to be used by the Baud Rate Generator for External Clock (BRG) on (H)SCIF. Signed-off-by: Vladimir Barinov --- arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts | 13 + 1 file changed, 13 insertions(+) diff --git a/arc

[PATCH 0/9] arm64: renesas: add M3ULCB board

Hello, This adds the folowing: - R8A7796 SoC based M3ULCB (R-Car Starter Kit Pro) device tree - Document DT bindings Vladimir Barinov (9): [1/9] dt: arm: shmobile: add M3ULCB board DT bindings [2/9] arm64: dts: m3ulcb: initial device tree [3/9] arm64: dts: m3ulcb: enable SCIF clk and pins [4/9] a

[PATCH 1/9] dt: arm: shmobile: add M3ULCB board DT bindings

Add M3ULCB Device tree bindings Documentation, listing it as a supported board. Signed-off-by: Vladimir Barinov --- Documentation/devicetree/bindings/arm/shmobile.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicet

[PATCH 3/3] arm64: dts: h3ulcb: enable SDHI2

This supports SDHI2 for H3ULCB onboard eMMC Signed-off-by: Vladimir Barinov --- arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts | 43 ++ 1 file changed, 43 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7795-h3u

[PATCH 1/3] dt: arm: shmobile: update H3ULCB board Documentation

This updates H3ULCB Device tree bindings Documentation with official board name Signed-off-by: Vladimir Barinov --- Documentation/devicetree/bindings/arm/shmobile.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documen

[PATCH 2/3] arm64: dts: h3ulcb: update header

This updates H3ULCB device tree header with official board name Signed-off-by: Vladimir Barinov --- arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a

[PATCH 0/3] arm64: renesas: enable H3ULCB board peripherals

Hello, This adds the folowing: - Update DT bindings documentation - add R8A7795 SoC based H3ULCB board peripherals Vladimir Barinov (3): [1/3] dt: arm: shmobile: update H3ULCB board Documentation [2/3] arm64: dts: h3ulcb: update header [3/3] arm64: dts: h3ulcb: enable SDHI2 --- This patchset is

Re: [PATCH 2/2] pinctrl: sh-pfc: r8a7795: Use lookup function for bias data

Hi Niklas, Thank you for thr patch. On Thursday 03 Nov 2016 16:34:21 Niklas Söderlund wrote: > There is a bug in the r8a7795 bias code where a WARN() is trigged > anytime a pin from PUEN0/PUD0is accessed. > > # cat /sys/kernel/debug/pinctrl/e606.pfc/pinconf-pins > > WARNING: CPU: 2 PID: 2

Re: [PATCH] ARM: DTS: r8a7794: alt: Fix PCF names for DU

Hello. On 11/03/2016 04:42 PM, Jacopo Mondi wrote: Update the PCF pin groups and function names of DU interface for PFC maybe? r8a7794 ALT board. The currently specified pin groups and function names prevented PCF and DU interfaces from being correctly configured: sh-pfc e606.pin-c

Re: [PATCH 1/2] pinctrl: sh-pfc: Do not unconditionally support PIN_CONFIG_BIAS_DISABLE

Hi Niklas, Thank you for the patch. On Thursday 03 Nov 2016 16:34:20 Niklas Söderlund wrote: > Always stating PIN_CONFIG_BIAS_DISABLE is supported gives untrue output > when examining /sys/kernel/debug/pinctrl/e606.pfc/pinconf-pins if > the operation get_bias() are implemented but the pin are

[PATCHv2 2/4] pinctrl: sh-pfc: r8a7795: Support none GPIO pins with configurable drive-strength

There are pins on the r8a7795 which are not part of a GPIO bank nor can be muxed between different functions. They do however allow for the drive-strength to be configured. Add those pins to the list of pins and to the drive-strength configuration registers. The pins can now be referred to in DT b

[PATCHv2 3/4] pinctrl: sh-pfc: r8a7795: Add group for AVB MDIO and MII pins

Group the AVB pins into similar groups found in other sh-pfc drivers. The pins can not be muxed between functions other then AVB but their drive strength can be controlled. The group avb_mdc containing ADV_MDC and ADV_MDIO are on other SoCs called avb_mdio. In pfc-r8a7795 the avb_mdc group already

[PATCHv2 4/4] pinctrl: sh-pfc: r8a7795: Add group for QSPI0 and QSPI1 pins

Group the QSPI0 and QSPI1 pins into similar groups found in other sh-pfc drivers. The pins can not be muxed between functions other then QSPI but there drive strength can be controlled. Signed-off-by: Niklas Söderlund Reviewed-by: Geert Uytterhoeven --- drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 6

[PATCHv2 0/4] pinctrl: sh-pfc: r8a7795: Support none GPIO pins with configurable drive-strength

Hi Geert and Laurent, This series adds support to control the drive strength for none GPIO pins. All pins which can have its drive strength controlled is now supported. I have also added the new pins to the correct groups, or added groups to mimic other sh-pfc drivers. One notable exception is t

[PATCHv2 1/4] pinctrl: sh-pfc: Support named pins with custom configuration

Pins not associated with a GPIO port can still have other configuration parameters. Add a new macro SH_PFC_PIN_NAMED_CFG which allows for named pins to be declared with a set of configurations. The new macro is an modification of SH_PFC_PIN_NAMED to allow for optional configuration to be assigned.

Re: [PATCH v2 0/5] r8a7796 I2C integration

On Mon, Oct 31, 2016 at 12:46 PM, Wolfram Sang wrote: > >> This revision is based on renesas-devel-20161024-v4.9-rc2. It adds the >> Reviewed-bys and the entries for SYS-DMAC2 in the applicable I2C nodes. I >> have also made sure it works with 64-bit memory enabled. > > I'd like to test, but: ca

[PATCH 2/2] pinctrl: sh-pfc: r8a7795: Use lookup function for bias data

There is a bug in the r8a7795 bias code where a WARN() is trigged anytime a pin from PUEN0/PUD0is accessed. # cat /sys/kernel/debug/pinctrl/e606.pfc/pinconf-pins WARNING: CPU: 2 PID: 2391 at drivers/pinctrl/sh-pfc/pfc-r8a7795.c:5364 r8a7795_pinmux_get_bias+0xbc/0xc8 [..] Call trace: []

[PATCH 0/2] pinctrl: sh-pfc: Fixups for bias handeling

Hi Geert and Laurent, This series fixes two issues I encounter for bias handling in the PFC while preparing my drive strength patch set. I do believe we should try to get the r8a7795 specific fix in to v4.9, do you agree (if the fix itself is acceptable ofc)? Niklas Söderlund (2): pinctrl: s

[PATCH 1/2] pinctrl: sh-pfc: Do not unconditionally support PIN_CONFIG_BIAS_DISABLE

Always stating PIN_CONFIG_BIAS_DISABLE is supported gives untrue output when examining /sys/kernel/debug/pinctrl/e606.pfc/pinconf-pins if the operation get_bias() are implemented but the pin are not handled by the get_bias() implementation. In that case the output will state that "input bias di

[PATCH v8 1/3] ARM: dts: lager: Enable UHS-I SDR-104

Add the sd-uhs-sdr104 property to SDHI0. Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7790-lager.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts index 434268262d88..e42748a5fe10 100644 --- a/arch/arm/boot/

[PATCH v8 3/3] ARM: dts: alt: Enable UHS-I SDR-104

And the sd-uhs-sdr104 property to SDHI0. Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7794-alt.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/r8a7794-alt.dts b/arch/arm/boot/dts/r8a7794-alt.dts index 325d3f972c57..ccb80d66076f 100644 --- a/arch/arm/boot/dts/r8

[PATCH v8 0/3] ARM, arm64: renesas: Enable UHS-I SDR-104

Hi, this series enables SDHI UHS-I SDR-104 on: * r8a7790/lager * r8a7791/koelsch * r8a7794/alt It is based on renesas-next-20161102-v4.9-rc1. For functional SDR-104 support the following dependencies are needed: * [PATCH v8 0/6] UHS-I SDR-104 support for sh_mobile_sdhi To aid review the followi

[PATCH v8 2/3] ARM: dts: koelsch: Enable UHS-I SDR-104

And the sd-uhs-sdr104 property to SDHI0. Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7791-koelsch.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts index c457b43deb7d..57e69af65136 100644 --- a/arch/arm

[PATCHv2] v4l: vsp1: Provide a writeback video device

When the VSP1 is used in an active display pipeline, the output of the WPF can supply the LIF entity directly and simultaneously write to memory. Support this functionality in the VSP1 driver, by extending the WPF source pads, and establishing a V4L2 video device node connected to the new source.

[PATCH v8 0/6] UHS-I SDR-104 support for sh_mobile_sdhi

Hi, this series is based on work by Ai Kyuse to add UHS-I SDR-104 support for sh_mobile_sdhi. It builds on work by Shinobu Uehara, Rob Taylor, William Towle and Ian Molton, Ben Hutchings, Wolfram Sang and others to add UHS-I SDR-50 support to the same driver. It is based on the next branch of the

[PATCH v8 1/6] mmc: core: Add helper to see if a host can be retuned

This is in preparation for restoring saved tuning parameters when resuming the TMIO driver. Signed-off-by: Simon Horman --- v6 * New patch --- include/linux/mmc/host.h | 5 + 1 file changed, 5 insertions(+) diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h index 0b2439441cc8.

[PATCH v8 4/6] mmc: tmio: Add hw reset support

From: Ai Kyuse Add hw reset support. Signed-off-by: Ai Kyuse Signed-off-by: Simon Horman --- This is required by tuning support which will be introduced by follow-up patches. v6 * Rely on core to retune on reset v5 * As suggested by Ulf Hansson - Broke out of a larger patch --- drivers/mm

[PATCH v8 3/6] mmc: tmio: document mandatory and optional callbacks

Signed-off-by: Simon Horman --- v5 * New patch --- drivers/mmc/host/tmio_mmc.h | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/tmio_mmc.h b/drivers/mmc/host/tmio_mmc.h index 8e126afd988c..b93762950e8f 100644 --- a/drivers/mmc/host/tmio_mmc.h +++ b/drivers/

[PATCH v8 6/6] mmc: sh_mobile_sdhi: Add tuning support

Add tuning support for use with SDR104 mode This includes adding support for the sampling clock controller (SCC). Based on work by Ai Kyuse. Cc: Ai Kyuse Signed-off-by: Simon Horman --- v8 [Simon Horman] * Correct inverted logic in sh_mobile_sdhi_hw_reset * Correct value of SH_MOBILE_SDHI_SCC_R

[PATCH v8 5/6] mmc: tmio: Add tuning support

From: Ai Kyuse Add tuning support for use with SDR104 mode Signed-off-by: Ai Kyuse Signed-off-by: Simon Horman --- v7 [Simon Horman] * As per review by Ulf Hansson: - Use tmio_mmc_hw_reset() rather than mmc_hw_reset() in tmio_mmc_execute_tuning() - Do not zero host->mmc->retune_period

[PATCH v8 2/6] mmc: tmio: enhance illegal sequence handling

From: Ai Kyuse An illegal sequence command error may occur if there is a stopbit or cmd_index error as well as a CRC error. The correct course of action is to re-enable IRQs An illegal sequence data error may occur if there is a CRC or stopbit error, or underrun. In this case set data->error co

Re: [PATCH] pinctrl: sh-pfc: r8a7796: Fix GPSR definitions for SDHI2/3

On Mon, Oct 24, 2016 at 10:22:41AM +0200, Geert Uytterhoeven wrote: > Fix off-by-one (row and/or register) errors in links to Peripheral > Function Select Register bitfields from GPIO/Peripheral Function Select > Register 4 macros for SDHI2 and SDHI3 pins. > > Based on rev. 0.52E of the R-Car Gen3

[PATCH] ARM: DTS: r8a7794: alt: Fix PCF names for DU

Update the PCF pin groups and function names of DU interface for r8a7794 ALT board. The currently specified pin groups and function names prevented PCF and DU interfaces from being correctly configured: sh-pfc e606.pin-controller: function 'du' not supported sh-pfc e606.pin-controller: in

Re: [RFC 2/3] v4l: vsp1: allow entities to have multiple source pads

Hi Laurent, On 02/11/16 23:59, Laurent Pinchart wrote: > Hi Kieran, > > Thank you for the patch. > > On Thursday 27 Oct 2016 15:01:24 Kieran Bingham wrote: >> The upcoming writeback feature of the VSP1 WPF, allows the active output >> of the DU to be written back to memory. On Generation 3 hardw