On 01.07.2017 20:14, Uwe Kleine-König wrote:
Hello,
On Sat, Jul 01, 2017 at 07:02:48AM +0200, Dirk Behme wrote:
On 30.06.2017 22:24, Uwe Kleine-König wrote:
Hello,
On Fri, Jun 30, 2017 at 10:58:26AM -0500, Rob Herring wrote:
TL;DR: Clocks may be in use by another CPU not running Linux,
The VersaClock 6 has an input frequency doubler between the input
clock mux and the predivider. Add new capability flag and support
for this frequency doubler block into the driver.
Signed-off-by: Marek Vasut
Cc: Stephen Boyd
Cc: Alexey
In case the initial values of the FOD registers are not configured in
the OTP or by the bootloader, it is possible that the FOD registers
will contain zeroes. The code in vc5_fod_recalc_rate() immediately
feeds the FOD divider value obtained from the FOD registers into the
div64_u64() and if the
IDT VersaClock 6 5P49V6901 has 4 clock outputs, 4 fractional dividers.
Input clock source can be taken from either external crystal or from
external reference clock.
Signed-off-by: Marek Vasut
Cc: Alexey Firago
Cc: Rob Herring
Update IDT VersaClock 5 driver to support IDT VersaClock 6 5P49V6901.
This chip has two clock inputs (external XTAL or external CLKIN), four
fractional dividers (FODs) and five clock outputs (four universal clock
outputs and one reference clock output at OUT0_SELB_I2C).
Signed-off-by: Marek Vasut
The output buffer input mux can be configured in either of three
states -- disabled, input from FOD, input from previous output.
If the output buffer input mux is set to disabled, the code in
vc5_clk_out_get_parent() would consider this an invalid setting
and warn about it, which is not
The output buffer input mux can be configured in either of three
states -- disabled, input from FOD, input from previous output.
Once the .prepare() callback of the output buffer is called, the
output buffer input mux must be set to either input from FOD or
input from previous output, it cannot be
Fix trivial typo in vc5_clk_out_unprepare() , s/Enable/Disable/ .
Signed-off-by: Marek Vasut
Cc: Stephen Boyd
Cc: Alexey Firago
Cc: Michael Turquette
Cc: Laurent Pinchart
On 06/30/2017 09:26 PM, Stephen Boyd wrote:
> On 06/29, Marek Vasut wrote:
>> @@ -549,6 +552,7 @@ static unsigned char vc5_clk_out_get_parent(struct
>> clk_hw *hw)
>>
>> dev_warn(>client->dev,
>> "Invalid clock output configuration (%02x)\n", src);
>> +
>> return 0;
>>
Split the VC5 clock input mux and the predivider to more accurately
model the hardware and fix the previously incorrect assumption that
both the OUT_SEL_I2CB and the PLL are fed from the predivider.
It is in fact the clock input mux output which is directly feeding
the clock into the OUT_SEL_I2CB
Hello,
On Sat, Jul 01, 2017 at 07:02:48AM +0200, Dirk Behme wrote:
> On 30.06.2017 22:24, Uwe Kleine-König wrote:
> > Hello,
> >
> > On Fri, Jun 30, 2017 at 10:58:26AM -0500, Rob Herring wrote:
> > > > TL;DR: Clocks may be in use by another CPU not running Linux, while
> > > > Linux
> > > >
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