From: Takeshi Kihara
This patch adds I2C{0,3,5} pins, groups and functions to the R8A7795 SoC.
These pins are physically muxed with other pins. Therefore, setup of
MOD_SEL is needed for exclusive control with other pins.
Signed-off-by: Takeshi Kihara
Signed-off-by: Ulrich Hecht
---
From: Takeshi Kihara
This patch adds I2C{0,3,5} pins, groups and functions to
the R8A7795 ES1.x SoC.
These pins are physically muxed with other pins. Therefore, setup of
MOD_SEL is needed for exclusive control with other pins.
Signed-off-by: Takeshi Kihara
Signed-off-by: Ulrich Hecht
---
From: Takeshi Kihara
This patch adds I2C{0,3,5} pins, groups and functions to the R8A7796 SoC.
These pins are physically muxed with other pins. Therefore, setup of
MOD_SEL is needed for exclusive control with other pins.
Signed-off-by: Takeshi Kihara
Signed-off-by: Ulrich Hecht
---
Used by I2C controllers 0, 3 and 5 in R8A7795 and R8A7796 SoCs.
Signed-off-by: Ulrich Hecht
---
drivers/pinctrl/sh-pfc/sh_pfc.h | 22 ++
1 file changed, 22 insertions(+)
diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h
index 1fc1336..6bb9c6b
This is an up-port from the BSP. Unfortunately I could not test these
because none of those pins seem to be accessible on Salvator boards (not on
ULCB either, AFAICT), so the best thing I can say is that they don't seem to
break anything.
This revision incorporates the suggestions made by Geert;
Hi Jacopo,
On Thursday, November 15, 2018 1, jacopo mondi wrote:
> > v5:
> > * Specify number of ports using of_device_id.data and save as priv-
> >npins
> > * Use priv->npins everywhere instead of hard coded RZA2_NPINS
> > * Check gpio-ranges to make sure args matches SOC
>
> Sorry about
From: Takeshi Kihara
This patch adds HSCIF{0,1,2,3,4} pins, groups and functions to
the R8A77990 SoC.
Signed-off-by: Takeshi Kihara
Signed-off-by: Yoshihiro Kaneko
---
This patch is based on the sh-pfc branch of Geert Uytterhoeven's
renesas-drivers tree.
v2 [Yoshihiro Kaneko]
* As suggested
Hi Geert-san,
Thanks for your review!!
2018年11月6日(火) 0:30 Geert Uytterhoeven :
>
> Hi Kaneko-san,
>
> On Sat, Oct 20, 2018 at 11:31 PM Yoshihiro Kaneko
> wrote:
> > From: Takeshi Kihara
> >
> > This patch adds HSCIF{0,1,2,3,4} pins, groups and functions to
> > the R8A77990 SoC.
> >
> >
Hi Chris,
On Thu, Nov 15, 2018 at 09:00:44AM -0500, Chris Brandt wrote:
> Adds support for the pin and gpio controller found in R7S9210 (RZ/A2) SoCs.
>
> Signed-off-by: Chris Brandt
> Reviewed-by: Jacopo Mondi
> ---
> v5:
> * Specify number of ports using of_device_id.data and save as
The pin controller in the RZ/A2 is nothing like the pin controller in
the RZ/A1. That's a good thing! This pin controller is much more simple
and easier to configure.
So, this driver is faily simple (I hope).
Chris Brandt (2):
pinctrl: Add RZ/A2 pin and gpio controller
dt-bindings: pinctrl:
Adds support for the pin and gpio controller found in R7S9210 (RZ/A2) SoCs.
Signed-off-by: Chris Brandt
Reviewed-by: Jacopo Mondi
---
v6:
* Bug fix: Output value not being set in rza2_chip_direction_output()
v5:
* Specify number of ports using of_device_id.data and save as priv->npins
* Use
Add device tree binding documentation and header file for Renesas R7S9210
(RZ/A2) SoCs.
Signed-off-by: Chris Brandt
Reviewed-by: Rob Herring
Reviewed-by: Geert Uytterhoeven
Reviewed-by: Jacopo Mondi
---
v4:
* Converted Px to PORTx because of conflict with "PM"
* Rounded up reg range
*
On 11/15/2018 03:33 PM, Simon Horman wrote:
> On Wed, Nov 14, 2018 at 04:32:05PM +0100, Marek Vasut wrote:
>> On 11/13/2018 04:22 PM, Geert Uytterhoeven wrote:
>>> Enable R-Car Gen3 PCIe PHY support, which is needed for PCIe to function
>>> on the Renesas Condor board.
>>>
>>> Signed-off-by: Geert
On Tue, Nov 13, 2018 at 04:20:23PM +0100, Geert Uytterhoeven wrote:
> Hi Simon,
>
> On Tue, Nov 13, 2018 at 3:31 PM Simon Horman wrote:
> > On Wed, Nov 07, 2018 at 12:21:16PM +0100, Simon Horman wrote:
> > > On Mon, Oct 22, 2018 at 02:14:34AM +0900, Magnus Damm wrote:
> > > > Connect R-Car Gen3
On Wed, Nov 14, 2018 at 04:32:05PM +0100, Marek Vasut wrote:
> On 11/13/2018 04:22 PM, Geert Uytterhoeven wrote:
> > Enable R-Car Gen3 PCIe PHY support, which is needed for PCIe to function
> > on the Renesas Condor board.
> >
> > Signed-off-by: Geert Uytterhoeven
>
> This helps
>
>
On Wed, Nov 14, 2018 at 10:56:04AM +0100, Geert Uytterhoeven wrote:
> Hi Inami-san,
>
> On Thu, Nov 8, 2018 at 8:25 AM Gaku Inami wrote:
> > Set the capacity-dmips-mhz for R-Car Gen3 SoCs, that is based on
> > dhrystone. The average in 10 times of dhrystone result as follows:
>
> [...]
>
> >
On Wed, Nov 14, 2018 at 10:50:03AM +0100, Geert Uytterhoeven wrote:
> Hi Inami-san,
>
> On Thu, Nov 8, 2018 at 8:25 AM Gaku Inami wrote:
> > This patch adds the "cpu-map" into r8a7795/r8a7796 composed of
> > multi-cluster. This definition is used to parse the cpu topology.
> >
> > Signed-off-by:
On Thu, Nov 15, 2018 at 10:57:31AM +0100, Geert Uytterhoeven wrote:
> As of commit 9a9863987bf7307f ("ARM: shmobile: Remove legacy SoC code
> for SH-Mobile AG5"), this header file is no longer used.
>
> Signed-off-by: Geert Uytterhoeven
Thanks Geert,
applied for v4.21.
On Thu, Nov 15, 2018 at 10:56:38AM +0100, Geert Uytterhoeven wrote:
> Currently support for the ARM Cortex-A9 Snoop Control Unit is included
> unconditionally, while only Renesas multicore Cortex-A9 SoCs have this
> kind of SCU.
>
> This decreases kernel image size by ca. 300 bytes on SoCs
On Thu, Nov 15, 2018 at 10:56:39AM +0100, Geert Uytterhoeven wrote:
> Currently support for the ARM Timer and Watchdog Unit is included
> unconditionally, while only some Renesas multicore Cortex-A9 SoCs have
> a TWD.
>
> This decreases kernel image size by ca. 2 KiB on SoCs without a TWD.
>
>
On Thu, Nov 15, 2018 at 10:46:49AM +0100, Geert Uytterhoeven wrote:
> From: Takeshi Kihara
>
> The R-Car GPIO driver cannot be enabled when Renesas SoC's ARCH configs
> (ARCH_RENESAS, ARCH_R8A7795, ARCH_R8A7796 and ARCH_R8A77965) are enabled
> only.
>
> As GPIOs are a critical resource for
Adds support for the pin and gpio controller found in R7S9210 (RZ/A2) SoCs.
Signed-off-by: Chris Brandt
Reviewed-by: Jacopo Mondi
---
v5:
* Specify number of ports using of_device_id.data and save as priv->npins
* Use priv->npins everywhere instead of hard coded RZA2_NPINS
* Check
The pin controller in the RZ/A2 is nothing like the pin controller in
the RZ/A1. That's a good thing! This pin controller is much more simple
and easier to configure.
So, this driver is faily simple (I hope).
Chris Brandt (2):
pinctrl: Add RZ/A2 pin and gpio controller
dt-bindings: pinctrl:
Add device tree binding documentation and header file for Renesas R7S9210
(RZ/A2) SoCs.
Signed-off-by: Chris Brandt
Reviewed-by: Rob Herring
Reviewed-by: Geert Uytterhoeven
Reviewed-by: Jacopo Mondi
---
v4:
* Converted Px to PORTx because of conflict with "PM"
* Rounded up reg range
*
Thanks for your patch!
>
> While I could see no obvious deficiencies at first glance, I gave your
> patch a try on Koelsch and Salvator-XS.
Thank you for testing the patch!
These issues seem to be related to a few patches that were merged only recently,
I have rebased my work on top of the next-
Hi Shimodaさん
> From: Yoshihiro Shimoda
> Sent: Thursday, November 15, 2018 4:20 AM
> > Host does NOT work:
> > //else
> > // /* No otg, so default to host mode */
> > // writel(0x, usb2_base + USB2_COMMCTRL);
>
> I got it. However, I have a concern how to set the
Hi Geert,
On Thursday, November 15, 2018, Geert Uytterhoeven wrote:
> > As for validating the values, the only thing I can really check is that:
> > of_args.args[2] == RZA2_NPINS
> >
> > Of course, now that I say that, I realize that if/when it does come time
> > to expand this driver beyond
From: Biju Das
This patch adds binding for r8a774a1 (RZ/G2M).
Signed-off-by: Biju Das
Reviewed-by: Fabrizio Castro
Acked-by: Vinod Koul
Reviewed-by: Simon Horman
Reviewed-by: Rob Herring
---
Documentation/devicetree/bindings/dma/renesas,usb-dmac.txt | 1 +
1 file changed, 1 insertion(+)
Renesas' RZ/G2M (R8A774A1) SoC has DMA controllers compatible
with this driver, therefore document RZ/G2M specific bindings.
Signed-off-by: Fabrizio Castro
Reviewed-by: Biju Das
Reviewed-by: Rob Herring
Reviewed-by: Simon Horman
---
Currently support for the ARM Timer and Watchdog Unit is included
unconditionally, while only some Renesas multicore Cortex-A9 SoCs have
a TWD.
This decreases kernel image size by ca. 2 KiB on SoCs without a TWD.
Signed-off-by: Geert Uytterhoeven
---
arch/arm/mach-shmobile/Kconfig | 3 ++-
1
Hi Simon, Magnus,
When Renesas ARM multi-platform support was conceived in commit
efacfce5f8a52345 ("ARM: shmobile: Introduce ARCH_SHMOBILE_MULTI"),
support for the ARM Cortex-A9 Snoop Control Unit and the Timer and
Watchdog Unit was enabled unconditionally.
However, only some Renesas
From: Takeshi Kihara
The R-Car GPIO driver cannot be enabled when Renesas SoC's ARCH configs
(ARCH_RENESAS, ARCH_R8A7795, ARCH_R8A7796 and ARCH_R8A77965) are enabled
only.
As GPIOs are a critical resource for proper operation on Renesas
platforms, this patch selects GPIOLIB, just like is done
As of commit d1dabab2841d546f ("ARM: OMAP2+: Clean up
omap4_local_timer_init"), this header file is no longer used.
Signed-off-by: Geert Uytterhoeven
---
arch/arm/mach-omap2/timer.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
As of commit 9a9863987bf7307f ("ARM: shmobile: Remove legacy SoC code
for SH-Mobile AG5"), this header file is no longer used.
Signed-off-by: Geert Uytterhoeven
---
arch/arm/mach-shmobile/smp-sh73a0.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm/mach-shmobile/smp-sh73a0.c
Currently support for the ARM Cortex-A9 Snoop Control Unit is included
unconditionally, while only Renesas multicore Cortex-A9 SoCs have this
kind of SCU.
This decreases kernel image size by ca. 300 bytes on SoCs without such
an SCU.
Signed-off-by: Geert Uytterhoeven
---
Thank you Geert for spotting the issue, thank you Simon for fixing.
Cheers,
Fab
> From: Simon Horman
> Sent: 13 November 2018 14:46
> Subject: Re: [PATCH 2/2] arm64: dts: renesas: r8a774a1: Replace clock magic
> numbers
>
> On Tue, Nov 13, 2018 at 09:53:55AM +0100, Geert Uytterhoeven wrote:
>
Hi Chris-san,
> From: Chris Brandt, Sent: Wednesday, November 14, 2018 10:03 PM
>
> Hi Shimoda-san,
>
> > From: Yoshihiro Shimoda
> > Sent: Wednesday, November 14, 2018 7:24 AM
> > > > > config PHY_RCAR_GEN3_USB2
> > > > > tristate "Renesas R-Car generation 3 USB 2.0 PHY driver"
> > > >
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