d160ed0a94927e ("ARM: shmobile: Convert file to use cntvoff")
> Signed-off-by: Geert Uytterhoeven
Reviewed-by: Maxime Ripard
Maxime
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Driver is based on a prototype by Koji Matsuoka in the Renesas BSP.
>
> Signed-off-by: Niklas Söderlund <niklas.soderlund+rene...@ragnatech.se>
Reviewed-by: Maxime Ripard <maxime.rip...@bootlin.com>
Maxime
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Hi!
On Tue, May 08, 2018 at 10:11:07AM -0700, Florian Fainelli wrote:
> On 05/08/2018 06:19 AM, Maxime Ripard wrote:
> > Hi,
> >
> > On Fri, May 04, 2018 at 09:05:33PM +0200, Mylène Josserand wrote:
> >> Hello everyone,
> >>
> >> This is a V9
83t
> (see patch 07), according to Maxime's review.
The machine name hasn't changed, and the name sun8i-a83t still doesn't
make much sense. I've fixed it as well.
Thanks,
Maxime
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Embedded Linux and Kernel engineering
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instead.
>
> Signed-off-by: Mylène Josserand <mylene.josser...@bootlin.com>
Acked-by: Maxime Ripard <maxime.rip...@bootlin.com>
Maxime
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net.au>
For the sake of bisectability (and to ease the merge), is it ok if we
take it through the sunxi (and then arm-soc) tree?
Thanks!
Maxime
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Embedded Linux and Kernel engineering
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e is the Power Off Gating register for clusters
> which is BIT(4) in case of SUN9I-A80 and BIT(0) in case of SUN8I-A83T.
> There is also a bit swap between sun8i-a83t and sun9i-a80 that must be
> handled.
>
> Signed-off-by: Mylène Josserand <mylene.josser...@bootlin.com&g
Signed-off-by: Mylène Josserand <mylene.josser...@bootlin.com>
Acked-by: Maxime Ripard <maxime.rip...@bootlin.com>
Maxime
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tartup
> assembly entry.
>
> Signed-off-by: Mylène Josserand <mylene.josser...@bootlin.com>
> Acked-by: Maxime Ripard <maxime.rip...@bootlin.com>
> ---
> arch/arm/mach-sunxi/headsmp.S | 1 +
> arch/arm/mach-sunxi/sunxi.c | 20 +++-
> 2 files ch
_init();
> +#endif
> +}
> +
> +static const char * const sun8i_cntvoff_board_dt_compat[] = {
> + "allwinner,sun8i-a83t",
> + NULL,
> +};
> +
> +DT_MACHINE_START(SUN8I_CNTVOFF_DT, "Allwinner sun8i-a83t board")
This name still doesn't really make mu
_is_cortex_a15(unsigned int core, unsigned int cluster)
> {
> @@ -624,6 +625,7 @@ struct sunxi_mc_smp_nodes {
> struct sunxi_mc_smp_data {
> const char *enable_method;
> int (*get_smp_nodes)(struct sunxi_mc_smp_nodes *nodes);
> + int is_a83t;
This can be ma
On Tue, Apr 17, 2018 at 07:25:15PM +0800, Chen-Yu Tsai wrote:
> On Tue, Apr 17, 2018 at 7:17 PM, Maxime Ripard
> <maxime.rip...@bootlin.com> wrote:
> > On Tue, Apr 17, 2018 at 11:12:41AM +0800, Chen-Yu Tsai wrote:
> >> On Tue, Apr 17, 2018 at 5:50 AM, Mylène Jo
id you have time to test it?
Maxime
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Embedded Linux and Kernel engineering
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; >
> > Do we really need to cache it? Can't we just have a pointer to the SMP
> > data structure and use that instead?
>
> I recommended that. We don't need any of the other fields in the SMP
> data structure once we're past the init phase. This saves a dereference
>
actually. There's a significant
readibility improvement, so even if there's no particular functional
improvement, I'd still call it a win.
Maxime
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>
> + is_sun8i = sunxi_mc_smp_data[i].is_sun8i;
> +
Do we really need to cache it? Can't we just have a pointer to the SMP
data structure and use that instead?
Maxime
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goto error;
> +
> + pm_runtime_enable(>dev);
Is CONFIG_PM mandatory on Renesas SoCs? If not, you end up with the
device uninitialised at probe, and pm_runtime_get_sync will not
initialise it either if CONFIG_PM is not enabled. I guess you could
call your runtime_re
Cc: Manfred Schlaegl <manfred.schla...@gmx.at>
> Cc: Marek Vasut <ma...@denx.de>
> Cc: Archit Taneja <arch...@codeaurora.org>
> Cc: Andrzej Hajda <a.ha...@samsung.com>
> Cc: Alison Wang <alison.w...@freescale.com>
> Cc: Eric Anholt <e...@anholt.net>
&
ey_modes),
> + true);
You seem to define the same list in your enumeration between your
patch 2 and this one. Can this be something made generic too?
Maxime
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operties
> related to color keying named colorkey.min, colorkey.max, colorkey.alpha
> and colorkey.mode. Additional properties can be defined by drivers to
> expose device-specific features.
>
> Signed-off-by: Laurent Pinchart <laurent.pinchart+rene...@ideasonboard.com>
xed both using the virtual channels and
the data-types, I'm not sure representing it using only muxed pads
like you did would work.
And I don't really know what a good stop gap measure would be either.
Thanks!
Maxime
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Hi Daniel,
On Tue, Jul 18, 2017 at 09:35:03AM +0200, Daniel Vetter wrote:
> On Tue, Jul 18, 2017 at 9:07 AM, Maxime Ripard
> <maxime.rip...@free-electrons.com> wrote:
> > On Mon, Jul 17, 2017 at 02:57:19PM +0800, Chen-Yu Tsai wrote:
> >> On Mon, Jul 17, 201
rything else happens
>in the v4l2-async framework. This leaves the interface in a good
>position for possible changes in v4l2-async.
>
> This is tested on Renesas H3 and M3-W together with the Renesas CSI-2
> and VIN Gen3 driver (posted separately). It is based on top of t
ediatek.com>
> Cc: Philipp Zabel <p.za...@pengutronix.de>
> Cc: Matthias Brugger <matthias@gmail.com>
> Cc: Neil Armstrong <narmstr...@baylibre.com>
> Cc: Carlo Caione <ca...@caione.org>
> Cc: Kevin Hilman <khil...@baylibre.com>
> Cc
uk>
> Cc: Matthias Brugger <matthias....@gmail.com>
> Cc: Geert Uytterhoeven <geert+rene...@glider.be>
> Cc: Maxime Ripard <maxime.rip...@free-electrons.com>
> Cc: Chen-Yu Tsai <w...@csie.org>
> Cc: "Emilio López" <emi...@elopez.com.ar>
> Cc:
On Mon, Jul 17, 2017 at 02:57:19PM +0800, Chen-Yu Tsai wrote:
> On Mon, Jul 17, 2017 at 2:55 PM, Maxime Ripard
> <maxime.rip...@free-electrons.com> wrote:
> > On Fri, Jul 14, 2017 at 04:56:01PM +0800, Chen-Yu Tsai wrote:
> >> Hi,
> >>
> >> On
Hi Laurent,
On Fri, Jul 14, 2017 at 02:43:12AM +0300, Laurent Pinchart wrote:
> Hi Maxime,
>
> Thank you for the patch.
>
> On Thursday 13 Jul 2017 16:41:13 Maxime Ripard wrote:
> > The current drm_atomic_helper_commit_tail helper works only if the CRTC is
> >
On Fri, Jul 14, 2017 at 04:56:01PM +0800, Chen-Yu Tsai wrote:
> Hi,
>
> On Thu, Jul 13, 2017 at 10:41 PM, Maxime Ripard
> <maxime.rip...@free-electrons.com> wrote:
> > In the earlier display engine designs, any register access while a commit
> > is pen
; [PATCH 1/4] drm/atomic: implement drm_atomic_helper_commit_tail for
> > runtime_pm users
>
> Never mind - I've just looked again, and seen that this new helper function is
> the ordering previous to *this* patch, and therefore isn't the same.
>
> However - it's worth noting t
modifications.
Signed-off-by: Maxime Ripard <maxime.rip...@free-electrons.com>
---
drivers/gpu/drm/sun4i/sun4i_crtc.c | 2 ++
drivers/gpu/drm/sun4i/sunxi_engine.h | 14 ++
2 files changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/sun4i/sun4i_crtc.c
b/drivers/gpu/drm
The backend (planes) commit can only happen when the TCON (CRTC) is
enabled, which is not guaranteed with the default commit_tail helper.
Let's use the runtime_pm version that is designed specifically to deal with
that case.
Signed-off-by: Maxime Ripard <maxime.rip...@free-electrons.
In the earlier display engine designs, any register access while a commit
is pending is forbidden.
One of the symptoms is that reading a register will return another, random,
register value which can lead to register corruptions if we ever do a
read/modify/write cycle.
Signed-off-by: Maxime
the relevant users can
use directly.
Signed-off-by: Maxime Ripard <maxime.rip...@free-electrons.com>
---
drivers/gpu/drm/drm_atomic_helper.c| 47 +++
drivers/gpu/drm/exynos/exynos_drm_fb.c | 27 +-
drivers/gpu/drm/rcar-du/rcar_du_kms.c
On Wed, Nov 30, 2016 at 02:57:35PM +0900, Chanwoo Choi wrote:
> This patch just uses the resource-managed extcon API when registering
> the extcon notifier.
>
> Signed-off-by: Chanwoo Choi <cw00.c...@samsung.com>
Acked-by: Maxime Ripard <maxime.rip...@free-electrons
an adv7123 driver when needed without breaking backward
> compatibility.
>
> Signed-off-by: Laurent Pinchart <laurent.pinchart+rene...@ideasonboard.com>
Acked-by: Maxime Ripard <maxime.rip...@free-electrons.com>
Thanks!
Maxime
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