On 08/23/2018 01:43 PM, Ulf Hansson wrote:
>> The DM_CM_RST register actually has bits 0-31 defaulting to 1s and bits
>> 32-63 defaulting to 0s -- fix off-by-one in #define RST_RESERVED_BITS.
>>
>> Signed-off-by: Sergei Shtylyov
>
> Reviewed-by: Wolfram Sang
>
>
On 22 August 2018 at 22:03, Sergei Shtylyov
wrote:
> On 08/22/2018 10:45 PM, Wolfram Sang wrote:
>
> The DM_CM_RST register actually has bits 0-31 defaulting to 1s and bits
> 32-63 defaulting to 0s -- fix off-by-one in #define RST_RESERVED_BITS.
>
> Signed-off-by: Sergei Shtylyov
On 08/22/2018 10:45 PM, Wolfram Sang wrote:
The DM_CM_RST register actually has bits 0-31 defaulting to 1s and bits
32-63 defaulting to 0s -- fix off-by-one in #define RST_RESERVED_BITS.
Signed-off-by: Sergei Shtylyov
>>>
>>> Reviewed-by: Wolfram Sang
>>>
>>> Suggesting
On Wed, Aug 22, 2018 at 10:41:56PM +0300, Sergei Shtylyov wrote:
> On 08/22/2018 10:38 PM, Wolfram Sang wrote:
>
> >> The DM_CM_RST register actually has bits 0-31 defaulting to 1s and bits
> >> 32-63 defaulting to 0s -- fix off-by-one in #define RST_RESERVED_BITS.
> >>
> >> Signed-off-by: Sergei
On 08/22/2018 10:38 PM, Wolfram Sang wrote:
>> The DM_CM_RST register actually has bits 0-31 defaulting to 1s and bits
>> 32-63 defaulting to 0s -- fix off-by-one in #define RST_RESERVED_BITS.
>>
>> Signed-off-by: Sergei Shtylyov
>
> Reviewed-by: Wolfram Sang
>
> Suggesting stable.
Stable
On Wed, Aug 22, 2018 at 09:28:01PM +0300, Sergei Shtylyov wrote:
> The DM_CM_RST register actually has bits 0-31 defaulting to 1s and bits
> 32-63 defaulting to 0s -- fix off-by-one in #define RST_RESERVED_BITS.
>
> Signed-off-by: Sergei Shtylyov
Reviewed-by: Wolfram Sang
Suggesting stable.
The DM_CM_RST register actually has bits 0-31 defaulting to 1s and bits
32-63 defaulting to 0s -- fix off-by-one in #define RST_RESERVED_BITS.
Signed-off-by: Sergei Shtylyov
---
The patch is against Ulf Hansson's 'mmc.git' repo's 'fixes' branch.
drivers/mmc/host/renesas_sdhi_internal_dmac.c |
