This patch fixes an issue that unexpected retransfering happens
if TCR is set to 0 before rcar_dmac_sync_tcr() writes DE bit to
the CHCR register. For example, sh-sci driver can reproduce this
issue like below:
In rx_timer_fn(): /* CHCR DE bit may be set to 1 */
On Sat, Jun 30, 2018 at 01:37:18PM +0300, Sergei Shtylyov wrote:
> Hello!
>
> On 6/28/2018 5:26 PM, Lorenzo Pieralisi wrote:
>
> >>>When testing the R-Car PCIe driver on the Condor board, I noticed that iff
> >>>I left the PCIe PHY driver disabled, the kernel crashed with this BUG:
> >>>
>
Hi Lorenzo,
On Mon, Jul 2, 2018 at 12:31 PM Lorenzo Pieralisi
wrote:
> On Sat, Jun 30, 2018 at 01:37:18PM +0300, Sergei Shtylyov wrote:
> > On 6/28/2018 5:26 PM, Lorenzo Pieralisi wrote:
> > >>>When testing the R-Car PCIe driver on the Condor board, I noticed that
> > >>>iff
> > >>>I left the
Hi,
> The second patch is an extension to the virtio-gpu protocol to allow memory
> for buffers to be allocated by the host and mapped to the guest, in an attempt
> to remove a full-frame memcpy() for each page flip.
> I haven't finished implementing this specification in QEMU and the Linux
>
Hi Laurent
> > // This patch started to use C++ style comment out
> > // because it is recent Linus request
>
> I fear this will generate lots of frustration :-/ While I strongly prefer the
> traditional C style, I'm fine leaving the choice to driver authors. However,
> I
> think that
The datasheet do not document any registers to control drive strength,
and no drive strength registers are for this reason described for this
SoC. The flag indicating that drive strength can be controlled are
however set for some pins in the driver.
This leads to a NULL pointer dereference when
Hi Morimoto-san,
Thank you for the patch.
On Monday, 2 July 2018 04:07:17 EEST Kuninori Morimoto wrote:
> From: Kuninori Morimoto
>
> We need to clear channel register in error case as recovery.
> The channel is already stopped in such case, thus we don't need to call
> rcar_dmac_chan_halt()
Hi Geert,
On 2018-06-28 08:57:40 +0200, Geert Uytterhoeven wrote:
> Hi Niklas,
>
> On Thu, Jun 28, 2018 at 2:41 AM Niklas Söderlund
> wrote:
> > On 2018-06-27 10:27:54 +0200, Geert Uytterhoeven wrote:
> > > On Wed, Jun 27, 2018 at 8:01 AM Niklas Söderlund
> > > wrote:
> > > > Not all SoCs
Hi Niklas,
On Mon, Jul 2, 2018 at 9:48 AM Niklas Söderlund
wrote:
> On 2018-06-28 08:57:40 +0200, Geert Uytterhoeven wrote:
> > On Thu, Jun 28, 2018 at 2:41 AM Niklas Söderlund
> > wrote:
> > > On 2018-06-27 10:27:54 +0200, Geert Uytterhoeven wrote:
> > > > On Wed, Jun 27, 2018 at 8:01 AM
Hi Rob,
On Sun, Jul 1, 2018 at 7:27 PM Rob Landley wrote:
> On 06/29/2018 09:25 AM, Geert Uytterhoeven wrote:
> > The RX FIFO timer may be armed when the port is shut down, hence the
> > timer function may still be called afterwards.
> >
> > Fix this race condition by deleting the timer during
This patch adds dma_pause operation. This patch is based on
Muhammad Hamza Farooq's patch.
After this patch applied, an issue that the sh-sci driver with
high baud rate might cause data lost disappeared because the DMAC
is possible to transmit between [1] and [2] below, and then
the residue of
This patch adds a new function rcar_dmac_clear_chcr_de() to simplify
adding pause function later.
Signed-off-by: Yoshihiro Shimoda
---
drivers/dma/sh/rcar-dmac.c | 15 +++
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/drivers/dma/sh/rcar-dmac.c
This patch set is based on the lasest slave-dma / next branch.
This issue can be reproduced by the following commands on r8a7795
Salvator-XS with the fixed patch [1] and Windows Teraterm :) :
# stty 921600
(Change Teraterm baud rate)
# cat > rx.txt
(Send 5MiB file by Teraterm.)
# cmp rx.txt
On Fri, Jun 29, 2018 at 04:51:12PM +0200, Geert Uytterhoeven wrote:
> HSCIF is superior to SCIF (larger FIFOs, more accurate and wider
> supported range of bitrates).
>
> Signed-off-by: Geert Uytterhoeven
Thanks,
This looks fine to me but I will wait to see if there are other reviews
before
CC Sergei,
Thanks for your patch!
On Mon, Jul 2, 2018 at 10:06 AM Niklas Söderlund
wrote:
> The datasheet do not document any registers to control drive strength,
does
> and no drive strength registers are for this reason described for this
> SoC. The flag indicating that drive strength can
On 18 June 2018 at 14:57, Simon Horman wrote:
> Hi,
>
> this patch-set provides SDHI driver support for eMMC HS400.
>
> Based on mmc-v4.18-rc1
>
> Dependencies for applying these patches:
> * none
>
> Dependencies to test eMMC HS400:
> * [PATCH] clk: renesas: rcar-gen3: Fix SD divider setting
> *
On 07/02/2018 04:50 AM, Geert Uytterhoeven wrote:
> Hi Rob,
>
> On Sun, Jul 1, 2018 at 7:27 PM Rob Landley wrote:
>> On 06/29/2018 09:25 AM, Geert Uytterhoeven wrote:
>>> The RX FIFO timer may be armed when the port is shut down, hence the
>>> timer function may still be called afterwards.
>>>
On 07/02/2018 01:33 PM, Lorenzo Pieralisi wrote:
> When testing the R-Car PCIe driver on the Condor board, I noticed that iff
> I left the PCIe PHY driver disabled, the kernel crashed with this BUG:
>
> [1.225819] kernel BUG at lib/ioremap.c:72!
> [1.230007] Internal
Hi Simon,
On Mon, Jun 25, 2018 at 7:05 AM, Simon Horman
wrote:
> Hi Olof, Hi Kevin, Hi Arnd,
>
> Please consider these Renesas ARM based SoC arm SoC updates for v4.19.
>
>
> The following changes since commit ce397d215ccd07b8ae3f71db689aedb85d56ab40:
>
> Linux 4.18-rc1 (2018-06-17 08:04:49
From: Kuninori Morimoto
We need to clear channel register in error case as recovery.
The channel is already stopped in such case, thus we don't need to call
rcar_dmac_chan_halt() before clearing.
rcar_dmac_chan_halt() will clear and confirm DE bit.
But it will be failed because channel is
From: Kuninori Morimoto
Signed-off-by: Kuninori Morimoto
---
drivers/dma/sh/rcar-dmac.c | 18 +++---
1 file changed, 7 insertions(+), 11 deletions(-)
diff --git a/drivers/dma/sh/rcar-dmac.c b/drivers/dma/sh/rcar-dmac.c
index 79d14af..322e57b 100644
---
Hi Morimoto-san,
Thank you for the patch.
On Tuesday, 3 July 2018 03:29:59 EEST Kuninori Morimoto wrote:
> From: Kuninori Morimoto
A commit message would be nice :-)
> Signed-off-by: Kuninori Morimoto
> ---
> drivers/dma/sh/rcar-dmac.c | 18 +++---
> 1 file changed, 7
On Mon, Jun 25, 2018 at 7:03 AM, Simon Horman
wrote:
> Hi Olof, Hi Kevin, Hi Arnd,
>
> Please consider these Renesas ARM64 based SoC DT updates for v4.19.
>
>
> The following changes since commit ce397d215ccd07b8ae3f71db689aedb85d56ab40:
>
> Linux 4.18-rc1 (2018-06-17 08:04:49 +0900)
>
> are
On Mon, Jul 02, 2018 at 10:05:44AM +0200, Niklas Söderlund wrote:
> The datasheet do not document any registers to control drive strength,
> and no drive strength registers are for this reason described for this
> SoC. The flag indicating that drive strength can be controlled are
> however set for
During system reboot or halt, with lockdep enabled:
WARNING: inconsistent lock state
4.18.0-rc1-salvator-x-2-g9203dbec90a68103 #41 Tainted: GW
inconsistent {IN-HARDIRQ-W} -> {HARDIRQ-ON-W} usage.
Hello!
On 7/2/2018 11:05 AM, Niklas Söderlund wrote:
The datasheet do not document any registers to control drive strength,
and no drive strength registers are for this reason described for this
SoC. The flag indicating that drive strength can be controlled are
however set for some pins in the
Hi Geert,
Thanks for your feedback.
On 2018-07-02 15:03:02 +0200, Geert Uytterhoeven wrote:
> CC Sergei,
>
> Thanks for your patch!
>
> On Mon, Jul 2, 2018 at 10:06 AM Niklas Söderlund
> wrote:
> > The datasheet do not document any registers to control drive strength,
>
> does
>
> > and no
On Mon, Jul 02, 2018 at 01:08:45PM +0200, Geert Uytterhoeven wrote:
> Hi Lorenzo,
>
> On Mon, Jul 2, 2018 at 12:31 PM Lorenzo Pieralisi
> wrote:
> > On Sat, Jun 30, 2018 at 01:37:18PM +0300, Sergei Shtylyov wrote:
> > > On 6/28/2018 5:26 PM, Lorenzo Pieralisi wrote:
> > > >>>When testing the
On Mon, Jul 02, 2018 at 02:34:04AM +, Kuninori Morimoto wrote:
>
> From: Kuninori Morimoto
>
> We need to clear channel register in error case as recovery.
> The channel is already stopped in such case, thus we don't need to call
> rcar_dmac_chan_halt() before clearing.
>
>
Hello!
On 7/2/2018 4:03 PM, Geert Uytterhoeven wrote:
CC Sergei,
Thanks for your patch!
On Mon, Jul 2, 2018 at 10:06 AM Niklas Söderlund
wrote:
The datasheet do not document any registers to control drive strength,
does
and no drive strength registers are for this reason described for
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