The Renesas BSP confirms that H3 ES1.x and M3-W ES1.[012] do not
properly support HS400. Add a quirk to indicate this and disable HS400
in the MMC capabilities if the quirk is set.
Signed-off-by: Niklas Söderlund
Tested-by: Wolfram Sang
Reviewed-by: Wolfram Sang
Reviewed-by: Simon Horman
---
Add VIN[012] support to SoC dt.
Signed-off-by: Biju Das
---
arch/arm/boot/dts/r8a7744.dtsi | 33 +
1 file changed, 33 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
index 2eae905..3b8aa3b 100644
---
This patch series aims to add support for some more interfaces
to RZ/G1N SoC (IPMMU, VSP, VIN, PWM and TPU).
This patch series tested against renesas-dev.
it depends on the the below patch series.
https://patchwork.kernel.org/project/linux-renesas-soc/list/?series=48065
Biju Das (5):
ARM:
Hi Biju,
On Wednesday, 28 November 2018 15:20:58 EET Biju Das wrote:
> Hi all,
>
> On the past, I have tested vsp source on rcar gen2 koelsch board, using the
> patches series below(Apart from the below patch series, I have enabled
> "CONFIG_DRM_RCAR_VSP=y")
>
It was though all ES revisions of H3 and M3-W SoCs required the
TMIO_MMC_HAVE_4TAP_HS400 flag. Recent datasheet updates tells us this is
not true, only early ES revisions of the SoC do.
Since quirk matching based on ES revisions is now used to handle the
flag it's possible to align all Gen3
Latest datasheet makes it clear that not all ES revisions of the H3 and
M3-W have the 4-tap HS400 mode quirk, currently the quirk is set
unconditionally for these two SoCs. Prepare to handle the quirk based on
SoC revision instead of compatibility value by using soc_device_match()
and set the
Hi,
Recent datasheet updates have made it clear that some quirks are not SoC
specific but SoC + ES version specific. Currently the quirks are
selected using compatibility values but whit this new information that
is not enough.
Patch 1/3 adds support to select quirks based on SoC + ES revision
Add the definitions for pwm[0123456] to the SoC dtsi.
Signed-off-by: Biju Das
---
arch/arm/boot/dts/r8a7744.dtsi | 70 ++
1 file changed, 70 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
index 152431c..43da6a0
Add the six IPMMU instances found in the r8a7744 to DT with a disabled
status.
Signed-off-by: Biju Das
---
arch/arm/boot/dts/r8a7744.dtsi | 58 ++
1 file changed, 58 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7744.dtsi
Add VSP support to SoC DT.
Signed-off-by: Biju Das
---
arch/arm/boot/dts/r8a7744.dtsi | 27 +++
1 file changed, 27 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
index 3b8aa3b..0937349 100644
---
Add TPU support to SoC DT.
Signed-off-by: Biju Das
---
arch/arm/boot/dts/r8a7744.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
index 43da6a0..40de227 100644
--- a/arch/arm/boot/dts/r8a7744.dtsi
+++
On Mon, Nov 26, 2018 at 01:54:03PM +0100, Simon Horman wrote:
> From: Phil Edworthy
>
> This provides a pinctrl driver for the Renesas R9A06G032 SoC
>
> Based on a patch originally written by Michel Pollet at Renesas.
>
> Signed-off-by: Phil Edworthy
> Geert Uytterhoeven
The tag above is
From: Phil Edworthy
This provides a pinctrl driver for the Renesas R9A06G032 SoC
Based on a patch originally written by Michel Pollet at Renesas.
Signed-off-by: Phil Edworthy
Reviewed-by: Geert Uytterhoeven
Signed-off-by: Simon Horman
---
arch/arm/boot/dts/r9a06g032.dtsi | 8
1
From: Fabrizio Castro
Add device tree nodes for the I2C[0123] controllers. Also, add
the aliases node.
Signed-off-by: Fabrizio Castro
Reviewed-by: Biju Das
Reviewed-by: Geert Uytterhoeven
Signed-off-by: Simon Horman
---
arch/arm/boot/dts/r8a77470.dtsi | 64
From: Fabrizio Castro
RZ/G1C comes with two different types of IP for the SDHI
interfaces, SDHI0 and SDHI2 share the same IP type, and
such an IP is also compatible with the one found in R-Car
Gen2. SDHI1 IP on the other hand is compatible with R-Car
Gen3 with internal DMA.
This patch completes
From: Fabrizio Castro
Althought interface SDHI1 found on the RZ/G1C SoC (a.k.a.
r8a77470) is compatible with the R-Car Gen3 ones, its OF
compatibility is restricted to the SoC specific compatible
string to avoid confusion, as from a more generic perspective
the RZ/G1C is sharing the most
Hi Olof, Hi Kevin, Hi Arnd,
Please consider these Renesas ARM based SoC DT updates for v4.21.
I am sending out this pull-request at this time as there are a number
of patches queued up in my arm (32) DT branch and I hope that this
will ease the burden later on in the development cycle. I expect
From: Fabrizio Castro
Add uSD card and eMMC support to the iwg23s single board
computer powered by the RZ/G1C SoC (a.k.a. r8a77470).
Signed-off-by: Fabrizio Castro
Reviewed-by: Biju Das
Signed-off-by: Simon Horman
---
arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts | 76
From: Laurent Pinchart
The LVDS0 encoder on Koelsh and Porter, and the LVDS1 encoder on Lager,
are enabled in DT but have no device connected to their output. This
result in spurious messages being printed to the kernel log such as
rcar-du feb0.display: no connector for encoder
From: Magnus Damm
Update the R-Mobile A1 (r8a7740), Emma Mobile EV2 (emev2) and
SH-Mobile AG5 (sh72a0) DTSI to include product name.
Signed-off-by: Magnus Damm
[simon: squashed similar patches]
Signed-off-by: Simon Horman
---
arch/arm/boot/dts/emev2.dtsi | 2 +-
From: Fabrizio Castro
This commit adds QSPI flash support to the iwg23s board specific
device tree.
Signed-off-by: Fabrizio Castro
Signed-off-by: Simon Horman
---
arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts | 26 ++
1 file changed, 26 insertions(+)
diff --git
From: Biju Das
This patch enables watchdog support on the iWave iwg23s sbc.
Signed-off-by: Biju Das
Reviewed-by: Fabrizio Castro
Signed-off-by: Simon Horman
---
arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts | 5 +
1 file changed, 5 insertions(+)
diff --git
From: Biju Das
This patch adds USB DMAC nodes.
Signed-off-by: Biju Das
Reviewed-by: Fabrizio Castro
Signed-off-by: Simon Horman
---
arch/arm/boot/dts/r8a77470.dtsi | 56 +
1 file changed, 56 insertions(+)
diff --git a/arch/arm/boot/dts/r8a77470.dtsi
From: Biju Das
This patch adds watchdog support to the r8a77470 SoC dtsi.
Signed-off-by: Biju Das
Reviewed-by: Fabrizio Castro
[simon: moved node to preserve sort order]
Signed-off-by: Simon Horman
---
arch/arm/boot/dts/r8a77470.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff
From: Fabrizio Castro
Add QSPI[01] support to the RZ/G1C SoC specific device tree.
Signed-off-by: Fabrizio Castro
Signed-off-by: Simon Horman
---
arch/arm/boot/dts/r8a77470.dtsi | 32
1 file changed, 32 insertions(+)
diff --git
From: Phil Edworthy
Harmless mistake, but it's incorrect. The DT spec provides recommendations
for the node names:
"The name of a node should be somewhat generic, reflecting the function
of the device and not its precise programming model. If appropriate, the
name should be one of the following
From: Biju Das
Adding pinctrl support for EtherAVB interface.
Signed-off-by: Biju Das
Reviewed-by: Fabrizio Castro
Reviewed-by: Geert Uytterhoeven
Signed-off-by: Fabrizio Castro
Signed-off-by: Simon Horman
---
arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts | 8
1 file changed, 8
From: Biju Das
This patch enables cmt0 support on the iWave iwg23s sbc.
Signed-off-by: Biju Das
Reviewed-by: Fabrizio Castro
Signed-off-by: Simon Horman
---
arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts | 4
1 file changed, 4 insertions(+)
diff --git
From: Biju Das
Add CMT[01] support to r8a77470 SoC DT.
Signed-off-by: Biju Das
Reviewed-by: Fabrizio Castro
Signed-off-by: Simon Horman
---
arch/arm/boot/dts/r8a77470.dtsi | 32
1 file changed, 32 insertions(+)
diff --git a/arch/arm/boot/dts/r8a77470.dtsi
Hi all,
On the past, I have tested vsp source on rcar gen2 koelsch board, using the
patches series below(Apart from the below patch series, I have enabled
"CONFIG_DRM_RCAR_VSP=y")
https://git.linuxtv.org/pinchartl/media.git/log/?h=drm/du/panels
1) [HACK] ARM: shmobile: r8a7791: Link the VSP1
On Mon, Nov 26, 2018 at 06:02:46PM +0100, Niklas Söderlund wrote:
> SD / MMC did not operate properly when suspend transition failed.
> Because the SCC was not reset at resume, issue of the command failed.
> Call the host specific reset function and reset the hardware in order to
> add reset of
> -Original Message-
> From: linux-renesas-soc-ow...@vger.kernel.org ow...@vger.kernel.org> On Behalf Of Simon Horman
> Sent: 28 November 2018 13:24
> To: Biju Das
> Cc: Sergei Shtylyov ; Rob Herring
> ; Mark Rutland ; Magnus
> Damm ; linux-renesas-soc@vger.kernel.org;
>
On Tue, Nov 27, 2018 at 02:22:12PM +, Biju Das wrote:
> Hello Sergei,
>
> Thanks for the feedback.
>
> > -Original Message-
> > From: Sergei Shtylyov
> > Sent: 27 November 2018 14:17
> > To: Biju Das ; Rob Herring
> > ; Mark Rutland
> > Cc: Simon Horman ; Magnus Damm
> > ;
Hi Geert,
Thanks for your feedback.
On 2018-11-05 16:45:39 +0100, Geert Uytterhoeven wrote:
> Hi Niklas,
>
> On Mon, Nov 5, 2018 at 4:07 PM Niklas Söderlund
> wrote:
> > On 2018-11-05 11:43:24 +0100, Geert Uytterhoeven wrote:
> > > On Thu, Nov 1, 2018 at 12:26 AM Niklas Söderlund
> > > wrote:
Hi Niklas,
thanks for the updates! Do you happen to have a branch ready for
testing?
Thanks,
Wolfram
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Hi Wolfram,
On 2018-11-28 22:56:20 +0100, Wolfram Sang wrote:
> Hi Niklas,
>
> thanks for the updates! Do you happen to have a branch ready for
> testing?
I will push a new branch once I'm done updating the clock patch so all
changes can be tested in one go. Will let you know once that is
Quoting Geert Uytterhoeven (2018-11-23 00:56:35)
> Hi Mike, Stephen,
>
> The following changes since commit 651022382c7f8da46cb4872a545ee1da6d097d2a:
>
> Linux 4.20-rc1 (2018-11-04 15:37:52 -0800)
>
> are available in the Git repository at:
>
>
Hi Wolfram,
On 2018-11-28 23:06:37 +0100, Niklas Söderlund wrote:
> Hi Wolfram,
>
> On 2018-11-28 22:56:20 +0100, Wolfram Sang wrote:
> > Hi Niklas,
> >
> > thanks for the updates! Do you happen to have a branch ready for
> > testing?
>
> I will push a new branch once I'm done updating the
The driver tries to figure out which state a SD clock is in when the
clock is register instead of setting a known state. This can be
problematic for two reasons.
1. If the clock driver can't figure out the state of the clock
registration of the clock fails and setting of a known state by a
Document the known use cases of the different clock settings. This is
useful as different SoC and ES versions uses different settings to do
the same thing as there are more then one combination to achieve the
same SDn clock speed.
Signed-off-by: Niklas Söderlund
Reviewed-by: Wolfram Sang
---
Hi Geert,
This series aims to solve the clock quirk needed to enabled HS400 on
SoCs needing special clock handeling. It uses the same method as v1 of
this series and which was discussed during the SDHI hackathon. However
patch 2/2 have been completely rewritten to take your comments from v1
On H3 (ES1.x, ES2.0) and M3-W (ES1.0, ES1.1) the clock setting for HS400
needs a quirk to function properly. The reason for the quirk is that
there are two settings which produces same divider value for the SDn
clock. On the effected boards the one currently selected results in
HS400 not working.
Hi Geert,
On 2018-11-28 19:02:33 +0100, Niklas Söderlund wrote:
> Hi Geert,
>
> Thanks for your feedback.
>
> On 2018-11-05 16:45:39 +0100, Geert Uytterhoeven wrote:
> > Hi Niklas,
> >
> > On Mon, Nov 5, 2018 at 4:07 PM Niklas Söderlund
> > wrote:
> > > On 2018-11-05 11:43:24 +0100, Geert
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