RE: [PATCH 2/3] mmc: tmio-mmc: add support for 32bit data port

On 9/9/2016, Sergei Shtylyov wrote: > > + if (is_read) { > > + sd_ctrl_read32_rep(host, CTL_SD_DATA_PORT, , 1); > > + while (count--) { > > + *buf8 = data * 0xFF; > > 'data & 0xFF', perhaps? Wow...how did I miss

RE: [PATCH v2] net: ethernet: renesas: sh_eth: add POST registers for rz

On 9/9/2016, Sergei Shtylyov wrote: > > sh_eth_private *mdp) { > > if (sh_eth_is_rz_fast_ether(mdp)) { > > sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */ > > + sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, > > +

Re: [PATCH v2] net: ethernet: renesas: sh_eth: add POST registers for rz

On 09/07/2016 09:57 PM, Chris Brandt wrote: Due to a mistake in the hardware manual, the FWSLC and POST1-4 registers were not documented and left out of the driver for RZ/A making the CAM feature non-operational. Additionally, when the offset values for POST1-4 are left blank, the driver

Re: [PATCH 2/3] mmc: tmio-mmc: add support for 32bit data port

Hello. On 09/09/2016 06:52 PM, Chris Brandt wrote: For the r7s72100 SOC, the DATA_PORT register was change to be 32-bits wide. Therefore a new flag has been created that will allow 32-bit reads/writes to the DATA_PORT register instead of 16-bit (because 16-bits accesses are not supported).

Re: [PATCH v2] net: ethernet: renesas: sh_eth: add POST registers for rz

Hello. On 09/07/2016 09:57 PM, Chris Brandt wrote: Due to a mistake in the hardware manual, the FWSLC and POST1-4 registers were not documented and left out of the driver for RZ/A making the CAM feature non-operational. Additionally, when the offset values for POST1-4 are left blank, the

Re: [PATCH 3/3] pinctrl: sh-pfc: r8a7794: Implement voltage switching for SDHI

Hi Simon, On Fri, Sep 9, 2016 at 5:26 PM, Simon Horman wrote: >> > + /* GP6_16-23 -> bits 31-24 of pocctrl >> > +* GP6_06-> bit 23of pocctrl >> > +* GP6_00-05 -> bits 22-17 of pocctrl >> > +* GP6_07-> bit 16of pocctrl >> > +

Re: [GIT PULL] Renesas ARM Based SoC Fixes for v4.8

On Wednesday, September 7, 2016 9:41:04 AM CEST Simon Horman wrote: > Renesas ARM Based SoC Fixes for v4.8 > > * Correct R-Car Gen2 regulator quirk > Pulled into fixes, thanks! Arnd

[PATCH 1/3] mmc: sh_mobile_sdhi: add ocr_mask option

In moving platforms from board files to DT, there still needs to be a way to set the ocr_mask setting for the tmio driver during probe. Without this setting, the probe will fail because the supported voltages are not known. This patch will also traditional platform registration platforms to

[PATCH 0/3] mmc: sh_mobile_sdhi: Add r7s72100 support

For the most part, the SDHI controller in the RZ/A1 (r7s72100) is the same as other Renesas SoC...except for the fact that the data port register was widened to 32-bits and the 16-bit accesses in the current tmio driver aren't going to cut it. Also, the tmio driver allows you to pass in what

[PATCH 2/3] mmc: tmio-mmc: add support for 32bit data port

For the r7s72100 SOC, the DATA_PORT register was change to be 32-bits wide. Therefore a new flag has been created that will allow 32-bit reads/writes to the DATA_PORT register instead of 16-bit (because 16-bits accesses are not supported). Signed-off-by: Chris Brandt

Re: [PATCH 3/3] pinctrl: sh-pfc: r8a7794: Implement voltage switching for SDHI

On Fri, Sep 09, 2016 at 10:08:03AM +0200, Geert Uytterhoeven wrote: > Hi Simon, > > On Thu, Sep 8, 2016 at 1:36 PM, Simon Horman > wrote: > > All the SHDIs can operate with either 3.3V or 1.8V signals, depending > > on negotiation with the card. > > > > Based on work

Re: [PATCH 2/3] pinctrl: sh-pfc: r8a7791: Implement voltage switching for SDHI

On Fri, Sep 09, 2016 at 09:52:20AM +0200, Geert Uytterhoeven wrote: > Hi Simon, > > On Thu, Sep 8, 2016 at 1:36 PM, Simon Horman > wrote: > > All the SHDIs can operate with either 3.3V or 1.8V signals, depending > > on negotiation with the card. > > > > Based on work

Re: [PATCH 3/3] pinctrl: sh-pfc: r8a7794: Implement voltage switching for SDHI

> > +static int r8a7794_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, > > u32 *pocctrl) > > +{ > > + if (pin < RCAR_GP_PIN(6, 0) || pin > RCAR_GP_PIN(6, 23)) > > + return -EINVAL; > > + > > + *pocctrl = 0xe606006c; > > + > > + /* GP6_16-23 -> bits 31-24 of

Re: [PATCH] pinctrl: sh-pfc: r8a7796: Add voltage switch operations for SDHI

On Thu, Sep 08, 2016 at 01:57:33PM +0200, Simon Horman wrote: > This patch supports the {get,set}_io_voltage operations of SDHI. > > This operates the POCCTRL0 register on R8A7796 SoC and makes 1.8v/3.3v > voltage switch. > > Based on work by Takeshi Kihara and Wolfram Sang. > > Cc: Wolfram

Re: [PATCH] i2c: mux: demux-pinctrl: run properly with multiple instances

> > > Simon: I think you can retest your demuxer-dts-series now. > > > > Simon: you think we can get that into 4.9? Would be awesome. > > Sorry, this slipped through the cracks. > Lets aim for v4.10. A ;) Ok, will update the todo. signature.asc Description: PGP signature

Re: [PATCH 6/8] clocksource: sh_cmt: Support separate R-car Gen3 CMT0/1

Hi Bui Duc, Thank you for the patch. On Friday 09 Sep 2016 20:43:12 bd-p...@jinso.co.jp wrote: > From: Bui Duc Phuc > > Add support for the new R-Car Gen3 CMT0 and CMT1 bindings. > > Signed-off-by: Bui Duc Phuc > --- > drivers/clocksource/sh_cmt.c |

Re: [PATCH 7/8] clocksource: Kconfig: Modify CMT config support 64bit

Hi Bui Duc, Thank you for the patch. On Friday 09 Sep 2016 20:43:13 bd-p...@jinso.co.jp wrote: > From: Bui Duc Phuc > > Modify CMT config to support 64bit > > Signed-off-by: Bui Duc Phuc > --- > drivers/clocksource/Kconfig | 2 +- > 1 file changed,

Re: [PATCH 7/8] clocksource: Kconfig: Modify CMT config support 64bit

Hi Sergei Thanks for your comment. +bool "Renesas CMT timer driver" if ( ARM64 || COMPILE_TEST ) Parens not needed and the spaces after/before them even less so. OK I will update in V2 Thanks & best regards. Bui Duc Phuc

Re: [PATCH 1/8] devicetree: binding: R-car Gen3 CMT0 and CMT1 bindings

Hi Phuc-san, On Fri, Sep 9, 2016 at 1:43 PM, wrote: > Add documentation for new separate CMT0 and CMT1 DT compatible strings > for R-Car Gen3. > > Signed-off-by: Bui Duc Phuc > --- > Documentation/devicetree/bindings/timer/renesas,cmt.txt | 2 ++ > 1

[PATCH] v4l: rcar-fcp: Extend compatible list to support the FDP

From: Kieran Bingham The FCP must be powered up for the FDP1 to function, even when the FDP1 does not make use of the FCNL features. Extend the compatible list to allow us to use the power domain and runtime-pm support. Signed-off-by: Kieran Bingham

Re: [PATCH 7/8] clocksource: Kconfig: Modify CMT config support 64bit

On 9/9/2016 2:43 PM, bd-p...@jinso.co.jp wrote: From: Bui Duc Phuc Modify CMT config to support 64bit Signed-off-by: Bui Duc Phuc --- drivers/clocksource/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git

[PATCH 4/8] clk: renesas: r8a7795: Add CMT clocks

From: Bui Duc Phuc This patch adds CMT module clocks for r8a7795 SoC. Signed-off-by: Bui Duc Phuc --- drivers/clk/renesas/r8a7795-cpg-mssr.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c

[PATCH 7/8] clocksource: Kconfig: Modify CMT config support 64bit

From: Bui Duc Phuc Modify CMT config to support 64bit Signed-off-by: Bui Duc Phuc --- drivers/clocksource/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index

[PATCH 3/8] ARM64: dts: r8a7796: Add CMT device to DT

From: Bui Duc Phuc Add the CMT0 and CMT1 counters to the r8a7796 device tree Signed-off-by: Bui Duc Phuc --- arch/arm64/boot/dts/renesas/r8a7796.dtsi | 30 ++ 1 file changed, 30 insertions(+) diff --git

[PATCH 2/8] ARM64: dts: r8a7795: Add CMT device to DT

From: Bui Duc Phuc Add the CMT0 and CMT1 counters to the r8a7795 device tree Signed-off-by: Bui Duc Phuc --- arch/arm64/boot/dts/renesas/r8a7795.dtsi | 30 ++ 1 file changed, 30 insertions(+) diff --git

[PATCH 1/8] devicetree: binding: R-car Gen3 CMT0 and CMT1 bindings

From: Bui Duc Phuc Add documentation for new separate CMT0 and CMT1 DT compatible strings for R-Car Gen3. Signed-off-by: Bui Duc Phuc --- Documentation/devicetree/bindings/timer/renesas,cmt.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git

[PATCH 6/8] clocksource: sh_cmt: Support separate R-car Gen3 CMT0/1

From: Bui Duc Phuc Add support for the new R-Car Gen3 CMT0 and CMT1 bindings. Signed-off-by: Bui Duc Phuc --- drivers/clocksource/sh_cmt.c | 21 +++-- 1 file changed, 19 insertions(+), 2 deletions(-) diff --git

[PATCH 0/8] clocksource: sh_cmt: Add R-car Gen3 CMT0/1 support

From: Bui Duc Phuc Hi, These are my first patches which will be added CMT driver for support R-car Gen3 series (r8a7795 and r8a7796). Please consider these patches. Best regards. Bui Duc Phuc (8): devicetree: binding: R-car Gen3 CMT0 and CMT1 bindings ARM64: dts:

[PATCH 5/8] clk: renesas: r8a7796: Add CMT clocks

From: Bui Duc Phuc This patch adds CMT module clocks for r8a7796 SoC. Signed-off-by: Bui Duc Phuc --- drivers/clk/renesas/r8a7796-cpg-mssr.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c

[PATCH 8/8] ARM64: defconfig: Enable SH_TIMER_CMT config option

From: Bui Duc Phuc Enable SH CMT driver for R-car Gen3 : SH_TIMER_CMT Signed-off-by: Bui Duc Phuc --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index

Re: [PATCH] mmc: sh_mobile_sdhi: Add r8a7796 support

On 6 September 2016 at 12:38, Simon Horman wrote: > From: Ai Kyuse > > Add support for r8a7796 SoC. > > Signed-off-by: Ai Kyuse > Signed-off-by: Simon Horman > Reviewed-by: Geert

Re: [PATCH 2/2] mmc: host: sh_mobile_sdhi: don't populate unneeded functions

On 5 September 2016 at 10:18, Wolfram Sang wrote: > >> > It can be argued that this tag could be added: >> > >> > Fixes: 452e5eef6d311e ("mmc: tmio: Add UHS-I mode support") >> > >> > I don't know how well it applies, though, because the code has been >> > modified a lot

Re: [PATCH] pinctrl: sh-pfc: r8a7796: Add voltage switch operations for SDHI

On Thu, Sep 8, 2016 at 1:57 PM, Simon Horman wrote: > This patch supports the {get,set}_io_voltage operations of SDHI. > > This operates the POCCTRL0 register on R8A7796 SoC and makes 1.8v/3.3v > voltage switch. > > Based on work by Takeshi Kihara and Wolfram Sang. > >

Re: [PATCH 3/3] pinctrl: sh-pfc: r8a7794: Implement voltage switching for SDHI

Hi Simon, On Thu, Sep 8, 2016 at 1:36 PM, Simon Horman wrote: > All the SHDIs can operate with either 3.3V or 1.8V signals, depending > on negotiation with the card. > > Based on work by Wolfram Sang for the r8a7790. > > Cc: Wolfram Sang

Re: [PATCH 2/3] pinctrl: sh-pfc: r8a7791: Implement voltage switching for SDHI

Hi Simon, On Thu, Sep 8, 2016 at 1:36 PM, Simon Horman wrote: > All the SHDIs can operate with either 3.3V or 1.8V signals, depending > on negotiation with the card. > > Based on work by Wolfram Sang for the r8a7790. > > Cc: Wolfram Sang

Re: [PATCH 1/3] pinctrl: sh-pfc: Add PORT_GP_24 helper macro

Hi Simon, On Thu, Sep 8, 2016 at 1:36 PM, Simon Horman wrote: > This follows the style of existing PORT_GP_X macros and > will be used by a follow-up patch for the r8a7791 SoC. > > Signed-off-by: Simon Horman > --- >

Re: [PATCH v3 07/10] v4l: fdp1: Remove unused struct fdp1_v4l2_buffer

On 07/09/16 23:25, Laurent Pinchart wrote: > The structure is not used, remove it. Ahh yes, looks like a left over from my first attempt at serialising input fields. Reviewed-by: Kieran Bingham > Signed-off-by: Laurent Pinchart

Re: [PATCH] i2c: mux: demux-pinctrl: run properly with multiple instances

On Thu, Sep 08, 2016 at 04:50:27PM +0200, Wolfram Sang wrote: > On Tue, Aug 23, 2016 at 05:28:03PM +0200, Wolfram Sang wrote: > > We can't use a static property for all the changesets, so we now create > > dynamic ones for each changeset. > > > > Signed-off-by: Wolfram Sang