[PATCH 11/11] arm64: dts: renesas: condor: add EtherAVB support

2018-02-02 Thread Sergei Shtylyov 
Define the Condor board dependent part of the EtherAVB device node.

Based  on the original (and large) patch by Vladimir Barinov.

Signed-off-by: Vladimir Barinov 
Signed-off-by: Sergei Shtylyov 

---
 arch/arm64/boot/dts/renesas/r8a77980-condor.dts |   11 +++
 1 file changed, 11 insertions(+)

Index: renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
===
--- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
+++ renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
@@ -15,6 +15,7 @@
 
aliases {
serial0 = 
+   ethernet0 = 
};
 
chosen {
@@ -28,6 +29,16 @@
};
 };
 
+ {
+   phy-handle = <>;
+   status = "okay";
+
+   phy0: ethernet-phy@0 {
+   rxc-skew-ps = <1500>;
+   reg = <0>;
+   };
+};
+
 _clk {
clock-frequency = <1666>;
 };

[PATCH 10/11] arm64: dts: renesas: initial Condor board device tree

2018-02-02 Thread Sergei Shtylyov 
Add the initial device  tree for  the R8A77980 SoC based Condor board.
The board has 1 debug serial port (SCIF0); include support for it, so
that the serial console can work.

Based on the original (and large) patch by Vladimir Barinov.

Signed-off-by: Vladimir Barinov 
Signed-off-by: Sergei Shtylyov 

---
 arch/arm64/boot/dts/renesas/Makefile|1 
 arch/arm64/boot/dts/renesas/r8a77980-condor.dts |   46 
 2 files changed, 47 insertions(+)

Index: renesas/arch/arm64/boot/dts/renesas/Makefile
===
--- renesas.orig/arch/arm64/boot/dts/renesas/Makefile
+++ renesas/arch/arm64/boot/dts/renesas/Makefile
@@ -8,4 +8,5 @@ dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-sa
 dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-m3ulcb-kf.dtb
 dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-xs.dtb
 dtb-$(CONFIG_ARCH_R8A77970) += r8a77970-eagle.dtb r8a77970-v3msk.dtb
+dtb-$(CONFIG_ARCH_R8A77980) += r8a77980-condor.dtb
 dtb-$(CONFIG_ARCH_R8A77995) += r8a77995-draak.dtb
Index: renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
===
--- /dev/null
+++ renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
@@ -0,0 +1,46 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the Condor board
+ *
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ * Copyright (C) 2018 Cogent Embedded, Inc.
+ */
+
+/dts-v1/;
+#include "r8a77980.dtsi"
+
+/ {
+   model = "Renesas Condor board based on r8a77980";
+   compatible = "renesas,condor", "renesas,r8a77980";
+
+   aliases {
+   serial0 = 
+   };
+
+   chosen {
+   stdout-path = "serial0:115200n8";
+   };
+
+   memory@4800 {
+   device_type = "memory";
+   /* first 128MB is reserved for secure area. */
+   reg = <0x0 0x4800 0x0 0x3800>;
+   };
+};
+
+_clk {
+   clock-frequency = <1666>;
+};
+
+_clk {
+   clock-frequency = <32768>;
+};
+
+ {
+   status = "okay";
+};
+
+_clk {
+   clock-frequency = <14745600>;
+   status = "okay";
+};

[PATCH 09/11] DT: arm: shmobile: document Condor board bindings

2018-02-02 Thread Sergei Shtylyov 
Document the Condor device tree bindings, listing it as a supported board.

This allows to use checkpatch.pl to validate .dts files referring to the
Condor board.

Signed-off-by: Sergei Shtylyov 

---
 Documentation/devicetree/bindings/arm/shmobile.txt |2 ++
 1 file changed, 2 insertions(+)

Index: renesas/Documentation/devicetree/bindings/arm/shmobile.txt
===
--- renesas.orig/Documentation/devicetree/bindings/arm/shmobile.txt
+++ renesas/Documentation/devicetree/bindings/arm/shmobile.txt
@@ -59,6 +59,8 @@ Boards:
 compatible = "renesas,blanche", "renesas,r8a7792"
   - BOCK-W
 compatible = "renesas,bockw", "renesas,r8a7778"
+  - Condor (RTP0RC77980SEB0010SS/RTP0RC77980SEB0010SA01)
+compatible = "renesas,condor", "renesas,r8a77980"
   - Draak (RTP0RC77995SEB0010S)
 compatible = "renesas,draak", "renesas,r8a77995"
   - Eagle (RTP0RC77970SEB0010S)

[PATCH 08/11] arm64: dts: renesas: r8a77980: add EtherAVB support

2018-02-02 Thread Sergei Shtylyov 
Define the generic R8A77980 part of the EtherAVB device node.

Based on the original (and large) patch by Vladimir Barinov.

Signed-off-by: Vladimir Barinov 
Signed-off-by: Sergei Shtylyov 

---
 arch/arm64/boot/dts/renesas/r8a77980.dtsi |   44 ++
 1 file changed, 44 insertions(+)

Index: renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
===
--- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi
+++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
@@ -164,6 +164,50 @@
status = "disabled";
};
 
+   avb: ethernet@e680 {
+   compatible = "renesas,etheravb-r8a77980",
+"renesas,etheravb-rcar-gen3";
+   reg = <0 0xe680 0 0x800>, <0 0xe6a0 0 0x1>;
+   interrupts = ,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+;
+   interrupt-names = "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14", "ch15",
+ "ch16", "ch17", "ch18", "ch19",
+ "ch20", "ch21", "ch22", "ch23",
+ "ch24";
+   clocks = < CPG_MOD 812>;
+   power-domains = < 32>;
+   resets = < 812>;
+   phy-mode = "rgmii-id";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   };
+
scif0: serial@e6e6 {
compatible = "renesas,scif-r8a77980",
 "renesas,rcar-gen3-scif",

[PATCH 07/11] arm64: dts: renesas: r8a77980: add [H]SCIF support

2018-02-02 Thread Sergei Shtylyov 
Describe [H]SCIF ports in the R8A77980 device tree.

Based on the original (and large) patch by Vladimir Barinov.

Signed-off-by: Vladimir Barinov 
Signed-off-by: Sergei Shtylyov 

---
 arch/arm64/boot/dts/renesas/r8a77980.dtsi |  151 ++
 1 file changed, 151 insertions(+)

Index: renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
===
--- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi
+++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
@@ -56,6 +56,13 @@
method = "smc";
};
 
+   /* External SCIF clock - to be overridden by boards that provide it */
+   scif_clk: scif {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   clock-frequency = <0>;
+   };
+
soc {
compatible = "simple-bus";
interrupt-parent = <>;
@@ -85,6 +92,150 @@
#power-domain-cells = <1>;
};
 
+   hscif0: serial@e654 {
+   compatible = "renesas,hscif-r8a77980",
+"renesas,rcar-gen3-hscif",
+"renesas,hscif";
+   reg = <0 0xe654 0 0x60>;
+   interrupts = ;
+   clocks = < CPG_MOD 520>,
+< CPG_CORE 16>,
+<_clk>;
+   clock-names = "fck", "brg_int", "scif_clk";
+   dmas = < 0x31>, < 0x30>,
+  < 0x31>, < 0x30>;
+   dma-names = "tx", "rx", "tx", "rx";
+   power-domains = < 32>;
+   resets = < 520>;
+   status = "disabled";
+   };
+
+   hscif1: serial@e655 {
+   compatible = "renesas,hscif-r8a77980",
+"renesas,rcar-gen3-hscif",
+"renesas,hscif";
+   reg = <0 0xe655 0 0x60>;
+   interrupts = ;
+   clocks = < CPG_MOD 519>,
+< CPG_CORE 16>,
+<_clk>;
+   clock-names = "fck", "brg_int", "scif_clk";
+   dmas = < 0x33>, < 0x32>,
+  < 0x33>, < 0x32>;
+   dma-names = "tx", "rx", "tx", "rx";
+   power-domains = < 32>;
+   resets = < 519>;
+   status = "disabled";
+   };
+
+   hscif2: serial@e656 {
+   compatible = "renesas,hscif-r8a77980",
+"renesas,rcar-gen3-hscif",
+"renesas,hscif";
+   reg = <0 0xe656 0 0x60>;
+   interrupts = ;
+   clocks = < CPG_MOD 518>,
+< CPG_CORE 16>,
+<_clk>;
+   clock-names = "fck", "brg_int", "scif_clk";
+   dmas = < 0x35>, < 0x34>,
+  < 0x35>, < 0x34>;
+   dma-names = "tx", "rx", "tx", "rx";
+   power-domains = < 32>;
+   resets = < 518>;
+   status = "disabled";
+   };
+
+   hscif3: serial@e66a {
+   compatible = "renesas,hscif-r8a77980",
+"renesas,rcar-gen3-hscif",
+"renesas,hscif";
+   reg = <0 0xe66a 0 0x60>;
+   interrupts = ;
+   clocks = < CPG_MOD 517>,
+< CPG_CORE 16>,
+<_clk>;
+   clock-names = "fck", "brg_int", "scif_clk";
+   dmas = < 0x37>, < 0x36>,
+  < 0x37>, < 0x36>;
+   dma-names = "tx", "rx", "tx", "rx";
+   power-domains = < 32>;
+   resets = < 517>;
+   status = "disabled";
+   };
+
+   scif0: serial@e6e6 {
+   compatible = "renesas,scif-r8a77980",
+"renesas,rcar-gen3-scif",
+"renesas,scif";
+   reg = <0 0xe6e6 0 0x40>;
+   interrupts = ;
+   clocks = < CPG_MOD 207>,
+< CPG_CORE 16>,
+<_clk>;
+   clock-names = "fck", "brg_int", "scif_clk";
+   dmas = < 0x51>, <

[PATCH 06/11] arm64: dts: renesas: r8a77980: add SYS-DMAC support

2018-02-02 Thread Sergei Shtylyov 
Describe SYS-DMAC1/2 in the R8A77980 device tree.

Based on the original (and large) patch by Vladimir Barinov.

Signed-off-by: Vladimir Barinov 
Signed-off-by: Sergei Shtylyov 

---
 arch/arm64/boot/dts/renesas/r8a77980.dtsi |   68 ++
 1 file changed, 68 insertions(+)

Index: renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
===
--- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi
+++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
@@ -85,6 +85,74 @@
#power-domain-cells = <1>;
};
 
+   dmac1: dma-controller@e730 {
+   compatible = "renesas,dmac-r8a77980",
+"renesas,rcar-dmac";
+   reg = <0 0xe730 0 0x1>;
+   interrupts = ;
+   interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14", "ch15";
+   clocks = < CPG_MOD 218>;
+   clock-names = "fck";
+   power-domains = < 32>;
+   resets = < 218>;
+   #dma-cells = <1>;
+   dma-channels = <16>;
+   };
+
+   dmac2: dma-controller@e731 {
+   compatible = "renesas,dmac-r8a77980",
+"renesas,rcar-dmac";
+   reg = <0 0xe731 0 0x1>;
+   interrupts = ;
+   interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14", "ch15";
+   clocks = < CPG_MOD 217>;
+   clock-names = "fck";
+   power-domains = < 32>;
+   resets = < 217>;
+   #dma-cells = <1>;
+   dma-channels = <16>;
+   };
+
gic: interrupt-controller@f101 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;

[PATCH 05/11] arm64: dts: renesas: initial R8A77980 SoC device tree

2018-02-02 Thread Sergei Shtylyov 
The initial R8A77980 SoC device tree including Cortex-A53 CPU, GIC, timer,
CPG, RST, and SYSC.

Based on the original (and large) patch by Vladimir Barinov.

Signed-off-by: Vladimir Barinov 
Signed-off-by: Sergei Shtylyov 

---
 arch/arm64/boot/dts/renesas/r8a77980.dtsi |  122 ++
 1 file changed, 122 insertions(+)

Index: renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
===
--- /dev/null
+++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
@@ -0,0 +1,122 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the r8a77980 SoC
+ *
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ * Copyright (C) 2018 Cogent Embedded, Inc.
+ */
+
+#include 
+#include 
+#include 
+
+/ {
+   compatible = "renesas,r8a77980";
+   #address-cells = <2>;
+   #size-cells = <2>;
+
+   cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   a53_0: cpu@0 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a53", "arm,armv8";
+   reg = <0>;
+   clocks = < CPG_CORE 0>;
+   power-domains = < 5>;
+   next-level-cache = <_CA53>;
+   enable-method = "psci";
+   };
+
+   L2_CA53: cache-controller {
+   compatible = "cache";
+   power-domains = < 21>;
+   cache-unified;
+   cache-level = <2>;
+   };
+   };
+
+   extal_clk: extal {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   /* This value must be overridden by the board */
+   clock-frequency = <0>;
+   };
+
+   extalr_clk: extalr {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   /* This value must be overridden by the board */
+   clock-frequency = <0>;
+   };
+
+   psci {
+   compatible = "arm,psci-1.0", "arm,psci-0.2";
+   method = "smc";
+   };
+
+   soc {
+   compatible = "simple-bus";
+   interrupt-parent = <>;
+
+   #address-cells = <2>;
+   #size-cells = <2>;
+   ranges;
+
+   cpg: clock-controller@e615 {
+   compatible = "renesas,r8a77980-cpg-mssr";
+   reg = <0 0xe615 0 0x1000>;
+   clocks = <_clk>, <_clk>;
+   clock-names = "extal", "extalr";
+   #clock-cells = <2>;
+   #power-domain-cells = <0>;
+   #reset-cells = <1>;
+   };
+
+   rst: reset-controller@e616 {
+   compatible = "renesas,r8a77980-rst";
+   reg = <0 0xe616 0 0x200>;
+   };
+
+   sysc: system-controller@e618 {
+   compatible = "renesas,r8a77980-sysc";
+   reg = <0 0xe618 0 0x440>;
+   #power-domain-cells = <1>;
+   };
+
+   gic: interrupt-controller@f101 {
+   compatible = "arm,gic-400";
+   #interrupt-cells = <3>;
+   #address-cells = <0>;
+   interrupt-controller;
+   reg = <0x0 0xf101 0 0x1000>,
+ <0x0 0xf102 0 0x2>,
+ <0x0 0xf104 0 0x2>,
+ <0x0 0xf106 0 0x2>;
+   interrupts = ;
+   clocks = < CPG_MOD 408>;
+   clock-names = "clk";
+   power-domains = < 32>;
+   resets = < 408>;
+   };
+
+   prr: chipid@fff00044 {
+   compatible = "renesas,prr";
+   reg = <0 0xfff00044 0 4>;
+   };
+   };
+
+   timer {
+   compatible = "arm,armv8-timer";
+   interrupts-extended = < GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) |
+  IRQ_TYPE_LEVEL_LOW)>,
+ < GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) |
+  IRQ_TYPE_LEVEL_LOW)>,
+ < GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) |
+  IRQ_TYPE_LEVEL_LOW)>,
+ < GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) |
+  IRQ_TYPE_LEVEL_LOW)>;
+   };
+};

[PATCH 03/11] dt-bindings: power: add R8A77980 SYSC power domain definitions

2018-02-02 Thread Sergei Shtylyov 
Add macros usable by the device tree sources to reference R8A77980 SYSC
power domains by index.

Based on the original (and large) patch by Vladimir Barinov.

Signed-off-by: Vladimir Barinov 
Signed-off-by: Sergei Shtylyov 

---
 include/dt-bindings/power/r8a77980-sysc.h |   43 ++
 1 file changed, 43 insertions(+)

Index: renesas/include/dt-bindings/power/r8a77980-sysc.h
===
--- /dev/null
+++ renesas/include/dt-bindings/power/r8a77980-sysc.h
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ * Copyright (C) 2018 Cogent Embedded, Inc.
+ */
+#ifndef __DT_BINDINGS_POWER_R8A77980_SYSC_H__
+#define __DT_BINDINGS_POWER_R8A77980_SYSC_H__
+
+/*
+ * These power domain indices match the numbers of the interrupt bits
+ * representing the power areas in the various Interrupt Registers
+ * (e.g. SYSCISR, Interrupt Status Register)
+ */
+
+#define R8A77980_PD_A2SC2  0
+#define R8A77980_PD_A2SC3  1
+#define R8A77980_PD_A2SC4  2
+#define R8A77980_PD_A2PD0  3
+#define R8A77980_PD_A2PD1  4
+#define R8A77980_PD_CA53_CPU0  5
+#define R8A77980_PD_CA53_CPU1  6
+#define R8A77980_PD_CA53_CPU2  7
+#define R8A77980_PD_CA53_CPU3  8
+#define R8A77980_PD_A2CN   10
+#define R8A77980_PD_A3VIP  11
+#define R8A77980_PD_A2IR5  12
+#define R8A77980_PD_CR713
+#define R8A77980_PD_A2IR4  15
+#define R8A77980_PD_CA53_SCU   21
+#define R8A77980_PD_A2IR0  23
+#define R8A77980_PD_A3IR   24
+#define R8A77980_PD_A3VIP1 25
+#define R8A77980_PD_A3VIP2 26
+#define R8A77980_PD_A2IR1  27
+#define R8A77980_PD_A2IR2  28
+#define R8A77980_PD_A2IR3  29
+#define R8A77980_PD_A2SC0  30
+#define R8A77980_PD_A2SC1  31
+
+/* Always-on power area */
+#define R8A77980_PD_ALWAYS_ON  32
+
+#endif /* __DT_BINDINGS_POWER_R8A77980_SYSC_H__ */

[PATCH 02/11] soc: renesas: rcar-rst: add R8A77980 support

2018-02-02 Thread Sergei Shtylyov 
Add support for R-Car V3H (R8A77980) to the R-Car RST driver -- this driver
is  needed  for the clock driver to work.

Signed-off-by: Sergei Shtylyov 

---
 Documentation/devicetree/bindings/reset/renesas,rst.txt |1 +
 drivers/soc/renesas/Kconfig |2 +-
 drivers/soc/renesas/rcar-rst.c  |1 +
 3 files changed, 3 insertions(+), 1 deletion(-)

Index: renesas/Documentation/devicetree/bindings/reset/renesas,rst.txt
===
--- renesas.orig/Documentation/devicetree/bindings/reset/renesas,rst.txt
+++ renesas/Documentation/devicetree/bindings/reset/renesas,rst.txt
@@ -27,6 +27,7 @@ Required properties:
  - "renesas,r8a7795-rst" (R-Car H3)
  - "renesas,r8a7796-rst" (R-Car M3-W)
  - "renesas,r8a77970-rst" (R-Car V3M)
+ - "renesas,r8a77980-rst" (R-Car V3H)
  - "renesas,r8a77995-rst" (R-Car D3)
   - reg: Address start and address range for the device.
 
Index: renesas/drivers/soc/renesas/Kconfig
===
--- renesas.orig/drivers/soc/renesas/Kconfig
+++ renesas/drivers/soc/renesas/Kconfig
@@ -4,7 +4,7 @@ config SOC_RENESAS
select SOC_BUS
select RST_RCAR if ARCH_RCAR_GEN1 || ARCH_RCAR_GEN2 || \
   ARCH_R8A7795 || ARCH_R8A7796 || ARCH_R8A77970 || \
-  ARCH_R8A77995
+  ARCH_R8A77980 || ARCH_R8A77995
select SYSC_R8A7743 if ARCH_R8A7743
select SYSC_R8A7745 if ARCH_R8A7745
select SYSC_R8A7779 if ARCH_R8A7779
Index: renesas/drivers/soc/renesas/rcar-rst.c
===
--- renesas.orig/drivers/soc/renesas/rcar-rst.c
+++ renesas/drivers/soc/renesas/rcar-rst.c
@@ -42,6 +42,7 @@ static const struct of_device_id rcar_rs
{ .compatible = "renesas,r8a7795-rst", .data = _rst_gen2 },
{ .compatible = "renesas,r8a7796-rst", .data = _rst_gen2 },
{ .compatible = "renesas,r8a77970-rst", .data = _rst_gen2 },
+   { .compatible = "renesas,r8a77980-rst", .data = _rst_gen2 },
{ .compatible = "renesas,r8a77995-rst", .data = _rst_gen2 },
{ /* sentinel */ }
 };

[PATCH 01/11] soc: renesas: identify R-Car V3H

2018-02-02 Thread Sergei Shtylyov 
Add support for identifying the R-Car V3H (R8A77980) SoC.

Signed-off-by: Sergei Shtylyov 

---
 drivers/soc/renesas/renesas-soc.c |8 
 1 file changed, 8 insertions(+)

Index: renesas/drivers/soc/renesas/renesas-soc.c
===
--- renesas.orig/drivers/soc/renesas/renesas-soc.c
+++ renesas/drivers/soc/renesas/renesas-soc.c
@@ -149,6 +149,11 @@ static const struct renesas_soc soc_rcar
.id = 0x54,
 };
 
+static const struct renesas_soc soc_rcar_v3h __initconst __maybe_unused = {
+   .family = _rcar_gen3,
+   .id = 0x56,
+};
+
 static const struct renesas_soc soc_rcar_d3 __initconst __maybe_unused = {
.family = _rcar_gen3,
.id = 0x58,
@@ -212,6 +217,9 @@ static const struct of_device_id renesas
 #ifdef CONFIG_ARCH_R8A77970
{ .compatible = "renesas,r8a77970", .data = _rcar_v3m },
 #endif
+#ifdef CONFIG_ARCH_R8A77980
+   { .compatible = "renesas,r8a77980", .data = _rcar_v3h },
+#endif
 #ifdef CONFIG_ARCH_R8A77995
{ .compatible = "renesas,r8a77995", .data = _rcar_d3 },
 #endif

[PATCH 00/11] Add R8A77980/Condor board support

2018-02-02 Thread Sergei Shtylyov 
Hello!

Here's the set of 11 patches against Simon Horman's 'renesas.git' repo's
'renesas-devel-20180202-v4.15' tag. I'm adding the device tree support for
the R8A77980-based Condor board (note that NFS root would only work on the
Condor boards [re]wired for booting from EtherAVB -- we haven't been able
to get the 'sh_eth' driver working in either U-Boot or Linux so far).
The necessary SYS-DMAC, [H]SCIF, and EtherAVB bindings updates have been
posted yesterday, the clock driver was posted the day before...

[01/11] soc: renesas: identify R-Car V3H
[02/11] soc: renesas: rcar-rst: add R8A77980 support
[03/11] dt-bindings: power: add R8A77980 SYSC power domain definitions
[04/11] soc: renesas: rcar-sysc: add R8A77980 support
[05/11] arm64: dts: renesas: initial R8A77980 SoC device tree
[06/11] arm64: dts: renesas: r8a77980: add SYS-DMAC support
[07/11] arm64: dts: renesas: r8a77980: add [H]SCIF support
[08/11] arm64: dts: renesas: r8a77980: add EtherAVB support
[09/11] DT: arm: shmobile: document Condor board bindings
[10/11] arm64: dts: renesas: initial Condor board device tree
[11/11] arm64: dts: renesas: condor: add EtherAVB support

WBR, Sergei

[PATCH] dmaengine: rcar-dmac: Check the done lists in rcar_dmac_chan_get_residue()

2018-02-02 Thread Yoshihiro Shimoda 
This patch fixes an issue that a race condition happens between a client
driver and the rcar-dmac driver:

- The rcar_dmac_isr_transfer_end() is called.
 - The done list appears, and desc.running is the next active list.
- rcar_dmac_chan_get_residue() is called by a client driver before
  rcar_dmac_isr_channel_thread() is called.
 - The rcar_dmac_chan_get_residue() will not find any descriptors.
 - And, the following WARNING happens:
WARN(1, "No descriptor for cookie!");

The sh-sci driver with HSCIF (921,600bps) on R-Car H3 can cause this
situation.
So, this patch checks the done lists in rcar_dmac_chan_get_residue()
and returns zero if the done lists has the argument cookie.

Tested-by: Nguyen Viet Dung 
Signed-off-by: Yoshihiro Shimoda 
---
 drivers/dma/sh/rcar-dmac.c | 9 +
 1 file changed, 9 insertions(+)

diff --git a/drivers/dma/sh/rcar-dmac.c b/drivers/dma/sh/rcar-dmac.c
index 2b2c7db..f748be6 100644
--- a/drivers/dma/sh/rcar-dmac.c
+++ b/drivers/dma/sh/rcar-dmac.c
@@ -1264,8 +1264,17 @@ static unsigned int rcar_dmac_chan_get_residue(struct 
rcar_dmac_chan *chan,
 * If the cookie doesn't correspond to the currently running transfer
 * then the descriptor hasn't been processed yet, and the residue is
 * equal to the full descriptor size.
+* Also, a client driver is possible to call this function before
+* rcar_dmac_isr_channel_thread() runs. In this case, the "desc.running"
+* will be the next descriptor, and the done list will appear. So, if
+* the argument cookie matches the done list's cookie, we can assume
+* the residue is zero.
 */
if (cookie != desc->async_tx.cookie) {
+   list_for_each_entry(desc, >desc.done, node) {
+   if (cookie == desc->async_tx.cookie)
+   return 0;
+   }
list_for_each_entry(desc, >desc.pending, node) {
if (cookie == desc->async_tx.cookie)
return desc->size;
-- 
1.9.1

Re: [PATCH topic/renesas_defconfig] arm64: renesas_defconfig: enable R8A77970 SoC

2018-02-02 Thread Geert Uytterhoeven 
On Fri, Feb 2, 2018 at 10:36 AM, Simon Horman
<horms+rene...@verge.net.au> wrote:
> Enable the Renesas R-Car V3H (R8A77970) SoC in the ARM64 renesas_defconfig.

R8A77980...

> Signed-off-by: Simon Horman <horms+rene...@verge.net.au>
> ---
>  arch/arm64/configs/renesas_defconfig | 1 +
>  1 file changed, 1 insertion(+)
>
>  Based on renesas-devel-20180202-v4.15
>
>  Not for upstream merge
>
> diff --git a/arch/arm64/configs/renesas_defconfig 
> b/arch/arm64/configs/renesas_defconfig
> index 3087bba06d3c..386211464efa 100644
> --- a/arch/arm64/configs/renesas_defconfig
> +++ b/arch/arm64/configs/renesas_defconfig
> @@ -34,6 +34,7 @@ CONFIG_ARCH_RENESAS=y
>  CONFIG_ARCH_R8A7795=y
>  CONFIG_ARCH_R8A7796=y
>  CONFIG_ARCH_R8A77970=y
> +CONFIG_ARCH_R8A77980=y
>  CONFIG_ARCH_R8A77995=y
>  CONFIG_PCI=y
>  CONFIG_PCIEPORTBUS=y

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

Re: [PATCH] arm64: defconfig: enable R8A77970 SoC

2018-02-02 Thread Simon Horman 
On Fri, Feb 02, 2018 at 10:55:22AM +0100, Geert Uytterhoeven wrote:
> On Fri, Feb 2, 2018 at 10:36 AM, Simon Horman
>  wrote:
> > Enable the Renesas R-Car V3H (R8A77970) SoC in the ARM64 defconfig.
> 
> Wrong subject, wrong body ;-)

Sorry, cut and paste madness.

> 
> > Signed-off-by: Simon Horman 
> > ---
> >  arch/arm64/configs/defconfig | 1 +
> >  1 file changed, 1 insertion(+)
> >
> >  Based on renesas-devel-20180130v2-v4.15
> >
> > diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
> > index 6356c6da34ea..45a423f845c7 100644
> > --- a/arch/arm64/configs/defconfig
> > +++ b/arch/arm64/configs/defconfig
> > @@ -52,6 +52,7 @@ CONFIG_ARCH_RENESAS=y
> >  CONFIG_ARCH_R8A7795=y
> >  CONFIG_ARCH_R8A7796=y
> >  CONFIG_ARCH_R8A77970=y
> > +CONFIG_ARCH_R8A77980=y
> >  CONFIG_ARCH_R8A77995=y
> >  CONFIG_ARCH_STRATIX10=y
> >  CONFIG_ARCH_TEGRA=y
> 
> Gr{oetje,eeting}s,
> 
> Geert
> 
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- 
> ge...@linux-m68k.org
> 
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like 
> that.
> -- Linus Torvalds
>

Re: [PATCH] arm64: defconfig: enable R8A77970 SoC

2018-02-02 Thread Geert Uytterhoeven 
On Fri, Feb 2, 2018 at 10:36 AM, Simon Horman
 wrote:
> Enable the Renesas R-Car V3H (R8A77970) SoC in the ARM64 defconfig.

Wrong subject, wrong body ;-)

> Signed-off-by: Simon Horman 
> ---
>  arch/arm64/configs/defconfig | 1 +
>  1 file changed, 1 insertion(+)
>
>  Based on renesas-devel-20180130v2-v4.15
>
> diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
> index 6356c6da34ea..45a423f845c7 100644
> --- a/arch/arm64/configs/defconfig
> +++ b/arch/arm64/configs/defconfig
> @@ -52,6 +52,7 @@ CONFIG_ARCH_RENESAS=y
>  CONFIG_ARCH_R8A7795=y
>  CONFIG_ARCH_R8A7796=y
>  CONFIG_ARCH_R8A77970=y
> +CONFIG_ARCH_R8A77980=y
>  CONFIG_ARCH_R8A77995=y
>  CONFIG_ARCH_STRATIX10=y
>  CONFIG_ARCH_TEGRA=y

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

[PATCH topic/renesas_defconfig] arm64: renesas_defconfig: enable R8A77970 SoC

2018-02-02 Thread Simon Horman 
Enable the Renesas R-Car V3H (R8A77970) SoC in the ARM64 renesas_defconfig.

Signed-off-by: Simon Horman <horms+rene...@verge.net.au>
---
 arch/arm64/configs/renesas_defconfig | 1 +
 1 file changed, 1 insertion(+)

 Based on renesas-devel-20180202-v4.15

 Not for upstream merge

diff --git a/arch/arm64/configs/renesas_defconfig 
b/arch/arm64/configs/renesas_defconfig
index 3087bba06d3c..386211464efa 100644
--- a/arch/arm64/configs/renesas_defconfig
+++ b/arch/arm64/configs/renesas_defconfig
@@ -34,6 +34,7 @@ CONFIG_ARCH_RENESAS=y
 CONFIG_ARCH_R8A7795=y
 CONFIG_ARCH_R8A7796=y
 CONFIG_ARCH_R8A77970=y
+CONFIG_ARCH_R8A77980=y
 CONFIG_ARCH_R8A77995=y
 CONFIG_PCI=y
 CONFIG_PCIEPORTBUS=y
-- 
2.11.0

[PATCH] arm64: defconfig: enable R8A77970 SoC

2018-02-02 Thread Simon Horman 
Enable the Renesas R-Car V3H (R8A77970) SoC in the ARM64 defconfig.

Signed-off-by: Simon Horman 
---
 arch/arm64/configs/defconfig | 1 +
 1 file changed, 1 insertion(+)

 Based on renesas-devel-20180130v2-v4.15

diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 6356c6da34ea..45a423f845c7 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -52,6 +52,7 @@ CONFIG_ARCH_RENESAS=y
 CONFIG_ARCH_R8A7795=y
 CONFIG_ARCH_R8A7796=y
 CONFIG_ARCH_R8A77970=y
+CONFIG_ARCH_R8A77980=y
 CONFIG_ARCH_R8A77995=y
 CONFIG_ARCH_STRATIX10=y
 CONFIG_ARCH_TEGRA=y
-- 
2.11.0

Re: [PATCH v2 5/5] dt-bindings: at24: add bindings for Rohm BR24T01

2018-02-02 Thread Bartosz Golaszewski 
2018-01-30 11:44 GMT+01:00 Wolfram Sang :
> On Mon, Jan 29, 2018 at 04:45:48PM +0100, Ulrich Hecht wrote:
>> Both manufacturer and name variant.
>>
>> Signed-off-by: Ulrich Hecht 
>
> Reviewed-by: Wolfram Sang 
>

Acked-by: Bartosz Golaszewski

Re: [PATCH] DT: net: renesas,ravb: document R8A77980 bindings

2018-02-02 Thread Simon Horman 
On Thu, Feb 01, 2018 at 09:27:12PM +0100, Geert Uytterhoeven wrote:
> On Thu, Feb 1, 2018 at 9:13 PM, Sergei Shtylyov
>  wrote:
> > Renesas R-Car V3H (R8A77980) SoC has the R-Car gen3 compatible EtherAVB
> > device, so document the SoC specific bindings.
> >
> > Signed-off-by: Sergei Shtylyov 
> 
> Reviewed-by: Geert Uytterhoeven 

Reviewed-by: Simon Horman

Re: [PATCH 2/2] arm64: add Renesas R8A77980 support

2018-02-02 Thread Simon Horman 
On Thu, Feb 01, 2018 at 09:02:47PM +0100, Geert Uytterhoeven wrote:
> On Wed, Jan 31, 2018 at 8:59 PM, Sergei Shtylyov
>  wrote:
> > Add a configuration option for the R-Car V3H (R8A77980) SoC.
> >
> > Based on the original (and large) patch by Vladimir Barinov.
> >
> > Signed-off-by: Vladimir Barinov 
> > Signed-off-by: Sergei Shtylyov 
> 
> Reviewed-by: Geert Uytterhoeven 

Thanks, applied.

Re: [PATCH 1/2] DT: arm: shmobile: document R8A77980 SoC bindings

2018-02-02 Thread Simon Horman 
On Thu, Feb 01, 2018 at 09:01:54PM +0100, Geert Uytterhoeven wrote:
> On Wed, Jan 31, 2018 at 8:56 PM, Sergei Shtylyov
>  wrote:
> > Document the R-Car V3H (R8A77980) SoC device tree bindings.
> >
> > Signed-off-by: Sergei Shtylyov 
> 
> Reviewed-by: Geert Uytterhoeven 
> 
> Some people may complain about the subject prefix, though.

I'm a bit unsure about what to do about prefixes for that file.
I've gone with the following which seems sensible to me.

arm64: renesas: document R8A77980 SoC bindings

Re: [PATCH] DT: serial: renesas,sci-serial: document R8A77980 bindings

2018-02-02 Thread Simon Horman 
On Thu, Feb 01, 2018 at 10:36:20PM +0300, Sergei Shtylyov wrote:
> R-Car V3H (R8A77980) SoC has the R-Car gen3 compatible SCIF and HSCIF ports,
> so document the SoC specific bindings.
> 
> Signed-off-by: Sergei Shtylyov 

Reviewed-by: Simon Horman

Re: [PATCH] DT: dma: renesas,rcar-dmac: document R8A77980 support

2018-02-02 Thread Simon Horman 
On Thu, Feb 01, 2018 at 10:09:25PM +0300, Sergei Shtylyov wrote:
> Renesas  R-Car V3H SoC has the R-Car gen3 compatible DMA controllers.
> Document R-Car V3H (also known as R8A77980) SoC bindings.
> 
> Signed-off-by: Sergei Shtylyov 

Reviewed-by: Simon Horman