[PATCH/RFT v2 0/3] thermal: add support for r8a77995

[Yoshihiro Kaneko]

This series adds thermal support for r8a77995.
R-Car D3 (r8a77995) have a thermal sensor module which is similar to Gen2.
Therefore this series adds r8a77995 support to rcar_thermal driver not
rcar_gen3_thermal driver.

This series is based on the next branch of Zhang Rui's linux tree.

v2 [Yoshihiro Kaneko]
* As suggested by Geert Uytterhoeven
rcar_thermal.c:
- remove rcar_of_data macro
- store a pointer to rcar_thermal_chip in rcar_thermal_priv
- remove unnecessary cast in rcar_thermal_dt_ids

rcar-thermal.txt:
- drop the fallback for D3
- update the paragraph about interrupts

r8a77995.dtsi:
- fix the base address and the register addresses
- drop the fallback


Yoshihiro Kaneko (3):
  thermal: rcar_thermal: add r8a77995 support
  dt-bindings: thermal: rcar-thermal: add R8A77995 support
  arm64: dts: renesas: r8a77995: add thermal device support

 .../devicetree/bindings/thermal/rcar-thermal.txt   |   7 +-
 arch/arm64/boot/dts/renesas/r8a77995.dtsi  |  30 +
 drivers/thermal/rcar_thermal.c | 148 -
 3 files changed, 151 insertions(+), 34 deletions(-)

-- 
1.9.1

[PATCH/RFT v2 1/3] thermal: rcar_thermal: add r8a77995 support

[Yoshihiro Kaneko]

Add support for R-Car D3 (r8a77995) thermal sensor.

Signed-off-by: Yoshihiro Kaneko 
---
 drivers/thermal/rcar_thermal.c | 148 -
 1 file changed, 116 insertions(+), 32 deletions(-)

diff --git a/drivers/thermal/rcar_thermal.c b/drivers/thermal/rcar_thermal.c
index 73e5fee..a631bff 100644
--- a/drivers/thermal/rcar_thermal.c
+++ b/drivers/thermal/rcar_thermal.c
@@ -58,10 +58,35 @@ struct rcar_thermal_common {
spinlock_t lock;
 };
 
+enum rcar_thermal_type {
+   RCAR_THERMAL,
+   RCAR_GEN2_THERMAL,
+   RCAR_GEN3_THERMAL,
+};
+
+struct rcar_thermal_chip {
+   int use_of_thermal;
+   enum rcar_thermal_type type;
+};
+
+static const struct rcar_thermal_chip rcar_thermal = {
+   .use_of_thermal = 0,
+   .type = RCAR_THERMAL,
+};
+static const struct rcar_thermal_chip rcar_gen2_thermal = {
+   .use_of_thermal = 1,
+   .type = RCAR_GEN2_THERMAL,
+};
+static const struct rcar_thermal_chip rcar_gen3_thermal = {
+   .use_of_thermal = 1,
+   .type = RCAR_GEN3_THERMAL,
+};
+
 struct rcar_thermal_priv {
void __iomem *base;
struct rcar_thermal_common *common;
struct thermal_zone_device *zone;
+   struct rcar_thermal_chip *chip;
struct delayed_work work;
struct mutex lock;
struct list_head list;
@@ -77,13 +102,20 @@ struct rcar_thermal_priv {
 #define rcar_priv_to_dev(priv) ((priv)->common->dev)
 #define rcar_has_irq_support(priv) ((priv)->common->base)
 #define rcar_id_to_shift(priv) ((priv)->id * 8)
-#define rcar_of_data(dev)  ((unsigned 
long)of_device_get_match_data(dev))
-#define rcar_use_of_thermal(dev)   (rcar_of_data(dev) == USE_OF_THERMAL)
 
-#define USE_OF_THERMAL 1
 static const struct of_device_id rcar_thermal_dt_ids[] = {
-   { .compatible = "renesas,rcar-thermal", },
-   { .compatible = "renesas,rcar-gen2-thermal", .data = (void 
*)USE_OF_THERMAL },
+   {
+   .compatible = "renesas,rcar-thermal",
+   .data = _thermal,
+   },
+   {
+   .compatible = "renesas,rcar-gen2-thermal",
+.data = _gen2_thermal,
+   },
+   {
+   .compatible = "renesas,thermal-r8a77995",
+   .data = _gen3_thermal,
+   },
{},
 };
 MODULE_DEVICE_TABLE(of, rcar_thermal_dt_ids);
@@ -190,7 +222,8 @@ static int rcar_thermal_update_temp(struct 
rcar_thermal_priv *priv)
 * enable IRQ
 */
if (rcar_has_irq_support(priv)) {
-   rcar_thermal_write(priv, FILONOFF, 0);
+   if (priv->chip->type != RCAR_GEN3_THERMAL)
+   rcar_thermal_write(priv, FILONOFF, 0);
 
/* enable Rising/Falling edge interrupt */
rcar_thermal_write(priv, POSNEG,  0x1);
@@ -420,7 +453,7 @@ static int rcar_thermal_remove(struct platform_device *pdev)
 
rcar_thermal_for_each_priv(priv, common) {
rcar_thermal_irq_disable(priv);
-   if (rcar_use_of_thermal(dev))
+   if (priv->chip->use_of_thermal)
thermal_remove_hwmon_sysfs(priv->zone);
else
thermal_zone_device_unregister(priv->zone);
@@ -438,6 +471,9 @@ static int rcar_thermal_probe(struct platform_device *pdev)
struct rcar_thermal_priv *priv;
struct device *dev = >dev;
struct resource *res, *irq;
+   struct rcar_thermal_chip *chip = ((struct rcar_thermal_chip *)
+ of_device_get_match_data(dev));
+   int nirq = chip->type == RCAR_GEN3_THERMAL ? 2 : 1;
int mres = 0;
int i;
int ret = -ENODEV;
@@ -457,19 +493,35 @@ static int rcar_thermal_probe(struct platform_device 
*pdev)
pm_runtime_enable(dev);
pm_runtime_get_sync(dev);
 
-   irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
-   if (irq) {
-   /*
-* platform has IRQ support.
-* Then, driver uses common registers
-* rcar_has_irq_support() will be enabled
-*/
-   res = platform_get_resource(pdev, IORESOURCE_MEM, mres++);
-   common->base = devm_ioremap_resource(dev, res);
-   if (IS_ERR(common->base))
-   return PTR_ERR(common->base);
+   for (i = 0; i < nirq; i++) {
+   irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+   if (!irq)
+   continue;
+   if (!common->base) {
+   /*
+* platform has IRQ support.
+* Then, driver uses common registers
+* rcar_has_irq_support() will be enabled
+*/
+   res = platform_get_resource(pdev, IORESOURCE_MEM,
+   mres++);
+

[PATCH/RFT v2 3/3] arm64: dts: renesas: r8a77995: add thermal device support

[Yoshihiro Kaneko]

Signed-off-by: Yoshihiro Kaneko 
---
 arch/arm64/boot/dts/renesas/r8a77995.dtsi | 30 ++
 1 file changed, 30 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi 
b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
index cff42cd..9a52b41 100644
--- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
@@ -636,5 +636,35 @@
#phy-cells = <0>;
status = "disabled";
};
+
+   thermal: thermal@e619 {
+   compatible = "renesas,thermal-r8a77995";
+   reg = <0 0xe619 0 0x10>, <0 0xe6190100 0 0x38>;
+   interrupts = ,
+,
+;
+   clocks = < CPG_MOD 522>;
+   power-domains = < R8A77995_PD_ALWAYS_ON>;
+   resets = < 522>;
+   #thermal-sensor-cells = <0>;
+   };
+   };
+
+   thermal-zones {
+   cpu_thermal: cpu-thermal {
+   polling-delay-passive = <250>;
+   polling-delay = <1000>;
+   thermal-sensors = <>;
+
+   trips {
+   cpu-crit {
+   temperature = <12>;
+   hysteresis = <2000>;
+   type = "critical";
+   };
+   };
+   cooling-maps {
+   };
+   };
};
 };
-- 
1.9.1

[PATCH/RFT v2 2/3] dt-bindings: thermal: rcar-thermal: add R8A77995 support

[Yoshihiro Kaneko]

Signed-off-by: Yoshihiro Kaneko 
---
 Documentation/devicetree/bindings/thermal/rcar-thermal.txt | 7 +--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/thermal/rcar-thermal.txt 
b/Documentation/devicetree/bindings/thermal/rcar-thermal.txt
index 349e635..5ab5fcd 100644
--- a/Documentation/devicetree/bindings/thermal/rcar-thermal.txt
+++ b/Documentation/devicetree/bindings/thermal/rcar-thermal.txt
@@ -3,7 +3,8 @@
 Required properties:
 - compatible   : "renesas,thermal-",
   "renesas,rcar-gen2-thermal" (with thermal-zone) or
-  "renesas,rcar-thermal" (without thermal-zone) as 
fallback.
+  "renesas,rcar-thermal" (without thermal-zone) as
+   fallback except R-Car D3.
  Examples with soctypes are:
- "renesas,thermal-r8a73a4" (R-Mobile APE6)
- "renesas,thermal-r8a7743" (RZ/G1M)
@@ -12,13 +13,15 @@ Required properties:
- "renesas,thermal-r8a7791" (R-Car M2-W)
- "renesas,thermal-r8a7792" (R-Car V2H)
- "renesas,thermal-r8a7793" (R-Car M2-N)
+   - "renesas,thermal-r8a77995" (R-Car D3)
 - reg  : Address range of the thermal registers.
  The 1st reg will be recognized as common register
  if it has "interrupts".
 
 Option properties:
 
-- interrupts   : use interrupt
+- interrupts   : use interrupt.
+  Should contain 3 interrupts for R-Car D3.
 
 Example (non interrupt support):
 
-- 
1.9.1

[PATCH 1/5] clk: renesas: r8a7743: Fix LB clock divider

[Geert Uytterhoeven]

The CLK_TYPE_GEN2_LB clock type is meant for SoCs like R-Car H2, where
the LB clock divider depends on the value of the MD18 pin.

On RZ/G1M, the LB clock divider is fixed to 24.  Hence model the clock
as a fixed factor clock instead.

Signed-off-by: Geert Uytterhoeven 
---
 drivers/clk/renesas/r8a7743-cpg-mssr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/renesas/r8a7743-cpg-mssr.c 
b/drivers/clk/renesas/r8a7743-cpg-mssr.c
index d3c8b1e2969fd305..011c170ec3f95d65 100644
--- a/drivers/clk/renesas/r8a7743-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7743-cpg-mssr.c
@@ -52,7 +52,6 @@ static const struct cpg_core_clk r8a7743_core_clks[] 
__initconst = {
 
/* Core Clock Outputs */
DEF_BASE("z",R8A7743_CLK_Z,CLK_TYPE_GEN2_Z, CLK_PLL0),
-   DEF_BASE("lb",   R8A7743_CLK_LB,   CLK_TYPE_GEN2_LB,CLK_PLL1),
DEF_BASE("sdh",  R8A7743_CLK_SDH,  CLK_TYPE_GEN2_SDH,   CLK_PLL1),
DEF_BASE("sd0",  R8A7743_CLK_SD0,  CLK_TYPE_GEN2_SD0,   CLK_PLL1),
DEF_BASE("qspi", R8A7743_CLK_QSPI, CLK_TYPE_GEN2_QSPI,  CLK_PLL1_DIV2),
@@ -63,6 +62,7 @@ static const struct cpg_core_clk r8a7743_core_clks[] 
__initconst = {
DEF_FIXED("zs",R8A7743_CLK_ZS,  CLK_PLL1,   6, 1),
DEF_FIXED("hp",R8A7743_CLK_HP,  CLK_PLL1,  12, 1),
DEF_FIXED("b", R8A7743_CLK_B,   CLK_PLL1,  12, 1),
+   DEF_FIXED("lb",R8A7743_CLK_LB,  CLK_PLL1,  24, 1),
DEF_FIXED("p", R8A7743_CLK_P,   CLK_PLL1,  24, 1),
DEF_FIXED("cl",R8A7743_CLK_CL,  CLK_PLL1,  48, 1),
DEF_FIXED("m2",R8A7743_CLK_M2,  CLK_PLL1,   8, 1),
-- 
2.7.4

[PATCH 5/5] clk: renesas: r8a7794: Fix LB clock divider

[Geert Uytterhoeven]

The CLK_TYPE_GEN2_LB clock type is meant for SoCs like R-Car H2, where
the LB clock divider depends on the value of the MD18 pin.

On R-Car E2, the LB clock divider is fixed to 24.  Hence model the clock
as a fixed factor clock instead.

Signed-off-by: Geert Uytterhoeven 
---
 drivers/clk/renesas/r8a7794-cpg-mssr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/renesas/r8a7794-cpg-mssr.c 
b/drivers/clk/renesas/r8a7794-cpg-mssr.c
index 2a40bbeaeeafc2a4..3ce74f063fa86b19 100644
--- a/drivers/clk/renesas/r8a7794-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7794-cpg-mssr.c
@@ -55,7 +55,6 @@ static const struct cpg_core_clk r8a7794_core_clks[] 
__initconst = {
DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
 
/* Core Clock Outputs */
-   DEF_BASE("lb",   R8A7794_CLK_LB,   CLK_TYPE_GEN2_LB,   CLK_PLL1),
DEF_BASE("adsp", R8A7794_CLK_ADSP, CLK_TYPE_GEN2_ADSP, CLK_PLL1),
DEF_BASE("sdh",  R8A7794_CLK_SDH,  CLK_TYPE_GEN2_SDH,  CLK_PLL1),
DEF_BASE("sd0",  R8A7794_CLK_SD0,  CLK_TYPE_GEN2_SD0,  CLK_PLL1),
@@ -69,6 +68,7 @@ static const struct cpg_core_clk r8a7794_core_clks[] 
__initconst = {
DEF_FIXED("hp", R8A7794_CLK_HP,CLK_PLL1, 12, 1),
DEF_FIXED("i",  R8A7794_CLK_I, CLK_PLL1,  2, 1),
DEF_FIXED("b",  R8A7794_CLK_B, CLK_PLL1, 12, 1),
+   DEF_FIXED("lb", R8A7794_CLK_B, CLK_PLL1, 24, 1),
DEF_FIXED("p",  R8A7794_CLK_P, CLK_PLL1, 24, 1),
DEF_FIXED("cl", R8A7794_CLK_CL,CLK_PLL1, 48, 1),
DEF_FIXED("cp", R8A7794_CLK_CP,CLK_PLL1, 48, 1),
-- 
2.7.4

[PATCH 2/5] clk: renesas: r8a7745: Fix LB clock divider

[Geert Uytterhoeven]

The CLK_TYPE_GEN2_LB clock type is meant for SoCs like R-Car H2, where
the LB clock divider depends on the value of the MD18 pin.

On RZ/G1E, the LB clock divider is fixed to 24.  Hence model the clock
as a fixed factor clock instead.

Signed-off-by: Geert Uytterhoeven 
---
 drivers/clk/renesas/r8a7745-cpg-mssr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/renesas/r8a7745-cpg-mssr.c 
b/drivers/clk/renesas/r8a7745-cpg-mssr.c
index 87f5a3619e4f9d60..4b0a9243b7481176 100644
--- a/drivers/clk/renesas/r8a7745-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7745-cpg-mssr.c
@@ -51,7 +51,6 @@ static const struct cpg_core_clk r8a7745_core_clks[] 
__initconst = {
DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
 
/* Core Clock Outputs */
-   DEF_BASE("lb",   R8A7745_CLK_LB,   CLK_TYPE_GEN2_LB,CLK_PLL1),
DEF_BASE("sdh",  R8A7745_CLK_SDH,  CLK_TYPE_GEN2_SDH,   CLK_PLL1),
DEF_BASE("sd0",  R8A7745_CLK_SD0,  CLK_TYPE_GEN2_SD0,   CLK_PLL1),
DEF_BASE("qspi", R8A7745_CLK_QSPI, CLK_TYPE_GEN2_QSPI,  CLK_PLL1_DIV2),
@@ -63,6 +62,7 @@ static const struct cpg_core_clk r8a7745_core_clks[] 
__initconst = {
DEF_FIXED("zs",R8A7745_CLK_ZS,  CLK_PLL1,   6, 1),
DEF_FIXED("hp",R8A7745_CLK_HP,  CLK_PLL1,  12, 1),
DEF_FIXED("b", R8A7745_CLK_B,   CLK_PLL1,  12, 1),
+   DEF_FIXED("lb",R8A7745_CLK_LB,  CLK_PLL1,  24, 1),
DEF_FIXED("p", R8A7745_CLK_P,   CLK_PLL1,  24, 1),
DEF_FIXED("cl",R8A7745_CLK_CL,  CLK_PLL1,  48, 1),
DEF_FIXED("cp",R8A7745_CLK_CP,  CLK_PLL1,  48, 1),
-- 
2.7.4

[PATCH 3/5] clk: renesas: r8a7791/r8a7793: Fix LB clock divider

[Geert Uytterhoeven]

The CLK_TYPE_GEN2_LB clock type is meant for SoCs like R-Car H2, where
the LB clock divider depends on the value of the MD18 pin.

On R-Car M2-W and M2-N, the LB clock divider is fixed to 24.  Hence
model the clock as a fixed factor clock instead.

Signed-off-by: Geert Uytterhoeven 
---
 drivers/clk/renesas/r8a7791-cpg-mssr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/renesas/r8a7791-cpg-mssr.c 
b/drivers/clk/renesas/r8a7791-cpg-mssr.c
index 820b220b09cc6bdb..1b91f03b75980766 100644
--- a/drivers/clk/renesas/r8a7791-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7791-cpg-mssr.c
@@ -57,7 +57,6 @@ static struct cpg_core_clk r8a7791_core_clks[] __initdata = {
 
/* Core Clock Outputs */
DEF_BASE("z",R8A7791_CLK_Z,CLK_TYPE_GEN2_Z,CLK_PLL0),
-   DEF_BASE("lb",   R8A7791_CLK_LB,   CLK_TYPE_GEN2_LB,   CLK_PLL1),
DEF_BASE("adsp", R8A7791_CLK_ADSP, CLK_TYPE_GEN2_ADSP, CLK_PLL1),
DEF_BASE("sdh",  R8A7791_CLK_SDH,  CLK_TYPE_GEN2_SDH,  CLK_PLL1),
DEF_BASE("sd0",  R8A7791_CLK_SD0,  CLK_TYPE_GEN2_SD0,  CLK_PLL1),
@@ -70,6 +69,7 @@ static struct cpg_core_clk r8a7791_core_clks[] __initdata = {
DEF_FIXED("hp", R8A7791_CLK_HP,CLK_PLL1, 12, 1),
DEF_FIXED("i",  R8A7791_CLK_I, CLK_PLL1,  2, 1),
DEF_FIXED("b",  R8A7791_CLK_B, CLK_PLL1, 12, 1),
+   DEF_FIXED("lb", R8A7791_CLK_LB,CLK_PLL1, 24, 1),
DEF_FIXED("p",  R8A7791_CLK_P, CLK_PLL1, 24, 1),
DEF_FIXED("cl", R8A7791_CLK_CL,CLK_PLL1, 48, 1),
DEF_FIXED("m2", R8A7791_CLK_M2,CLK_PLL1,  8, 1),
-- 
2.7.4

[PATCH 4/5] clk: renesas: r8a7792: Fix LB clock divider

[Geert Uytterhoeven]

The CLK_TYPE_GEN2_LB clock type is meant for SoCs like R-Car H2, where
the LB clock divider depends on the value of the MD18 pin.

On R-Car V2H, the LB clock divider is fixed to 24.  Hence model the
clock as a fixed factor clock instead.

Signed-off-by: Geert Uytterhoeven 
---
 drivers/clk/renesas/r8a7792-cpg-mssr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/renesas/r8a7792-cpg-mssr.c 
b/drivers/clk/renesas/r8a7792-cpg-mssr.c
index 609a540804965c40..8b66e6f4b4584de1 100644
--- a/drivers/clk/renesas/r8a7792-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7792-cpg-mssr.c
@@ -53,7 +53,6 @@ static const struct cpg_core_clk r8a7792_core_clks[] 
__initconst = {
DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
 
/* Core Clock Outputs */
-   DEF_BASE("lb",   R8A7792_CLK_LB,   CLK_TYPE_GEN2_LB,   CLK_PLL1),
DEF_BASE("qspi", R8A7792_CLK_QSPI, CLK_TYPE_GEN2_QSPI, CLK_PLL1_DIV2),
 
DEF_FIXED("z",  R8A7792_CLK_Z, CLK_PLL0,  1, 1),
@@ -63,6 +62,7 @@ static const struct cpg_core_clk r8a7792_core_clks[] 
__initconst = {
DEF_FIXED("hp", R8A7792_CLK_HP,CLK_PLL1, 12, 1),
DEF_FIXED("i",  R8A7792_CLK_I, CLK_PLL1,  3, 1),
DEF_FIXED("b",  R8A7792_CLK_B, CLK_PLL1, 12, 1),
+   DEF_FIXED("lb", R8A7792_CLK_B, CLK_PLL1, 24, 1),
DEF_FIXED("p",  R8A7792_CLK_P, CLK_PLL1, 24, 1),
DEF_FIXED("cl", R8A7792_CLK_CL,CLK_PLL1, 48, 1),
DEF_FIXED("m2", R8A7792_CLK_M2,CLK_PLL1,  8, 1),
-- 
2.7.4

[PATCH 0/5] clk: renesas: r-car gen2: Fix LB clock divider

[Geert Uytterhoeven]

Hi all,

The CLK_TYPE_GEN2_LB clock type is meant for SoCs like R-Car H2, where
the LB clock divider depends on the value of the MD18 pin.

However, on most RZ/G1 and R-Car Gen2 SoCs, the LB clock divider is
fixed to 24.  Hence this series corrects the LB clock on affected SoCs
by modelling it as a fixed factor clock instead.

This doesn't have much impact, as no kernel code relies on the rate of
the LB clock.

To be queued in clk-renesas-for-v4.18.

Geert Uytterhoeven (5):
  clk: renesas: r8a7743: Fix LB clock divider
  clk: renesas: r8a7745: Fix LB clock divider
  clk: renesas: r8a7791/r8a7793: Fix LB clock divider
  clk: renesas: r8a7792: Fix LB clock divider
  clk: renesas: r8a7794: Fix LB clock divider

 drivers/clk/renesas/r8a7743-cpg-mssr.c | 2 +-
 drivers/clk/renesas/r8a7745-cpg-mssr.c | 2 +-
 drivers/clk/renesas/r8a7791-cpg-mssr.c | 2 +-
 drivers/clk/renesas/r8a7792-cpg-mssr.c | 2 +-
 drivers/clk/renesas/r8a7794-cpg-mssr.c | 2 +-
 5 files changed, 5 insertions(+), 5 deletions(-)

-- 
2.7.4

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

[PATCH] dmaengine: rcar-dmac: Fix too early/late system suspend/resume callbacks

[Geert Uytterhoeven]

If serial console wake-up is enabled ("echo enabled >
/sys/.../ttySC0/power/wakeup"), and any serial input is received while
the system is suspended, serial port input no longer works after system
resume.

Note that:
  1) The system can still be woken up using the serial console,
  2) Serial port input keeps working if the system is woken up in some
 other way (e.g. Wake-on-LAN or gpio-keys), and no serial input was
 received while suspended.

To fix this, replace SET_LATE_SYSTEM_SLEEP_PM_OPS() by
SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(), as the callbacks installed by the
former happen too early resp. late in the suspend resp. resume process.

Reported-by: RVC test team via Yoshihiro Shimoda 

Fixes: 1131b0a4af911de5 ("dmaengine: rcar-dmac: Make DMAC reinit during system 
resume explicit")
Signed-off-by: Geert Uytterhoeven 
---
This is a fix for a regression introduced in v4.16-rc1.
---
 drivers/dma/sh/rcar-dmac.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/dma/sh/rcar-dmac.c b/drivers/dma/sh/rcar-dmac.c
index b10bf71ef5ae2b34..386894fa9ecaa2f1 100644
--- a/drivers/dma/sh/rcar-dmac.c
+++ b/drivers/dma/sh/rcar-dmac.c
@@ -1686,8 +1686,8 @@ static const struct dev_pm_ops rcar_dmac_pm = {
 *   - Wait for the current transfer to complete and stop the device,
 *   - Resume transfers, if any.
 */
-   SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
-pm_runtime_force_resume)
+   SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
+ pm_runtime_force_resume)
SET_RUNTIME_PM_OPS(rcar_dmac_runtime_suspend, rcar_dmac_runtime_resume,
   NULL)
 };
-- 
2.7.4

Re: [PATCH net-next] dt-bindings: net: renesas-ravb: Add support for r8a77470 SoC

[Sergei Shtylyov]

Hello!

On 03/29/2018 01:02 PM, Biju Das wrote:

> Add a new compatible string for the RZ/G1C (R8A77470) SoC.

   Needed solely to please checkpatch.pl. :-)

> Signed-off-by: Biju Das 
> Reviewed-by: Fabrizio Castro 

Acked-by: Sergei Shtylyov 

[...]

MBR, Sergei

Re: [PATCH 10/15] v4l: vsp1: Move DRM pipeline output setup code to a function

[Kieran Bingham]

Hi Laurent,

Thank you for another patch :D

On 26/02/18 21:45, Laurent Pinchart wrote:
> In order to make the vsp1_du_setup_lif() easier to read, and for
> symmetry with the DRM pipeline input setup, move the pipeline output
> setup code to a separate function.
> 
> Signed-off-by: Laurent Pinchart 

Just an easy code move. And I agree it improves things.

Small question below, but otherwise:

Reviewed-by: Kieran Bingham 

> ---
>  drivers/media/platform/vsp1/vsp1_drm.c | 107 
> +++--
>  1 file changed, 61 insertions(+), 46 deletions(-)
> 
> diff --git a/drivers/media/platform/vsp1/vsp1_drm.c 
> b/drivers/media/platform/vsp1/vsp1_drm.c
> index 00ce99bd1605..1c8adda47440 100644
> --- a/drivers/media/platform/vsp1/vsp1_drm.c
> +++ b/drivers/media/platform/vsp1/vsp1_drm.c
> @@ -276,6 +276,66 @@ static int vsp1_du_pipeline_setup_input(struct 
> vsp1_device *vsp1,
>   return 0;
>  }
>  
> +/* Setup the output side of the pipeline (WPF and LIF). */
> +static int vsp1_du_pipeline_setup_output(struct vsp1_device *vsp1,
> +  struct vsp1_pipeline *pipe)
> +{
> + struct vsp1_drm_pipeline *drm_pipe = to_vsp1_drm_pipeline(pipe);
> + struct v4l2_subdev_format format = {
> + .which = V4L2_SUBDEV_FORMAT_ACTIVE,

Why do you initialise this .which here, but all the other member variables 
below.

Wouldn't it make more sense to group all of this initialisation together? or is
there a distinction in keeping the .which separate.

(Perhaps this is just a way to initialise the rest of the structure to 0,
without using the memset?)


> + };
> + int ret;
> +
> + format.pad = RWPF_PAD_SINK;
> + format.format.width = drm_pipe->width;
> + format.format.height = drm_pipe->height;
> + format.format.code = MEDIA_BUS_FMT_ARGB_1X32;
> + format.format.field = V4L2_FIELD_NONE;
> +
> + ret = v4l2_subdev_call(>output->entity.subdev, pad, set_fmt, NULL,
> +);
> + if (ret < 0)
> + return ret;
> +
> + dev_dbg(vsp1->dev, "%s: set format %ux%u (%x) on WPF%u sink\n",
> + __func__, format.format.width, format.format.height,
> + format.format.code, pipe->output->entity.index);
> +
> + format.pad = RWPF_PAD_SOURCE;
> + ret = v4l2_subdev_call(>output->entity.subdev, pad, get_fmt, NULL,
> +);
> + if (ret < 0)
> + return ret;
> +
> + dev_dbg(vsp1->dev, "%s: got format %ux%u (%x) on WPF%u source\n",
> + __func__, format.format.width, format.format.height,
> + format.format.code, pipe->output->entity.index);
> +
> + format.pad = LIF_PAD_SINK;
> + ret = v4l2_subdev_call(>lif->subdev, pad, set_fmt, NULL,
> +);
> + if (ret < 0)
> + return ret;
> +
> + dev_dbg(vsp1->dev, "%s: set format %ux%u (%x) on LIF%u sink\n",
> + __func__, format.format.width, format.format.height,
> + format.format.code, pipe->lif->index);
> +
> + /*
> +  * Verify that the format at the output of the pipeline matches the
> +  * requested frame size and media bus code.
> +  */
> + if (format.format.width != drm_pipe->width ||
> + format.format.height != drm_pipe->height ||
> + format.format.code != MEDIA_BUS_FMT_ARGB_1X32) {
> + dev_dbg(vsp1->dev, "%s: format mismatch on LIF%u\n", __func__,
> + pipe->lif->index);
> + return -EPIPE;
> + }
> +
> + return 0;
> +}
> +
>  /* Configure all entities in the pipeline. */
>  static void vsp1_du_pipeline_configure(struct vsp1_pipeline *pipe)
>  {
> @@ -356,7 +416,6 @@ int vsp1_du_setup_lif(struct device *dev, unsigned int 
> pipe_index,
>   struct vsp1_drm_pipeline *drm_pipe;
>   struct vsp1_pipeline *pipe;
>   struct vsp1_bru *bru;
> - struct v4l2_subdev_format format;
>   unsigned long flags;
>   unsigned int i;
>   int ret;
> @@ -417,54 +476,10 @@ int vsp1_du_setup_lif(struct device *dev, unsigned int 
> pipe_index,
>   if (ret < 0)
>   return ret;
>  
> - memset(, 0, sizeof(format));
> - format.which = V4L2_SUBDEV_FORMAT_ACTIVE;
> - format.pad = RWPF_PAD_SINK;
> - format.format.width = cfg->width;
> - format.format.height = cfg->height;
> - format.format.code = MEDIA_BUS_FMT_ARGB_1X32;
> - format.format.field = V4L2_FIELD_NONE;
> -
> - ret = v4l2_subdev_call(>output->entity.subdev, pad, set_fmt, NULL,
> -);
> + ret = vsp1_du_pipeline_setup_output(vsp1, pipe);
>   if (ret < 0)
>   return ret;
>  
> - dev_dbg(vsp1->dev, "%s: set format %ux%u (%x) on WPF%u sink\n",
> - __func__, format.format.width, format.format.height,
> - format.format.code, 

Re: [PATCH 12/15] v4l: vsp1: Generalize detection of entity removal from DRM pipeline

[Kieran Bingham]

Hi Laurent,

Thank you for the patch,

On 26/02/18 21:45, Laurent Pinchart wrote:
> When disabling a DRM plane, the corresponding RPF is only marked as
> removed from the pipeline in the atomic update handler, with the actual
> removal happening when configuring the pipeline at atomic commit time.
> This is required as the RPF has to be disabled in the hardware, which
> can't be done from the atomic update handler.
> 
> The current implementation is RPF-specific. Make it independent of the
> entity type by using the entity's pipe pointer to mark removal from the
> pipeline. This will allow using the mechanism to remove BRU instances.

Nice improvement ...

> Signed-off-by: Laurent Pinchart 
> ---
>  drivers/media/platform/vsp1/vsp1_drm.c | 14 +++---
>  1 file changed, 7 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/media/platform/vsp1/vsp1_drm.c 
> b/drivers/media/platform/vsp1/vsp1_drm.c
> index d705a6e9fa1d..6c60b72b6f50 100644
> --- a/drivers/media/platform/vsp1/vsp1_drm.c
> +++ b/drivers/media/platform/vsp1/vsp1_drm.c
> @@ -346,13 +346,12 @@ static void vsp1_du_pipeline_configure(struct 
> vsp1_pipeline *pipe)
>   dl = vsp1_dl_list_get(pipe->output->dlm);
>  
>   list_for_each_entry_safe(entity, next, >entities, list_pipe) {
> - /* Disconnect unused RPFs from the pipeline. */
> - if (entity->type == VSP1_ENTITY_RPF &&
> - !pipe->inputs[entity->index]) {
> + /* Disconnect unused entities from the pipeline. */
> + if (!entity->pipe) {
>   vsp1_dl_list_write(dl, entity->route->reg,
>  VI6_DPR_NODE_UNUSED);

I don't think it's a problem, as we don't unset the entity->pipe for arbitrary
entities, but what happens if we set an HGO/HGT entity to NULL (these currently
have 0 as the route->reg. This would risk writing VI6_DPR_NODE_UNUSED to the
VI6_CMD(0) register?

In fact any entity in the pipeline with a null pipe pointer could cause this...
so we'd best be sure that they are right. Otherwise this could cause some crazy
bugs manifesting with the hardware doing something unexpected.

Assuming that won't be a problem,

Reviewed-by: Kieran Bingham 

>  
> - entity->pipe = NULL;
> + entity->sink = NULL;
>   list_del(>list_pipe);
>  
>   continue;
> @@ -569,10 +568,11 @@ int vsp1_du_atomic_update(struct device *dev, unsigned 
> int pipe_index,
>   rpf_index);
>  
>   /*
> -  * Remove the RPF from the pipe's inputs. The atomic flush
> -  * handler will disable the input and remove the entity from the
> -  * pipe's entities list.
> +  * Remove the RPF from the pipeline's inputs. Keep it in the
> +  * pipeline's entity list to let vsp1_du_pipeline_configure()
> +  * remove it from the hardware pipeline.
>*/
> + rpf->entity.pipe = NULL;
>   drm_pipe->pipe.inputs[rpf_index] = NULL;
>   return 0;
>   }
> 

Re: [PATCH v13 2/2] rcar-csi2: add Renesas R-Car MIPI CSI-2 receiver driver

[Maxime Ripard]

Hi Niklas,

On Tue, Feb 13, 2018 at 12:01:32AM +0100, Niklas Söderlund wrote:
> + switch (priv->lanes) {
> + case 1:
> + phycnt = PHYCNT_ENABLECLK | PHYCNT_ENABLE_0;
> + break;
> + case 2:
> + phycnt = PHYCNT_ENABLECLK | PHYCNT_ENABLE_1 | PHYCNT_ENABLE_0;
> + break;
> + case 4:
> + phycnt = PHYCNT_ENABLECLK | PHYCNT_ENABLE_3 | PHYCNT_ENABLE_2 |
> + PHYCNT_ENABLE_1 | PHYCNT_ENABLE_0;
> + break;
> + default:
> + return -EINVAL;
> + }

I guess you could have a simpler construct here using this:

phycnt = PHYCNT_ENABLECLK;

switch (priv->lanes) {
case 4:
phycnt |= PHYCNT_ENABLE_3 | PHYCNT_ENABLE_2;
case 2:
phycnt |= PHYCNT_ENABLE_1;
case 1:
phycnt |= PHYCNT_ENABLE_0;
break;

default:
return -EINVAL;
}

But that's really up to you.

> +static int rcar_csi2_probe(struct platform_device *pdev)
> +{
> + const struct soc_device_attribute *attr;
> + struct rcar_csi2 *priv;
> + unsigned int i;
> + int ret;
> +
> + priv = devm_kzalloc(>dev, sizeof(*priv), GFP_KERNEL);
> + if (!priv)
> + return -ENOMEM;
> +
> + priv->info = of_device_get_match_data(>dev);
> +
> + /* r8a7795 ES1.x behaves different then ES2.0+ but no own compat */
> + attr = soc_device_match(r8a7795es1);
> + if (attr)
> + priv->info = attr->data;
> +
> + priv->dev = >dev;
> +
> + mutex_init(>lock);
> + priv->stream_count = 0;
> +
> + ret = rcar_csi2_probe_resources(priv, pdev);
> + if (ret) {
> + dev_err(priv->dev, "Failed to get resources\n");
> + return ret;
> + }
> +
> + platform_set_drvdata(pdev, priv);
> +
> + ret = rcar_csi2_parse_dt(priv);
> + if (ret)
> + return ret;
> +
> + priv->subdev.owner = THIS_MODULE;
> + priv->subdev.dev = >dev;
> + v4l2_subdev_init(>subdev, _csi2_subdev_ops);
> + v4l2_set_subdevdata(>subdev, >dev);
> + snprintf(priv->subdev.name, V4L2_SUBDEV_NAME_SIZE, "%s %s",
> +  KBUILD_MODNAME, dev_name(>dev));
> + priv->subdev.flags = V4L2_SUBDEV_FL_HAS_DEVNODE;
> +
> + priv->subdev.entity.function = MEDIA_ENT_F_PROC_VIDEO_PIXEL_FORMATTER;
> + priv->subdev.entity.ops = _csi2_entity_ops;
> +
> + priv->pads[RCAR_CSI2_SINK].flags = MEDIA_PAD_FL_SINK;
> + for (i = RCAR_CSI2_SOURCE_VC0; i < NR_OF_RCAR_CSI2_PAD; i++)
> + priv->pads[i].flags = MEDIA_PAD_FL_SOURCE;
> +
> + ret = media_entity_pads_init(>subdev.entity, NR_OF_RCAR_CSI2_PAD,
> +  priv->pads);
> + if (ret)
> + goto error;
> +
> + pm_runtime_enable(>dev);

Is CONFIG_PM mandatory on Renesas SoCs? If not, you end up with the
device uninitialised at probe, and pm_runtime_get_sync will not
initialise it either if CONFIG_PM is not enabled. I guess you could
call your runtime_resume function unconditionally, and mark the device
as active in runtime_pm using pm_runtime_set_active.

Looks good otherwise, once fixed (and if relevant):
Reviewed-by: Maxime Ripard 

Maxime

-- 
Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com


signature.asc
Description: PGP signature

RE: [PATCH v3 4/8] reset: Renesas RZ/N1 reboot driver

[Michel Pollet]

On 29 March 2018 08:47, I messed up:
[snip]
>
> The Renesas RZ/N1 Family (Part #R9A06G0xx) needs a small driver to reboot
> the Cortex-A7 cores. This driver is a sub driver of the sysctrl MFD.
>
> Signed-off-by: Michel Pollet 
> ---
>  drivers/power/reset/Kconfig   |   7 +++
>  drivers/power/reset/Makefile  |   1 +
>  drivers/power/reset/rzn1-reboot.c | 105
[snip]
> +
> +parent = pdev->dev.parent;
> +if (!parent || !parent->of_node)

Not sure what went on when I had all the patches loaded in the editor before 
sending, but I've deleted a brace here. Will be fixed in v4... :/

Michel


> +dev_err(>dev, "couldn't find sysctrl node\n");
> +return -ENODEV;
> +}
> +sysctrl = syscon_node_to_regmap(parent->of_node);
> +if (IS_ERR(sysctrl)) {
> +dev_err(>dev, "couldn't find find regmap\n");
> +return PTR_ERR(sysctrl);
> +}
> +err = register_restart_handler(_reboot_nb);
> +if (err) {
> +dev_err(>dev, "register restart handler
> failed(err=%d)\n",
> +err);
> +}
> +
> +return err;
> +}
> +
> +static const struct of_device_id rzn1_reboot_of_match[] = {
> +{ .compatible = "renesas,rzn1-reboot" },
> +{}
> +};
> +MODULE_DEVICE_TABLE(of, rzn1_reboot_of_match);
> +
> +static struct platform_driver rzn1_reboot_driver = {
> +.probe = rzn1_reboot_probe,
> +.driver = {
> +.name = "rzn1-reboot",
> +.of_match_table = rzn1_reboot_of_match,
> +},
> +};
> +module_platform_driver(rzn1_reboot_driver);
> +
> +MODULE_DESCRIPTION("RZ/N1 reboot driver");
> MODULE_AUTHOR("Michel Pollet
> +, ");
> +MODULE_LICENSE("GPL v2");
> --
> 2.7.4




Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, 
Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered 
No. 04586709.

Re: [PATCH v3 6/8] DT: arm: Add Renesas RZ/N1 SoC base device tree file

[jacopo mondi]

Hi Michel

The subject of all your patches for arch/arm should start with:

ARM: dts:

A git log on that directory clearly shows that's the preferred one.

I would also say that you are missing a symbol definition in
arch/arm/mach-shmobile/Kconfig
(even if you got rid of any board file)

I would expect a symbol to select in menuconfig, with your
dependencies listed there (ie, the serial interface driver)

Something like this (I left the 'xx' out from the part name on purpose)

diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 280e731..9a519330 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -114,4 +114,8 @@ config ARCH_SH73A0
bool "SH-Mobile AG5 (R8A73A00)"
select ARCH_RMOBILE
select RENESAS_INTC_IRQPIN
+
+config ARCH_R9A06G0
+   bool "RZ/N1 (R9A06G0)"
+   select SERIAL_8250_DW
 endif

But please wait for others (preferibly Geert or Simon) to confim this.

On Thu, Mar 29, 2018 at 08:47:02AM +0100, Michel Pollet wrote:
> This adds the Renesas RZ/N1 Family (Part #R9A06G0xx) SoC
> bare bone support.
>
> This currently only handles generic parts (gic, architected timer)
> and a UART.
> For simplicity sake, this also relies on the bootloader to set the
> pinctrl and clocks.
>
> Signed-off-by: Michel Pollet 
> ---
>  arch/arm/boot/dts/r9a06g0xx.dtsi | 96 
> 
>  1 file changed, 96 insertions(+)
>  create mode 100644 arch/arm/boot/dts/r9a06g0xx.dtsi
>
> diff --git a/arch/arm/boot/dts/r9a06g0xx.dtsi 
> b/arch/arm/boot/dts/r9a06g0xx.dtsi
> new file mode 100644
> index 000..c63
> --- /dev/null
> +++ b/arch/arm/boot/dts/r9a06g0xx.dtsi
> @@ -0,0 +1,96 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Base Device Tree Source for the Renesas RZ/N1 SoC Family of devices
> + *
> + * Copyright (C) 2018 Renesas Electronics Europe Limited
> + *
> + */
> +
> +#include 
> +
> +/ {
> + compatible = "renesas,rzn1";
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu@0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a7";
> + reg = <0>;
> + };
> + cpu@1 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a7";
> + reg = <1>;
> + };
> + };

I see you don't like empy lines, that's fine, it is not a strict
requiremen afaik, but I find a few empty lines here and there more
redable, expecially if the file is going to grow, as it will be.


> + clocks {
> + /*
> +  * this is fixed clock for now,
> +  * until the clock driver is merged
> +  */
> + clkuarts: clkuarts {

You can remove the node lable if it's the same as the node name afaik

> + #clock-cells = <0>;
> + compatible = "fixed-clock";
> + clock-frequency = <47619047>;
> + };
> + };

Grouping clock nodes under a "clocks" one is now deprecated.

Please see, ie.
"ARM: dts: r7s72100: stop grouping clocks under a "clocks" subnode"

Thanks
   j

> + arch-timer {
> + compatible = "arm,cortex-a7-timer",
> +  "arm,armv7-timer";
> + interrupt-parent = <>;
> + arm,cpu-registers-not-fw-configured;
> + interrupts =
> +  + IRQ_TYPE_LEVEL_LOW)>,
> +  + IRQ_TYPE_LEVEL_LOW)>,
> +  + IRQ_TYPE_LEVEL_LOW)>,
> +  + IRQ_TYPE_LEVEL_LOW)>;
> + };
> + soc {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + interrupt-parent = <>;
> + ranges;
> +
> + gic: gic@44101000 {
> + compatible = "arm,cortex-a7-gic", "arm,gic-400";
> + interrupt-controller;
> + #interrupt-cells = <3>;
> + reg = <0x44101000 0x1000>, /* Distributer */
> +   <0x44102000 0x2000>, /* CPU interface */
> +   <0x44104000 0x2000>, /* Virt interface control */
> +   <0x44106000 0x2000>; /* Virt CPU interface */
> + interrupts =
> +  + IRQ_TYPE_LEVEL_HIGH)>;
> + };
> + sysctrl: sysctrl@4000c000 {
> + compatible = "renesas,rzn1-sysctrl", "syscon",
> + "simple-mfd";
> + reg = <0x4000c000 0x1000>;
> +
> + reboot {

[PATCH] ARM: debug-ll: Add support for r8a77470

[Biju Das]

Enable low-level debugging support for RZ/G1C (r8a77470). RZ/G1C uses
SCIF1 for the debug console.

Signed-off-by: Biju Das 
Reviewed-by: Fabrizio Castro 
---
* This patch has runtime depency on
https://www.spinics.net/lists/arm-kernel/msg644192.html

 arch/arm/Kconfig.debug | 13 +++--
 1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 78a6470..5778103 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -941,6 +941,13 @@ choice
  via SCIF0 on Renesas RZ/G1M (R8A7743), R-Car H2 (R8A7790),
  M2-W (R8A7791), V2H (R8A7792), or M2-N (R8A7793).
 
+   config DEBUG_RCAR_GEN2_SCIF1
+   bool "Kernel low-level debugging messages via SCIF1 on R8A77470"
+   depends on ARCH_R8A77470
+   help
+ Say Y here if you want kernel low-level debugging support
+ via SCIF1 on Renesas RZ/G1C (R8A77470).
+
config DEBUG_RCAR_GEN2_SCIF2
bool "Kernel low-level debugging messages via SCIF2 on R8A7794"
depends on ARCH_R8A7794
@@ -1494,6 +1501,7 @@ config DEBUG_LL_INCLUDE
default "debug/renesas-scif.S" if DEBUG_RCAR_GEN1_SCIF0
default "debug/renesas-scif.S" if DEBUG_RCAR_GEN1_SCIF2
default "debug/renesas-scif.S" if DEBUG_RCAR_GEN2_SCIF0
+   default "debug/renesas-scif.S" if DEBUG_RCAR_GEN2_SCIF1
default "debug/renesas-scif.S" if DEBUG_RCAR_GEN2_SCIF2
default "debug/renesas-scif.S" if DEBUG_RCAR_GEN2_SCIF4
default "debug/renesas-scif.S" if DEBUG_RMOBILE_SCIFA0
@@ -1616,6 +1624,7 @@ config DEBUG_UART_PHYS
default 0xe6c8 if DEBUG_RMOBILE_SCIFA4
default 0xe6e58000 if DEBUG_RCAR_GEN2_SCIF2
default 0xe6e6 if DEBUG_RCAR_GEN2_SCIF0
+   default 0xe6e68000 if DEBUG_RCAR_GEN2_SCIF1
default 0xe6ee if DEBUG_RCAR_GEN2_SCIF4
default 0xe8008000 if DEBUG_R7S72100_SCIF2
default 0xfbe0 if ARCH_EBSA110
@@ -1650,8 +1659,8 @@ config DEBUG_UART_PHYS
DEBUG_NETX_UART || \
DEBUG_QCOM_UARTDM || DEBUG_R7S72100_SCIF2 || \
DEBUG_RCAR_GEN1_SCIF0 || DEBUG_RCAR_GEN1_SCIF2 || \
-   DEBUG_RCAR_GEN2_SCIF0 || DEBUG_RCAR_GEN2_SCIF2 || \
-   DEBUG_RCAR_GEN2_SCIF4 || \
+   DEBUG_RCAR_GEN2_SCIF0 || DEBUG_RCAR_GEN2_SCIF1 || \
+   DEBUG_RCAR_GEN2_SCIF2 || DEBUG_RCAR_GEN2_SCIF4 || \
DEBUG_RMOBILE_SCIFA0 || DEBUG_RMOBILE_SCIFA1 || \
DEBUG_RMOBILE_SCIFA4 || DEBUG_S3C24XX_UART || \
DEBUG_S3C64XX_UART || \
-- 
2.7.4

[PATCH] dt-bindings: irqchip: renesas-irqc: Document r8a77470 support

[Biju Das]

Renesas RZ/G SoC have the R-Car gen2 compatible IRQC interrupt
controllers. Document RZ/G1C (also known as R8A77470) SoC bindings.

Signed-off-by: Biju Das 
Reviewed-by: Fabrizio Castro 
---
 Documentation/devicetree/bindings/interrupt-controller/renesas,irqc.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git 
a/Documentation/devicetree/bindings/interrupt-controller/renesas,irqc.txt 
b/Documentation/devicetree/bindings/interrupt-controller/renesas,irqc.txt
index 20f121d..1d5891a 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/renesas,irqc.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,irqc.txt
@@ -7,6 +7,7 @@ Required properties:
 - "renesas,irqc-r8a73a4" (R-Mobile APE6)
 - "renesas,irqc-r8a7743" (RZ/G1M)
 - "renesas,irqc-r8a7745" (RZ/G1E)
+- "renesas,irqc-r8a77470" (RZ/G1C)
 - "renesas,irqc-r8a7790" (R-Car H2)
 - "renesas,irqc-r8a7791" (R-Car M2-W)
 - "renesas,irqc-r8a7792" (R-Car V2H)
-- 
2.7.4

[PATCH] dt-bindings: rcar-dmac: Document r8a77470 support

[Biju Das]

Renesas  RZ/G SoC also have the R-Car gen2/3 compatible DMA controllers.
Document RZ/G1C (also known as R8A77470) SoC bindings.

Signed-off-by: Biju Das 
Reviewed-by: Fabrizio Castro 
---
 Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt 
b/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt
index 891db41..b5e603c 100644
--- a/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt
+++ b/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt
@@ -18,6 +18,7 @@ Required Properties:
  Examples with soctypes are:
- "renesas,dmac-r8a7743" (RZ/G1M)
- "renesas,dmac-r8a7745" (RZ/G1E)
+   - "renesas,dmac-r8a77470" (RZ/G1C)
- "renesas,dmac-r8a7790" (R-Car H2)
- "renesas,dmac-r8a7791" (R-Car M2-W)
- "renesas,dmac-r8a7792" (R-Car V2H)
-- 
2.7.4

[PATCH net-next] dt-bindings: net: renesas-ravb: Add support for r8a77470 SoC

[Biju Das]

Add a new compatible string for the RZ/G1C (R8A77470) SoC.

Signed-off-by: Biju Das 
Reviewed-by: Fabrizio Castro 
---
 Documentation/devicetree/bindings/net/renesas,ravb.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/net/renesas,ravb.txt 
b/Documentation/devicetree/bindings/net/renesas,ravb.txt
index b4dc455..c306f55 100644
--- a/Documentation/devicetree/bindings/net/renesas,ravb.txt
+++ b/Documentation/devicetree/bindings/net/renesas,ravb.txt
@@ -7,6 +7,7 @@ Required properties:
 - compatible: Must contain one or more of the following:
   - "renesas,etheravb-r8a7743" for the R8A7743 SoC.
   - "renesas,etheravb-r8a7745" for the R8A7745 SoC.
+  - "renesas,etheravb-r8a77470" for the R8A77470 SoC.
   - "renesas,etheravb-r8a7790" for the R8A7790 SoC.
   - "renesas,etheravb-r8a7791" for the R8A7791 SoC.
   - "renesas,etheravb-r8a7792" for the R8A7792 SoC.
-- 
2.7.4

Re: [PATCH v6 1/3] dt-bindings: display: bridge: Document THC63LVD1024 LVDS decoder

[jacopo mondi]

Hi Vladimir,

On Tue, Mar 27, 2018 at 02:03:25PM +0300, Vladimir Zapolskiy wrote:
> Hi Jacopo,
>
> On 03/27/2018 01:10 PM, jacopo mondi wrote:
> > Hi Vladimir,
> >
> > On Tue, Mar 27, 2018 at 12:37:31PM +0300, Vladimir Zapolskiy wrote:
> >> Hi Jacopo,
> >>
> >> On 03/27/2018 11:57 AM, jacopo mondi wrote:
> >>> Hi Vladimir,
> >>>
> >>> On Tue, Mar 27, 2018 at 11:30:29AM +0300, Vladimir Zapolskiy wrote:
>  Hi Sergei,
> 
>  On 03/27/2018 11:27 AM, Sergei Shtylyov wrote:
> > Hello!
> >
> > On 3/27/2018 10:33 AM, jacopo mondi wrote:
> > [...]
> >>> Document Thine THC63LVD1024 LVDS decoder device tree bindings.
> >>>
> >>> Signed-off-by: Jacopo Mondi 
> >>> Reviewed-by: Andrzej Hajda 
> >>> Reviewed-by: Niklas Söderlund 
> >>> 
> >>> ---
> >>>   .../bindings/display/bridge/thine,thc63lvd1024.txt | 66 
> >>> +++
> >>>   1 file changed, 66 insertions(+)
> >>>   create mode 100644
> >>> Documentation/devicetree/bindings/display/bridge/thine,thc63lvd1024.txt
> >>>
> >>> diff --git
> >>> a/Documentation/devicetree/bindings/display/bridge/thine,thc63lvd1024.txt
> >>> b/Documentation/devicetree/bindings/display/bridge/thine,thc63lvd1024.txt
> >>> new file mode 100644
> >>> index 000..8225c6a
> >>> --- /dev/null
> >>> +++
> >>> b/Documentation/devicetree/bindings/display/bridge/thine,thc63lvd1024.txt
> >>> @@ -0,0 +1,66 @@
> >>> +Thine Electronics THC63LVD1024 LVDS decoder
> >>> +---
> >>> +
> >>> +The THC63LVD1024 is a dual link LVDS receiver designed to 
> >>> convert LVDS
> >>> streams
> >>> +to parallel data outputs. The chip supports single/dual 
> >>> input/output modes,
> >>> +handling up to two two input LVDS stream and up to two digital 
> >>> CMOS/TTL
> >>> outputs.
> >>> +
> >>> +Single or dual operation modes, output data mapping and DDR 
> >>> output modes
> >>> are
> >>> +configured through input signals and the chip does not expose 
> >>> any control
> >>> bus.
> >>> +
> >>> +Required properties:
> >>> +- compatible: Shall be "thine,thc63lvd1024"
> >>> +
> >>> +Optional properties:
> >>> +- vcc-supply: Power supply for TTL output and digital circuitry
> >>> +- cvcc-supply: Power supply for TTL CLOCKOUT signal
> >>> +- lvcc-supply: Power supply for LVDS inputs
> >>> +- pvcc-supply: Power supply for PLL circuitry
> >> As explained in a comment to one of the previous versions of this 
> >> series, I'm
> >> tempted to make vcc-supply mandatory and drop the three other 
> >> power supplies
> >> for now, as I believe there's very little chance they will be 
> >> connected to
> >> separately controllable regulators (all supplies use the same 
> >> voltage). In the
> >> very unlikely event that this occurs in design we need to support 
> >> in the
> >> future, the cvcc, lvcc and pvcc supplies can be added later as 
> >> optional
> >> without breaking backward compatibility.
> > I'm okay with that.
> >
> >> Apart from that,
> >>
> >> Reviewed-by: Laurent Pinchart 
> >>
> >>> +- pdwn-gpios: Power down GPIO signal. Active low
> > powerdown-gpios is the semi-standard name.
> >
>  right, I've also noticed it. If possible please avoid shortenings in
>  property names.
> >>>
> >>> It is not shortening, it just follow pin name from decoder's 
> >>> datasheet.
> >>>
> 
> >>> +- oe-gpios: Output enable GPIO signal. Active high
> >>> +
>  And this one is also a not ever met property name, please consider to
>  rename it to 'enable-gpios', for instance display panels define it.
> >>>
> >>>
> >>> Again, it follows datasheet naming scheme. Has something changed in DT
> >>> conventions?
> >>
> >> Seconded. My understanding is that the property name should reflect
> >> what reported in the the chip manual. For THC63LVD1024 the enable and
> >> power down pins are named 'OE' and 'PDWN' respectively.
> >
> > But don't we need the vendor prefix in the prop names then, like
> > "renesas,oe-gpios" then?
> >
> 
>  Seconded, with a correction to "thine,oe-gpios".
> 
> >>>
> >>> mmm, okay then...
> >>>
> >>> A grep for that semi-standard properties names in Documentation/
> >>> returns only usage examples and no actual definitions, so I 

RE: [PATCH 09/12] ARM: shmobile: Document iW-RainboW-G23S single board computer

[Fabrizio Castro]

Hello Simon,

thank you for reworking the subject.

> Subject: Re: [PATCH 09/12] ARM: shmobile: Document iW-RainboW-G23S single 
> board computer
>
> On Wed, Mar 28, 2018 at 09:36:10AM +0200, Geert Uytterhoeven wrote:
> > On Tue, Mar 27, 2018 at 4:37 PM, Biju Das  wrote:
> > >
> > > Document the iW-RainboW-G23S single board computer device tree bindings,
> > > listing it as a supported board.
> > >
> > > Signed-off-by: Biju Das 
> > > Reviewed-by: Fabrizio Castro 
> >
> > Reviewed-by: Geert Uytterhoeven 
>
> Thanks, applied with the subject updated to:
>
> dt-bindings: arm:: Document iW-RainboW-G23S single board computer

There is an extra : in the new subject, is it too late for fixing this?

Thanks,
Fab



Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, 
Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered 
No. 04586709.

RE: [PATCH] gpio: dwapb: Add support for 32 interrupts

[Phil Edworthy]

Hi,

On 28 March 2018 15:23, Phil Edworthy wrote:
> The DesignWare GPIO IP can be configured for either 1 or 32 interrupts,
> but the driver currently only supports 1 interrupt. See the DesignWare
> DW_apb_gpio Databook description of the 'GPIO_INTR_IO' parameter.
> 
> This change allows the driver to work with up to 32 interrupts, it will
> get as many interrupts as specified in the DT 'interrupts' property.
> It doesn't do anything clever with the different interrupts, it just calls
> the same handler used for single interrupt hardware.
> 
> Signed-off-by: Phil Edworthy 
> ---
> Note: There are a few lines over 80 chars, but this is just guidance, right?
>   Especially as there are already some lines over 80 chars.
> ---
>  .../devicetree/bindings/gpio/snps-dwapb-gpio.txt   | 10 -
>  drivers/gpio/gpio-dwapb.c  | 44 
> +-
>  include/linux/platform_data/gpio-dwapb.h   |  3 +-
>  3 files changed, 45 insertions(+), 12 deletions(-)

This patch triggers a build error for Quark MFD driver, which is the only user
of the structure outside of the driver. I will fix that with an additional 
patch,
but I'll wait to see what other comments I get first.

Thanks
Phil


> diff --git a/Documentation/devicetree/bindings/gpio/snps-dwapb-gpio.txt
> b/Documentation/devicetree/bindings/gpio/snps-dwapb-gpio.txt
> index 4a75da7..e343581 100644
> --- a/Documentation/devicetree/bindings/gpio/snps-dwapb-gpio.txt
> +++ b/Documentation/devicetree/bindings/gpio/snps-dwapb-gpio.txt
> @@ -26,8 +26,14 @@ controller.
>the second encodes the triger flags encoded as described in
>Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
>  - interrupt-parent : The parent interrupt controller.
> -- interrupts : The interrupt to the parent controller raised when GPIOs
> -  generate the interrupts.
> +- interrupts : The interrupts to the parent controller raised when GPIOs
> +  generate the interrupts. If the controller provides one combined interrupt
> +  for all GPIOs, specify a single interrupt. If the controller provides one
> +  interrupt for each GPIO, provide a list of interrupts that correspond to 
> each
> +  of the GPIO pins. When specifying multiple interrupts, if any of the GPIOs
> are
> +  not connected to an interrupt, use the interrupt-mask property.
> +- interrupt-mask : a 32-bit bit mask that specifies which interrupts in the 
> list
> +  of interrupts is valid, bit is 1 for a valid irq.
>  - snps,nr-gpios : The number of pins in the port, a single cell.
>  - resets : Reset line for the controller.
> 
> diff --git a/drivers/gpio/gpio-dwapb.c b/drivers/gpio/gpio-dwapb.c
> index 226977f..47d82f9 100644
> --- a/drivers/gpio/gpio-dwapb.c
> +++ b/drivers/gpio/gpio-dwapb.c
> @@ -441,14 +441,19 @@ static void dwapb_configure_irqs(struct
> dwapb_gpio *gpio,
>   irq_gc->chip_types[1].handler = handle_edge_irq;
> 
>   if (!pp->irq_shared) {
> - irq_set_chained_handler_and_data(pp->irq,
> dwapb_irq_handler,
> -  gpio);
> + int i;
> +
> + for (i = 0; i < pp->ngpio; i++) {
> + if (pp->irq[i])
> + irq_set_chained_handler_and_data(pp-
> >irq[i],
> + dwapb_irq_handler, gpio);
> + }
>   } else {
>   /*
>* Request a shared IRQ since where MFD would have
> devices
>* using the same irq pin
>*/
> - err = devm_request_irq(gpio->dev, pp->irq,
> + err = devm_request_irq(gpio->dev, pp->irq[0],
>  dwapb_irq_handler_mfd,
>  IRQF_SHARED, "gpio-dwapb-mfd", gpio);
>   if (err) {
> @@ -524,7 +529,7 @@ static int dwapb_gpio_add_port(struct dwapb_gpio
> *gpio,
>   if (pp->idx == 0)
>   port->gc.set_config = dwapb_gpio_set_config;
> 
> - if (pp->irq)
> + if (pp->has_irq)
>   dwapb_configure_irqs(gpio, port, pp);
> 
>   err = gpiochip_add_data(>gc, port);
> @@ -535,7 +540,7 @@ static int dwapb_gpio_add_port(struct dwapb_gpio
> *gpio,
>   port->is_registered = true;
> 
>   /* Add GPIO-signaled ACPI event support */
> - if (pp->irq)
> + if (pp->has_irq)
>   acpi_gpiochip_request_interrupts(>gc);
> 
>   return err;
> @@ -601,13 +606,34 @@ dwapb_gpio_get_pdata(struct device *dev)
>   if (dev->of_node && pp->idx == 0 &&
>   fwnode_property_read_bool(fwnode,
> "interrupt-controller")) {
> - pp->irq =
> irq_of_parse_and_map(to_of_node(fwnode), 0);
> - if (!pp->irq)
> + struct device_node *np = to_of_node(fwnode);
> + u32 irq_mask = 0x;
> + 

Re: [PATCH v2 4/8] clk: renesas: cpg-mssr: Add r8a77470 support

[Geert Uytterhoeven]

Hi Biju,

On Wed, Mar 28, 2018 at 9:26 PM, Biju Das  wrote:
> Add RZ/G1C (R8A77470) Clock Pulse Generator / Module Standby and Software
> Reset support.
>
> Signed-off-by: Biju Das 
> Reviewed-by: Fabrizio Castro 
> ---
> V1->V2:
> * incorporated geert's review comment

Thanks for the update, will queue in clk-renesas-for v4.18.

Gr{oetje,eeting}s,

Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

Re: [PATCH v2 3/8] clk: renesas: Add r8a77470 CPG Core Clock Definitions

[Geert Uytterhoeven]

Hi Biju,

On Wed, Mar 28, 2018 at 9:26 PM, Biju Das  wrote:
> Add all RZ/G1C Clock Pulse Generator Core Clock Outputs, as listed in
> Table 7.2 ("List of Clocks [RZ/G1C]") of the RZ/G1C Hardware User's
> Manual.
>
> Signed-off-by: Biju Das 
> Reviewed-by: Fabrizio Castro 
> Reviewed-by: Geert Uytterhoeven 
> ---
> V1->V2:
> * incorporated geert's review comment

Thanks for the update, will queue in clk-renesas-for v4.18.

Gr{oetje,eeting}s,

Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

[PATCH v3 5/8] arm: shmobile: Add the RZ/N1 arch to the shmobile Kconfig

[Michel Pollet]

Add the RZ/N1 Family (Part #R9A06G0xx) ARCH config to the rest of
the Renesas SoC collection.

Signed-off-by: Michel Pollet 
Reviewed-by: Geert Uytterhoeven 
---
 arch/arm/mach-shmobile/Kconfig | 5 +
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 280e731..221fbcb 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -110,6 +110,11 @@ config ARCH_R8A7794
bool "R-Car E2 (R8A77940)"
select ARCH_RCAR_GEN2
 
+config ARCH_RZN1
+   bool "RZ/N1 (R9A06G0xx) Family"
+   select ARM_AMBA
+   select CPU_V7
+
 config ARCH_SH73A0
bool "SH-Mobile AG5 (R8A73A00)"
select ARCH_RMOBILE
-- 
2.7.4

[PATCH v3 6/8] DT: arm: Add Renesas RZ/N1 SoC base device tree file

[Michel Pollet]

This adds the Renesas RZ/N1 Family (Part #R9A06G0xx) SoC
bare bone support.

This currently only handles generic parts (gic, architected timer)
and a UART.
For simplicity sake, this also relies on the bootloader to set the
pinctrl and clocks.

Signed-off-by: Michel Pollet 
---
 arch/arm/boot/dts/r9a06g0xx.dtsi | 96 
 1 file changed, 96 insertions(+)
 create mode 100644 arch/arm/boot/dts/r9a06g0xx.dtsi

diff --git a/arch/arm/boot/dts/r9a06g0xx.dtsi b/arch/arm/boot/dts/r9a06g0xx.dtsi
new file mode 100644
index 000..c63
--- /dev/null
+++ b/arch/arm/boot/dts/r9a06g0xx.dtsi
@@ -0,0 +1,96 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Base Device Tree Source for the Renesas RZ/N1 SoC Family of devices
+ *
+ * Copyright (C) 2018 Renesas Electronics Europe Limited
+ *
+ */
+
+#include 
+
+/ {
+   compatible = "renesas,rzn1";
+   #address-cells = <1>;
+   #size-cells = <1>;
+
+   cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   cpu@0 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a7";
+   reg = <0>;
+   };
+   cpu@1 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a7";
+   reg = <1>;
+   };
+   };
+   clocks {
+   /*
+* this is fixed clock for now,
+* until the clock driver is merged
+*/
+   clkuarts: clkuarts {
+   #clock-cells = <0>;
+   compatible = "fixed-clock";
+   clock-frequency = <47619047>;
+   };
+   };
+   arch-timer {
+   compatible = "arm,cortex-a7-timer",
+"arm,armv7-timer";
+   interrupt-parent = <>;
+   arm,cpu-registers-not-fw-configured;
+   interrupts =
+   ,
+   ,
+   ,
+   ;
+   };
+   soc {
+   compatible = "simple-bus";
+   #address-cells = <1>;
+   #size-cells = <1>;
+   interrupt-parent = <>;
+   ranges;
+
+   gic: gic@44101000 {
+   compatible = "arm,cortex-a7-gic", "arm,gic-400";
+   interrupt-controller;
+   #interrupt-cells = <3>;
+   reg = <0x44101000 0x1000>, /* Distributer */
+ <0x44102000 0x2000>, /* CPU interface */
+ <0x44104000 0x2000>, /* Virt interface control */
+ <0x44106000 0x2000>; /* Virt CPU interface */
+   interrupts =
+   ;
+   };
+   sysctrl: sysctrl@4000c000 {
+   compatible = "renesas,rzn1-sysctrl", "syscon",
+   "simple-mfd";
+   reg = <0x4000c000 0x1000>;
+
+   reboot {
+   compatible = "renesas,rzn1-reboot";
+   };
+   };
+   uart0: serial@4006 {
+   compatible = "snps,dw-apb-uart";
+   reg = <0x4006 0x400>;
+   interrupts = ;
+   reg-shift = <2>;
+   reg-io-width = <4>;
+   clocks = <>;
+   clock-names = "baudclk";
+   status = "disabled";
+   };
+   };
+};
-- 
2.7.4

[PATCH v3 7/8] DT: arm: Add Renesas RZN1D-DB Board base file

[Michel Pollet]

This adds a base device tree file for the RZN1-DB board, with only the
basic support allowing the system to boot to a prompt. Only one UART is
used, with only a single CPU running.

Signed-off-by: Michel Pollet 
---
 arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts | 26 ++
 1 file changed, 26 insertions(+)
 create mode 100644 arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts

diff --git a/arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts 
b/arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts
new file mode 100644
index 000..a462b1a
--- /dev/null
+++ b/arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the RZN1D-DB Board
+ *
+ * Copyright (C) 2018 Renesas Electronics Europe Limited
+ *
+ */
+
+/dts-v1/;
+
+#include "r9a06g0xx.dtsi"
+
+/ {
+   model = "RZN1D-DB Board";
+   compatible = "renesas,rzn1d400-db", "renesas,r9a06g032", "renesas,rzn1";
+
+   chosen {
+   stdout-path = "serial0:115200n8";
+   };
+   aliases {
+   serial0 = 
+   };
+};
+ {
+   status = "okay";
+};
-- 
2.7.4

[PATCH v3 8/8] DT: arm: Add the RZN1D-DB Board to Renesas Makefile target

[Michel Pollet]

This adds the newly added board to the Renesas built target

Signed-off-by: Michel Pollet 
Reviewed-by: Geert Uytterhoeven 
---
 arch/arm/boot/dts/Makefile | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 8164c12..1849228 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -806,6 +806,7 @@ dtb-$(CONFIG_ARCH_RENESAS) += \
r8a7793-gose.dtb \
r8a7794-alt.dtb \
r8a7794-silk.dtb \
+   r9a06g032-rzn1d400-db.dtb \
sh73a0-kzm9g.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rv1108-evb.dtb \
-- 
2.7.4

[PATCH v3 0/8] arm: Base support for Renesas RZN1D-DB Board

[Michel Pollet]

This series adds the plain basic support for booting a bare
kernel on the RZ/N1D-DB Board. It's been trimmed to the strict
minimum as a 'base', further patches that will add the
rest of the support, pinctrl, clock architecture and quite
a few others.

Thanks for the comments on the previous version!

v3:
 + Fixes for suggestions by Geert Uytterhoeven
 + Removed SoC Specific renesas,r9a06g032-xxx, as it's not needed for now.
 + Kept renesas,rzn1 as a family/generic for this family.
 + Fixed a couple of the commit messages.
 + Added Geert's Reviewed-By where appropriate.
v2: 
 + Fixes for suggestions by Simon Horman
 + Fixes for suggestions by Rob Herring
 + Fixes for suggestions by Geert Uytterhoeven
 + Removed the mach file
 + Added a MFD base for the sysctrl block
 + Added a regmap based sub driver for the reboot handler
 + Renamed the files to match shmobile conventions
 + Adapted the compatible= strings to reflect 'family' vs 'part'
   distinction.
 + Removed the sysctrl.h file entirelly. 
 + Fixed every warnings from the DTC compiler on W=12 mode.
 + Split the device-tree patches from the code.

Michel Pollet (8):
  DT: mfd: renesas,rzn1-sysctrl: document RZ/N1 sysctrl node
  DT: reset: renesas,rzn1-reboot: document RZ/N1 reboot driver
  DT: arm: renesas,rzn1: add the RZ/N1 SoC and RZN1D-DB board
  reset: Renesas RZ/N1 reboot driver
  arm: shmobile: Add the RZ/N1 arch to the shmobile Kconfig
  DT: arm: Add Renesas RZ/N1 SoC base device tree file
  DT: arm: Add Renesas RZN1D-DB Board base file
  DT: arm: Add the RZN1D-DB Board to Renesas Makefile target

 Documentation/devicetree/bindings/arm/shmobile.txt |   7 +-
 .../bindings/mfd/renesas,rzn1-sysctrl.txt  |  19 
 .../bindings/power/renesas,rzn1-reboot.txt |  20 
 arch/arm/boot/dts/Makefile |   1 +
 arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts|  26 +
 arch/arm/boot/dts/r9a06g0xx.dtsi   |  96 +++
 arch/arm/mach-shmobile/Kconfig |   5 +
 drivers/power/reset/Kconfig|   7 ++
 drivers/power/reset/Makefile   |   1 +
 drivers/power/reset/rzn1-reboot.c  | 105 +
 10 files changed, 286 insertions(+), 1 deletion(-)
 create mode 100644 
Documentation/devicetree/bindings/mfd/renesas,rzn1-sysctrl.txt
 create mode 100644 
Documentation/devicetree/bindings/power/renesas,rzn1-reboot.txt
 create mode 100644 arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts
 create mode 100644 arch/arm/boot/dts/r9a06g0xx.dtsi
 create mode 100644 drivers/power/reset/rzn1-reboot.c

-- 
2.7.4

[PATCH v3 1/8] DT: mfd: renesas,rzn1-sysctrl: document RZ/N1 sysctrl node

[Michel Pollet]

The Renesas RZ/N1 Family (Part #R9A06G0xx) has a multi-function
system controller. This documents the node used to encapsulate
it's sub drivers.

Signed-off-by: Michel Pollet 
---
 .../devicetree/bindings/mfd/renesas,rzn1-sysctrl.txt  | 19 +++
 1 file changed, 19 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/mfd/renesas,rzn1-sysctrl.txt

diff --git a/Documentation/devicetree/bindings/mfd/renesas,rzn1-sysctrl.txt 
b/Documentation/devicetree/bindings/mfd/renesas,rzn1-sysctrl.txt
new file mode 100644
index 000..1dbfdaf
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/renesas,rzn1-sysctrl.txt
@@ -0,0 +1,19 @@
+DT bindings for the Renesas RZ/N1 System Controller
+
+== System Controller Node ==
+
+The system controller node currently only hosts a single sub-node to handle
+the rebooting of the CPU. Eventually it will host the clock driver, SMP
+start handler, watchdog etc.
+
+See renesas,rzn1-reboot.txt for further details.
+
+Bindings:
++ Required:
+   compatible = "renesas,rzn1-sysctrl", "syscon", "simple-mfd";
+
+Example:
+   sysctrl: sysctrl@4000c000 {
+   compatible = "renesas,rzn1-sysctrl", "syscon", "simple-mfd";
+   reg = <0x4000c000 0x1000>;
+   };
-- 
2.7.4

[PATCH v3 4/8] reset: Renesas RZ/N1 reboot driver

[Michel Pollet]

The Renesas RZ/N1 Family (Part #R9A06G0xx) needs a small driver
to reboot the Cortex-A7 cores. This driver is a sub driver of
the sysctrl MFD.

Signed-off-by: Michel Pollet 
---
 drivers/power/reset/Kconfig   |   7 +++
 drivers/power/reset/Makefile  |   1 +
 drivers/power/reset/rzn1-reboot.c | 105 ++
 3 files changed, 113 insertions(+)
 create mode 100644 drivers/power/reset/rzn1-reboot.c

diff --git a/drivers/power/reset/Kconfig b/drivers/power/reset/Kconfig
index df58fc8..1416d88 100644
--- a/drivers/power/reset/Kconfig
+++ b/drivers/power/reset/Kconfig
@@ -144,6 +144,13 @@ config POWER_RESET_RESTART
  Instead they restart, and u-boot holds the SoC until the
  user presses a key. u-boot then boots into Linux.
 
+config POWER_RESET_RZN1
+   bool "Renesas RZ/N1 reboot driver"
+   depends on ARCH_RZN1
+   help
+ This driver allows rebooting the CA7 cores of the
+ Renesas RZ/N1 Family of SoC (Part # R9A06G0xx).
+
 config POWER_RESET_ST
bool "ST restart driver"
depends on ARCH_STI
diff --git a/drivers/power/reset/Makefile b/drivers/power/reset/Makefile
index 7778c74..bad9702 100644
--- a/drivers/power/reset/Makefile
+++ b/drivers/power/reset/Makefile
@@ -16,6 +16,7 @@ obj-$(CONFIG_POWER_RESET_PIIX4_POWEROFF) += piix4-poweroff.o
 obj-$(CONFIG_POWER_RESET_LTC2952) += ltc2952-poweroff.o
 obj-$(CONFIG_POWER_RESET_QNAP) += qnap-poweroff.o
 obj-$(CONFIG_POWER_RESET_RESTART) += restart-poweroff.o
+obj-$(CONFIG_POWER_RESET_RZN1) += rzn1-reboot.o
 obj-$(CONFIG_POWER_RESET_ST) += st-poweroff.o
 obj-$(CONFIG_POWER_RESET_VERSATILE) += arm-versatile-reboot.o
 obj-$(CONFIG_POWER_RESET_VEXPRESS) += vexpress-poweroff.o
diff --git a/drivers/power/reset/rzn1-reboot.c 
b/drivers/power/reset/rzn1-reboot.c
new file mode 100644
index 000..54fdd81
--- /dev/null
+++ b/drivers/power/reset/rzn1-reboot.c
@@ -0,0 +1,105 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * RZ/N1 reboot driver
+ *
+ * Copyright (C) 2018 Renesas Electronics Europe Limited
+ *
+ * Michel Pollet , 
+ * Derived from zx-reboot.c
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* Definitions from the SDK rzn1-sysctrl.h autogenerated file */
+#define RZN1_SYSCTRL_REG_RSTEN 0x120
+#define RZN1_SYSCTRL_REG_RSTEN_MRESET_EN   0
+#define RZN1_SYSCTRL_REG_RSTEN_WDA7RST_EN  1
+#define RZN1_SYSCTRL_REG_RSTEN_WDA7RST_EN_MASK 0x6
+#define RZN1_SYSCTRL_REG_RSTEN_WDM3RST_EN  3
+#define RZN1_SYSCTRL_REG_RSTEN_CM3LOCKUPRST_EN 4
+#define RZN1_SYSCTRL_REG_RSTEN_CM3SYSRESET_EN  5
+#define RZN1_SYSCTRL_REG_RSTEN_SWRST_EN6
+#define RZN1_SYSCTRL_REG_RSTCTRL   0x198
+#define RZN1_SYSCTRL_REG_RSTCTRL_WDA7RST_REQ   1
+#define RZN1_SYSCTRL_REG_RSTCTRL_WDA7RST_REQ_MASK  0x6
+#define RZN1_SYSCTRL_REG_RSTCTRL_WDM3RST_REQ   3
+#define RZN1_SYSCTRL_REG_RSTCTRL_CM3LOCKUPRST_REQ  4
+#define RZN1_SYSCTRL_REG_RSTCTRL_CM3SYSRESET_REQ   5
+#define RZN1_SYSCTRL_REG_RSTCTRL_SWRST_REQ 6
+
+static struct regmap *sysctrl;
+
+static int rzn1_reboot_handler(struct notifier_block *this,
+ unsigned long mode, void *cmd)
+{
+   regmap_write_bits(sysctrl,
+   RZN1_SYSCTRL_REG_RSTEN,
+   BIT(RZN1_SYSCTRL_REG_RSTEN_SWRST_EN) |
+   BIT(RZN1_SYSCTRL_REG_RSTEN_MRESET_EN),
+   BIT(RZN1_SYSCTRL_REG_RSTEN_SWRST_EN) |
+   BIT(RZN1_SYSCTRL_REG_RSTEN_MRESET_EN));
+   regmap_write_bits(sysctrl,
+   RZN1_SYSCTRL_REG_RSTCTRL,
+   BIT(RZN1_SYSCTRL_REG_RSTCTRL_SWRST_REQ),
+   BIT(RZN1_SYSCTRL_REG_RSTCTRL_SWRST_REQ));
+
+   mdelay(50);
+   pr_emerg("Unable to restart system\n");
+
+   return NOTIFY_DONE;
+}
+
+static struct notifier_block rzn1_reboot_nb = {
+   .notifier_call = rzn1_reboot_handler,
+   .priority = 128,
+};
+
+static int rzn1_reboot_probe(struct platform_device *pdev)
+{
+   int err;
+   struct device *parent;
+
+   parent = pdev->dev.parent;
+   if (!parent || !parent->of_node)
+   dev_err(>dev, "couldn't find sysctrl node\n");
+   return -ENODEV;
+   }
+   sysctrl = syscon_node_to_regmap(parent->of_node);
+   if (IS_ERR(sysctrl)) {
+   dev_err(>dev, "couldn't find find regmap\n");
+   return PTR_ERR(sysctrl);
+   }
+   err = register_restart_handler(_reboot_nb);
+   if (err) {
+   dev_err(>dev, "register restart handler failed(err=%d)\n",
+   err);
+   }
+
+   return err;
+}
+
+static const struct of_device_id rzn1_reboot_of_match[] = {
+   { .compatible = 

[PATCH v3 3/8] DT: arm: renesas,rzn1: add the RZ/N1 SoC and RZN1D-DB board

[Michel Pollet]

This documents the RZ/N1 bindings for both the RZ/N1 and the RZN1D-DB
board.

Signed-off-by: Michel Pollet 
---
 Documentation/devicetree/bindings/arm/shmobile.txt | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt 
b/Documentation/devicetree/bindings/arm/shmobile.txt
index d3d1df9..52368fc 100644
--- a/Documentation/devicetree/bindings/arm/shmobile.txt
+++ b/Documentation/devicetree/bindings/arm/shmobile.txt
@@ -47,7 +47,10 @@ SoCs:
 compatible = "renesas,r8a77980"
   - R-Car D3 (R8A77995)
 compatible = "renesas,r8a77995"
-
+  - RZ/N1 Family (R9A06G032 & R9A06G033)
+compatible = "renesas,rzn1"
+  - RZ/N1D (R9A06G032)
+compatible = "renesas,r9a06g032", "renesas,rzn1"
 
 Boards:
 
@@ -104,6 +107,8 @@ Boards:
 compatible = "renesas,porter", "renesas,r8a7791"
   - RSKRZA1 (YR0K77210C000BE)
 compatible = "renesas,rskrza1", "renesas,r7s72100"
+  - RZN1D-DB (RZ/N1D Demo Board for the RZ/N1D 400 pins package)
+compatible = "renesas,rzn1d400-db", "renesas,r9a06g032", "renesas,rzn1"
   - Salvator-X (RTP0RC7795SIPB0010S)
 compatible = "renesas,salvator-x", "renesas,r8a7795"
   - Salvator-X (RTP0RC7796SIPB0011S)
-- 
2.7.4

[PATCH v3 2/8] DT: reset: renesas,rzn1-reboot: document RZ/N1 reboot driver

[Michel Pollet]

The Renesas RZ/N1 Family (Part #R9A06G0xx) requires a driver
as part of the sysctrl MFD to handle rebooting the CA7 cores.
This documents the driver bindings.

Signed-off-by: Michel Pollet 
---
 .../bindings/power/renesas,rzn1-reboot.txt   | 20 
 1 file changed, 20 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/power/renesas,rzn1-reboot.txt

diff --git a/Documentation/devicetree/bindings/power/renesas,rzn1-reboot.txt 
b/Documentation/devicetree/bindings/power/renesas,rzn1-reboot.txt
new file mode 100644
index 000..f592769
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/renesas,rzn1-reboot.txt
@@ -0,0 +1,20 @@
+DT bindings for the Renesas RZ/N1 Reboot Driver
+
+== Reboot Driver Node ==
+
+The reboot driver is always a subnode of the system controller node, see
+renesas,rzn1-sysctrl.txt for details.
+
+Bindings:
++ Required:
+   compatible = "renesas,rzn1-reboot";
+
+Example:
+   sysctrl: sysctrl@4000c000 {
+   compatible = "renesas,rzn1-sysctrl", "syscon", "simple-mfd";
+   reg = <0x4000c000 0x1000>;
+
+   reboot {
+   compatible = "renesas,rzn1-reboot";
+   };
+   };
-- 
2.7.4

Re: [PATCH v2 5/8] ARM: shmobile: r8a77470: basic SoC support

[Geert Uytterhoeven]

On Wed, Mar 28, 2018 at 9:26 PM, Biju Das  wrote:
> Add minimal support for the RZ/G1C (R8A77470) SoC.
>
> Signed-off-by: Biju Das 
> Reviewed-by: Fabrizio Castro 
> ---
> V1->V2:
> * No change

Hence my
Reviewed-by: Geert Uytterhoeven 
for v1 is still valid.

Gr{oetje,eeting}s,

Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

Re: [PATCH v2 8/8] ARM: multi_v7_defconfig: Enable r8a77470 SoC

[Geert Uytterhoeven]

On Wed, Mar 28, 2018 at 9:26 PM, Biju Das  wrote:
> Enable recently added r8a77470 (RZ/G1C) SoC.
>
> Signed-off-by: Biju Das 
> Reviewed-by: Fabrizio Castro 

Reviewed-by: Geert Uytterhoeven 

Gr{oetje,eeting}s,

Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

Re: [PATCH 07/15] v4l: vsp1: Move DRM atomic commit pipeline setup to separate function

[Laurent Pinchart]

Hi Kieran,

On Wednesday, 28 March 2018 17:43:13 EEST Kieran Bingham wrote:
> On 26/02/18 21:45, Laurent Pinchart wrote:
> > The DRM pipeline setup code used at atomic commit time is similar to the
> > setup code used when enabling the pipeline. Move it to a separate
> > function in order to share it.
> > 
> > Signed-off-by: Laurent Pinchart
> > 
> 
> Assuming no hidden secret code addition in this code move that I haven't
> seen..
> 
> Only a minor nit below asking if the function should be pluralised (_inputs,
> rather than _input)

I'll fix that in v2, thanks.

> Reviewed-by: Kieran Bingham 
> 
> > ---
> > 
> >  drivers/media/platform/vsp1/vsp1_drm.c | 347
> >  + 1 file changed, 180 insertions(+), 167
> >  deletions(-)
> > 
> > diff --git a/drivers/media/platform/vsp1/vsp1_drm.c
> > b/drivers/media/platform/vsp1/vsp1_drm.c index 9a043a915c0b..7bf697ba7969
> > 100644
> > --- a/drivers/media/platform/vsp1/vsp1_drm.c
> > +++ b/drivers/media/platform/vsp1/vsp1_drm.c
> > @@ -46,6 +46,185 @@ static void vsp1_du_pipeline_frame_end(struct
> > vsp1_pipeline *pipe,> 
> >   * Pipeline Configuration
> >   */
> > 
> > +/* Setup one RPF and the connected BRU sink pad. */
> > +static int vsp1_du_pipeline_setup_rpf(struct vsp1_device *vsp1,
> > + struct vsp1_pipeline *pipe,
> > + struct vsp1_rwpf *rpf,
> > + unsigned int bru_input)
> > +{
> > +   struct v4l2_subdev_selection sel;
> > +   struct v4l2_subdev_format format;
> > +   const struct v4l2_rect *crop;
> > +   int ret;
> > +
> > +   /*
> > +* Configure the format on the RPF sink pad and propagate it up to the
> > +* BRU sink pad.
> > +*/
> > +   crop = >drm->inputs[rpf->entity.index].crop;
> > +
> > +   memset(, 0, sizeof(format));
> > +   format.which = V4L2_SUBDEV_FORMAT_ACTIVE;
> > +   format.pad = RWPF_PAD_SINK;
> > +   format.format.width = crop->width + crop->left;
> > +   format.format.height = crop->height + crop->top;
> > +   format.format.code = rpf->fmtinfo->mbus;
> > +   format.format.field = V4L2_FIELD_NONE;
> > +
> > +   ret = v4l2_subdev_call(>entity.subdev, pad, set_fmt, NULL,
> > +  );
> > +   if (ret < 0)
> > +   return ret;
> > +
> > +   dev_dbg(vsp1->dev,
> > +   "%s: set format %ux%u (%x) on RPF%u sink\n",
> > +   __func__, format.format.width, format.format.height,
> > +   format.format.code, rpf->entity.index);
> > +
> > +   memset(, 0, sizeof(sel));
> > +   sel.which = V4L2_SUBDEV_FORMAT_ACTIVE;
> > +   sel.pad = RWPF_PAD_SINK;
> > +   sel.target = V4L2_SEL_TGT_CROP;
> > +   sel.r = *crop;
> > +
> > +   ret = v4l2_subdev_call(>entity.subdev, pad, set_selection, NULL,
> > +  );
> > +   if (ret < 0)
> > +   return ret;
> > +
> > +   dev_dbg(vsp1->dev,
> > +   "%s: set selection (%u,%u)/%ux%u on RPF%u sink\n",
> > +   __func__, sel.r.left, sel.r.top, sel.r.width, sel.r.height,
> > +   rpf->entity.index);
> > +
> > +   /*
> > +* RPF source, hardcode the format to ARGB to turn on format
> > +* conversion if needed.
> > +*/
> > +   format.pad = RWPF_PAD_SOURCE;
> > +
> > +   ret = v4l2_subdev_call(>entity.subdev, pad, get_fmt, NULL,
> > +  );
> > +   if (ret < 0)
> > +   return ret;
> > +
> > +   dev_dbg(vsp1->dev,
> > +   "%s: got format %ux%u (%x) on RPF%u source\n",
> > +   __func__, format.format.width, format.format.height,
> > +   format.format.code, rpf->entity.index);
> > +
> > +   format.format.code = MEDIA_BUS_FMT_ARGB_1X32;
> > +
> > +   ret = v4l2_subdev_call(>entity.subdev, pad, set_fmt, NULL,
> > +  );
> > +   if (ret < 0)
> > +   return ret;
> > +
> > +   /* BRU sink, propagate the format from the RPF source. */
> > +   format.pad = bru_input;
> > +
> > +   ret = v4l2_subdev_call(>bru->subdev, pad, set_fmt, NULL,
> > +  );
> > +   if (ret < 0)
> > +   return ret;
> > +
> > +   dev_dbg(vsp1->dev, "%s: set format %ux%u (%x) on %s pad %u\n",
> > +   __func__, format.format.width, format.format.height,
> > +   format.format.code, BRU_NAME(pipe->bru), format.pad);
> > +
> > +   sel.pad = bru_input;
> > +   sel.target = V4L2_SEL_TGT_COMPOSE;
> > +   sel.r = vsp1->drm->inputs[rpf->entity.index].compose;
> > +
> > +   ret = v4l2_subdev_call(>bru->subdev, pad, set_selection, NULL,
> > +  );
> > +   if (ret < 0)
> > +   return ret;
> > +
> > +   dev_dbg(vsp1->dev, "%s: set selection (%u,%u)/%ux%u on %s pad %u\n",
> > +   __func__, sel.r.left, sel.r.top, sel.r.width, sel.r.height,
> > +   BRU_NAME(pipe->bru), sel.pad);
> > +
> > +   return 0;
> > +}
> > +
> > +static unsigned int rpf_zpos(struct vsp1_device 

Re: [PATCH 05/15] v4l: vsp1: Use vsp1_entity.pipe to check if entity belongs to a pipeline

[Laurent Pinchart]

Hi Kieran,

On Wednesday, 28 March 2018 17:10:10 EEST Kieran Bingham wrote:
> On 26/02/18 21:45, Laurent Pinchart wrote:
> > The DRM pipeline handling code uses the entity's pipe list head to check
> > whether the entity is already included in a pipeline. This method is a
> > bit fragile in the sense that it uses list_empty() on a list_head that
> > is a list member. Replace it by a simpler check for the entity pipe
> > pointer.
> 
> Yes, excellent.
> 
> > Signed-off-by: Laurent Pinchart
> > 
> 
> Reviewed-by: Kieran Bingham 
> 
> > ---
> > 
> >  drivers/media/platform/vsp1/vsp1_drm.c | 8 
> >  1 file changed, 4 insertions(+), 4 deletions(-)
> > 
> > diff --git a/drivers/media/platform/vsp1/vsp1_drm.c
> > b/drivers/media/platform/vsp1/vsp1_drm.c index a7ad85ab0b08..e210917fdc3f
> > 100644
> > --- a/drivers/media/platform/vsp1/vsp1_drm.c
> > +++ b/drivers/media/platform/vsp1/vsp1_drm.c
> > @@ -119,9 +119,9 @@ int vsp1_du_setup_lif(struct device *dev, unsigned int
> > pipe_index,> 
> >  * Remove the RPF from the pipe and the list of BRU
> >  * inputs.
> >  */
> > 
> > -   WARN_ON(list_empty(>entity.list_pipe));
> > +   WARN_ON(!rpf->entity.pipe);
> 
> Does this WARN_ON() have much value any more ?
> 
> I think it could probably be removed... unless there is a race between
> potential calls through vsp1_du_atomic_flush() and vsp1_du_setup_lif() -
> but I would be very surprised if that wasn't protected at the DRM levels.

It should indeed be protected at the DRM level. The purpose of the WARN_ON() 
is twofold, it catches both bugs in the VSP1 driver (but I don't expect any 
bug here, so from that point of view the WARN_ON isn't needed), but also 
misbehaviours in the callers. There hasn't been any so far though, so maybe we 
could indeed remove the WARN_ON(). It just makes me feel a bit safer but 
probably not in any rational way :-)

>  (Removing it if chosen doesn't need to be in this patch though)
> 
> > rpf->entity.pipe = NULL;
> > 
> > -   list_del_init(>entity.list_pipe);
> > +   list_del(>entity.list_pipe);
> > 
> > pipe->inputs[i] = NULL;
> > 
> > bru->inputs[rpf->bru_input].rpf = NULL;
> > 
> > @@ -537,7 +537,7 @@ void vsp1_du_atomic_flush(struct device *dev, unsigned
> > int pipe_index)> 
> > continue;
> > 
> > }
> > 
> > -   if (list_empty(>entity.list_pipe)) {
> > +   if (!rpf->entity.pipe) {
> > 
> > rpf->entity.pipe = pipe;
> > list_add_tail(>entity.list_pipe, >entities);
> > 
> > }
> > 
> > @@ -566,7 +566,7 @@ void vsp1_du_atomic_flush(struct device *dev, unsigned
> > int pipe_index)> 
> >VI6_DPR_NODE_UNUSED);
> > 
> > entity->pipe = NULL;
> > 
> > -   list_del_init(>list_pipe);
> > +   list_del(>list_pipe);
> > 
> > continue;
> > 
> > }

-- 
Regards,

Laurent Pinchart

Re: [PATCH 02/15] v4l: vsp1: Remove outdated comment

[Laurent Pinchart]

Hi Kieran,

On Wednesday, 28 March 2018 22:04:49 EEST Kieran Bingham wrote:
> On 28/03/18 13:27, Kieran Bingham wrote:
> > On 26/02/18 21:45, Laurent Pinchart wrote:
> >> The entities in the pipeline are all started when the LIF is setup.
> >> Remove the outdated comment that state otherwise.
> >> 
> >> Signed-off-by: Laurent Pinchart
> >> 
> > 
> > I'll start with the easy ones :-)
> 
> In fact, couldn't this patch be squashed into [PATCH 01/15] in this series ?

I suppose it could, I'll do so.

> > Reviewed-by: Kieran Bingham 
> > 
> >> ---
> >> 
> >>  drivers/media/platform/vsp1/vsp1_drm.c | 6 +-
> >>  1 file changed, 1 insertion(+), 5 deletions(-)
> >> 
> >> diff --git a/drivers/media/platform/vsp1/vsp1_drm.c
> >> b/drivers/media/platform/vsp1/vsp1_drm.c index
> >> e31fb371eaf9..a1f2ba044092 100644
> >> --- a/drivers/media/platform/vsp1/vsp1_drm.c
> >> +++ b/drivers/media/platform/vsp1/vsp1_drm.c
> >> @@ -221,11 +221,7 @@ int vsp1_du_setup_lif(struct device *dev, unsigned
> >> int pipe_index,>> 
> >>return -EPIPE;
> >>
> >>}
> >> 
> >> -  /*
> >> -   * Enable the VSP1. We don't start the entities themselves right at
> >> this
> >> -   * point as there's no plane configured yet, so we can't start
> >> -   * processing buffers.
> >> -   */
> >> +  /* Enable the VSP1. */
> >> 
> >>ret = vsp1_device_get(vsp1);
> >>if (ret < 0)
> >>
> >>return ret;


-- 
Regards,

Laurent Pinchart