The IPMMU nodes should follow the GEther node, not the CAN-FD node,
according to the part of the startng IPMMU-DS1 node.
While moving the nodes, also do sort them by label alphanumerically...
Signed-off-by: Sergei Shtylyov
---
The patch is against the 'renesas-devel-20180726-v4.18-rc6' tag
Quoting Geert Uytterhoeven (2018-07-26 08:25:24)
> All other internal clock names have a period prepended.
>
> Hence rename the internal RCLK from "rint" to ".r", and move it to the
> section where all other internal clocks are defined.
>
> Signed-off-by: Geert Uytterhoeven
> ---
Acked-by:
Add support for defining fixed rate clocks, to be used for on-chip
oscillators.
Signed-off-by: Geert Uytterhoeven
Reviewed-by: Simon Horman
---
v2:
- Add Reviewed-by.
---
drivers/clk/renesas/renesas-cpg-mssr.c | 5 +
drivers/clk/renesas/renesas-cpg-mssr.h | 3 +++
2 files changed, 8
Make the existing support for selecting between clean and SSCG clocks
using MD12 more generic, to allow using other mode pins for arbitrary
clock selection.
Signed-off-by: Geert Uytterhoeven
Reviewed-by: Simon Horman
---
v2:
- Add Reviewed-by.
---
drivers/clk/renesas/rcar-gen3-cpg.c | 10
R-Car Gen3 Hardware Manual Rev.0.52 documents the relation between the
MD13 and MD14 mode pins, and the OSC EXTAL predivider, as used by the
OSC and RINT RCLK clocks. Hence augment the configuration structure
with all documented predivider values.
According to R-Car Gen3 Hardware Manual
R-Car Gen3 Hardware Manual Rev.0.52 documents the relation between the
MD13 and MD14 mode pins, and the OSC EXTAL predivider, as used by the
OSC and RINT RCLK clocks. Hence augment the configuration structure
with all documented predivider values.
According to R-Car Gen3 Hardware Manual
On R-Car V3H, RCLK can be switched between EXTALR and the On-Chip
Oscillator using mode pin MD19.
Signed-off-by: Geert Uytterhoeven
Reviewed-by: Simon Horman
---
v2:
- Add Reviewed-by,
- Rename "oco" to ".oco", as it is an internal clock.
As Figure 8.1e "Block Diagram of CPG (R-Car V3H)"
R-Car Gen3 Hardware Manual Rev.0.52 documents the relation between the
MD13 and MD14 mode pins, and the OSC EXTAL predivider, as used by the
OSC and RINT RCLK clocks. Hence augment the configuration structure
with all documented predivider values.
According to R-Car Gen3 Hardware Manual
According to R-Car Gen3 Hardware Manual Rev.1.00, R-Car D3 has the
RCLK Frequency Control Register (RCKCR), which determines the OSC and
RINT predivider values, and selection of the RCLK clock source between
RINT and the On-Chip Oscillator.
Hence change the OSC and RINT clock definitions to use
R-Car Gen3 Hardware Manual Rev.0.54 documents the relation between the
MD13 and MD14 mode pins, and the OSC EXTAL predivider, as used by the
OSC clock. Hence augment the configuration structure with all
documented predivider values.
Add the OSC clock using the configured predivider.
Add a clock type and macro for defining clocks where the parent and
divider are selected based on the value of the RCKCR.CKSEL bit.
Signed-off-by: Geert Uytterhoeven
Reviewed-by: Simon Horman
---
v2:
- Add Reviewed-by,
- Drop extra blank line.
---
drivers/clk/renesas/rcar-gen3-cpg.c | 23
Add a clock type and macro for defining clocks using the OSC EXTAL
predivider combined with a fixed divider.
On most R-Car Gen3 SoCs, the predivider value depends on mode pins, and
thus must be specified in the configuration structure.
Inspired by a patch in the BSP by Takeshi Kihara
.
According to R-Car Gen3 Hardware Manual Rev.1.00, R-Car E3 has the
RCLK Frequency Control Register (RCKCR), which determines the OSC and
RINT predivider values, and selection of the RCLK clock source between
RINT and the On-Chip Oscillator.
Hence change the OSC and RINT clock definitions to use
Hi all,
This patch series contains various improvements for OSC and RCLK
handling on R-Car Gen3 SoCs.
Changes compared to v1:
- Add Reviewed-by,
- Fix OSC predivider for 27 MHz EXTAL on R-Car V3H,
- Rename "r_int" to ".r", and "oco" to ".oco", as they are internal
clocks,
-
All other internal clock names have a period prepended.
Hence rename the internal RCLK from "rint" to ".r", and move it to the
section where all other internal clocks are defined.
Signed-off-by: Geert Uytterhoeven
---
To be queued in clk-renesas-for-v4.20.
On Thu, Jul 26, 2018 at 03:59:05PM +0300, Laurent Pinchart wrote:
> Hi Simon,
>
> On Wednesday, 6 June 2018 11:44:22 EEST Simon Horman wrote:
> > On Tue, Jun 05, 2018 at 12:51:04PM +0300, Laurent Pinchart wrote:
> > > Hello,
> > >
> > > This small patch series contains the last two remaining
On Thu, Jul 26, 2018 at 01:51:18PM +0200, Geert Uytterhoeven wrote:
> On Wed, Jul 25, 2018 at 11:22 PM Chris Brandt
> wrote:
> > Add the RZ/A2 SoC to the Renesas SoC collection.
> >
> > Signed-off-by: Chris Brandt
>
> Reviewed-by: Geert Uytterhoeven
Thanks, applied for v4.20.
I'm expecting
On Thu, Jul 26, 2018 at 02:33:55PM +0200, Geert Uytterhoeven wrote:
> On Wed, Jul 25, 2018 at 7:34 PM Geert Uytterhoeven
> wrote:
> > On Wed, Jul 25, 2018 at 6:44 PM Sergei Shtylyov
> > wrote:
> > > Describe the performance monitor unit (PMU) for the Cortex-A53 cores in
> > > the R8A77970 SoC's
On Wed, Jul 25, 2018 at 09:15:46PM +0200, Wolfram Sang wrote:
> From: Takeshi Kihara
>
> This patch adds SATA0 pin, group and function to the R8A77965 SoC.
>
> Signed-off-by: Takeshi Kihara
> [wsa: rebased to upstream base]
> Signed-off-by: Wolfram Sang
Reviewed-by: Simon Horman
On Wed, Jul 25, 2018 at 09:34:55PM +0200, Wolfram Sang wrote:
> Since Geert also argumented that it is reasonable to have this in the board
> DTS
> files [1], I converted the RFC into proper patches. So, SATA will be available
> out of the box for H3 and M3-N if MD12 is switched off properly.
>
On Wed, Jul 25, 2018 at 09:16:55PM +0200, Wolfram Sang wrote:
> Update the binding docs for Renesas R-Car M3-N. No driver changes are
> needed.
>
> Signed-off-by: Wolfram Sang
Reviewed-by: Simon Horman
On Wed, Jul 25, 2018 at 09:14:17PM +0200, Wolfram Sang wrote:
> From: Takeshi Kihara
>
> This patch adds SATA clock to the R8A77965 SoC.
>
> Signed-off-by: Takeshi Kihara
> [wsa: rebased to upstream base]
> Signed-off-by: Wolfram Sang
Reviewed-by: Simon Horman
On Tue, Jul 24, 2018 at 04:47:15PM +0100, Biju Das wrote:
> This patch series aims to add SoC identification support
> for RZ/G2M SoC. RZ/G2M SoC is similar to R-Car Gen3 M3-W SoC.
>
>
> Biju Das (3):
> dt-bindings: arm: Document RZ/G2M SoC DT bindings
> arm64: Add Renesas R8A774A1 support
On Thu, Jul 26, 2018 at 05:40:15AM +0900, Yoshihiro Kaneko wrote:
> From: Hiroyuki Yokoyama
>
> Document support for the sound modules in the Renesas M3-N (r8a77965)
> SoC.
>
> No driver update is needed.
>
> Signed-off-by: Hiroyuki Yokoyama
> Signed-off-by: Yoshihiro Kaneko
Reviewed-by:
Hi Geert,
On Thursday, July 26, 2018, Geert Uytterhoeven wrote:
> > In your opinion, which one would be better (revert or rebase)?
>
> [looking at the incremental differences]
>
> I think the easiest for Greg is to rebase, and send 3 patches:
> 1. Document interrupt order in bindings,
> 2.
On Tue, Jun 05, 2018 at 12:51:04PM +0300, Laurent Pinchart wrote:
> Hello,
>
> This small patch series contains the last two remaining patches from
> "[PATCH v4 00/16] R-Car DU: Convert LVDS code to bridge driver". Apart from
> the individual SoC patches being squashed together as requested by
Hi Chris,
On Thu, Jul 26, 2018 at 2:25 PM Chris Brandt wrote:
> On Thursday, July 26, 2018, Geert Uytterhoeven wrote:
> > Thanks for your series!
> >
> > Unfortunately Greg has already applied your v1 (and my fix for a
> > use-after-free), so either these have to be reverted first, or you have
Hi Simon,
On Wednesday, 6 June 2018 11:44:22 EEST Simon Horman wrote:
> On Tue, Jun 05, 2018 at 12:51:04PM +0300, Laurent Pinchart wrote:
> > Hello,
> >
> > This small patch series contains the last two remaining patches from
> > "[PATCH v4 00/16] R-Car DU: Convert LVDS code to bridge driver".
Hi Geert,
Thanks for your review!
On Thursday, July 26, 2018, Geert Uytterhoeven wrote:
> > struct renesas_family {
> > const char name[16];
> > - u32 reg;/* CCCR or PRR, if not in DT */
> > + u32 reg;/* CCCR, PRR or BSID, if
Hi Chris,
On Thu, Jul 26, 2018 at 2:14 PM Chris Brandt wrote:
> On Thursday, July 26, 2018, Geert Uytterhoeven wrote:
> > On Wed, Jul 25, 2018 at 4:39 PM Chris Brandt
> > wrote:
> > > Some devices with SCIx_SH4_SCIF_REGTYPE have no space between registers.
> > > Use the register area size to
On Wed, Jul 25, 2018 at 7:34 PM Geert Uytterhoeven wrote:
> On Wed, Jul 25, 2018 at 6:44 PM Sergei Shtylyov
> wrote:
> > Describe the performance monitor unit (PMU) for the Cortex-A53 cores in
> > the R8A77970 SoC's device tree.
>
> 8?
With that fixes:
Reviewed-by: Geert Uytterhoeven
On Wed, Jul 25, 2018 at 9:15 PM Wolfram Sang
wrote:
> From: Takeshi Kihara
>
> This patch adds SATA0 pin, group and function to the R8A77965 SoC.
>
> Signed-off-by: Takeshi Kihara
> [wsa: rebased to upstream base]
> Signed-off-by: Wolfram Sang
Reviewed-by: Geert Uytterhoeven
i.e. will queue
On Wed, Jul 25, 2018 at 9:35 PM Wolfram Sang
wrote:
> Add the nodes to enable SATA. Note that MD12 (SW12-7) must be switched
> off for that to work.
>
> Signed-off-by: Wolfram Sang
Reviewed-by: Geert Uytterhoeven
> --- a/arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts
> +++
Hi Wolfram
On Wed, Jul 25, 2018 at 9:35 PM Wolfram Sang
wrote:
> Add the nodes to enable SATA. Note that MD12 (SW12-7) must be switched
> off for that to work.
Thanks for your patch!
> Signed-off-by: Wolfram Sang
> Tested-by: Geert Uytterhoeven
Reviewed-by: Geert Uytterhoeven
> ---
Hi Geert,
On Thursday, July 26, 2018, Geert Uytterhoeven wrote:
> Thanks for your series!
>
> Unfortunately Greg has already applied your v1 (and my fix for a
> use-after-free), so either these have to be reverted first, or you have to
> rebase against tty-next.
I assume you would prefer the
Hi Wolfram,
On Wed, Jul 25, 2018 at 9:18 PM Wolfram Sang
wrote:
> From: Takeshi Kihara
>
> This patch adds SATA controller node for the R8A77965 SoC.
Thanks for your patch!
> Signed-off-by: Takeshi Kihara
> [wsa: rebased to upstream base]
> Signed-off-by: Wolfram Sang
Reviewed-by: Geert
Hi Geert,
On Thursday, July 26, 2018, Geert Uytterhoeven wrote:
> With the below typo fixed:
> Reviewed-by: Geert Uytterhoeven
OK, I will fix the typo and resend.
Thank you.
Chris
Hi Geert,
On Thursday, July 26, 2018, Geert Uytterhoeven wrote:
> > +static irqreturn_t sci_br_interrupt(int irq, void *ptr);
>
> You can avoid the forward declaration by moving the whole function here.
OK.
> > @@ -2809,6 +2845,8 @@ static int sci_init_single(struct platform_device
> *dev,
> >
On Wed, Jul 25, 2018 at 9:17 PM Wolfram Sang
wrote:
> Update the binding docs for Renesas R-Car M3-N. No driver changes are
> needed.
>
> Signed-off-by: Wolfram Sang
Reviewed-by: Geert Uytterhoeven
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of
On Wed, Jul 25, 2018 at 9:14 PM Wolfram Sang
wrote:
> From: Takeshi Kihara
>
> This patch adds SATA clock to the R8A77965 SoC.
>
> Signed-off-by: Takeshi Kihara
> [wsa: rebased to upstream base]
> Signed-off-by: Wolfram Sang
Reviewed-by: Geert Uytterhoeven
i.e. will queue in
Hi Geert,
On Thursday, July 26, 2018, Geert Uytterhoeven wrote:
> Hi Chris,
>
> On Wed, Jul 25, 2018 at 4:39 PM Chris Brandt
> wrote:
> > Some devices with SCIx_SH4_SCIF_REGTYPE have no space between registers.
> > Use the register area size to determine the spacing between register.
> >
> >
Hi Chris,
On Wed, Jul 25, 2018 at 11:22 PM Chris Brandt wrote:
> Add support for identifying the RZ/A2M (R7S9210) SoC.
> Also add support for reading the BSID register which is a different format
> than the PRR.
>
> Signed-off-by: Chris Brandt
Thanks for your patch!
> ---
On Wed, Jul 25, 2018 at 11:22 PM Chris Brandt wrote:
> Add the RZ/A2 SoC to the Renesas SoC collection.
>
> Signed-off-by: Chris Brandt
Reviewed-by: Geert Uytterhoeven
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 --
Hi Biju,
On Tue, Jul 24, 2018 at 5:53 PM Biju Das wrote:
> This patch adds support for identifying the RZ/G2M (r8a774a1) SoC.
> It corrects the original RZ/G SoC family name to RZ/G1 and also
> adds support for the new RZ/G2 SoC family.
Note that there are no in-kernel users (e.g.
On Tue, Jul 24, 2018 at 5:53 PM Biju Das wrote:
> Add configuration option for the RZ/G2M (R8A774A1) SoC.
>
> Signed-off-by: Biju Das
> Reviewed-by: Chris Paterson
Reviewed-by: Geert Uytterhoeven
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of
On Tue, Jul 24, 2018 at 5:53 PM Biju Das wrote:
> Add device tree bindings documentation for Renesas RZ/G2M (r8a774a1) SoC.
>
> Signed-off-by: Biju Das
> Reviewed-by: Chris Paterson
Reviewed-by: Geert Uytterhoeven
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven --
Hi Chris,
On Wed, Jul 25, 2018 at 4:39 PM Chris Brandt wrote:
> The RZ/A2 uses a modified SCIF that until recently was only used in
> Renesas MCU devices (not MPU devices).
> So, while it functions mostly the same as a normal SCIF, some things
> needed to be shifted around.
>
> In the end, a
Hi Chris,
On Wed, Jul 25, 2018 at 4:39 PM Chris Brandt wrote:
> Add R7S9210 (RZ/A2) support.
> Also describe interrupts property in more detail.
>
> Signed-off-by: Chris Brandt
> ---
> v2:
> * Add more details to interrupts property
> * Geert gave a Reviewed-by for V1, but then later said
Hi Chris,
On Wed, Jul 25, 2018 at 4:39 PM Chris Brandt wrote:
> Some SCIF versions mux error and break interrupts together and then provide
> a separate interrupt ID for just TEI/DRI.
>
> Allow all 6 types of interrupts to be specified via platform data (or DT)
> and for any signals that are
Hi Chris,
On Wed, Jul 25, 2018 at 4:39 PM Chris Brandt wrote:
> Some devices with SCIx_SH4_SCIF_REGTYPE have no space between registers.
> Use the register area size to determine the spacing between register.
>
> Signed-off-by: Chris Brandt
Reviewed-by: Geert Uytterhoeven
> ---
Hi Geert,
On Thursday, July 26, 2018, Geert Uytterhoeven wrote:
> > @@ -148,7 +150,7 @@ product and revision information. If present, a
> device node for this register
> > should be added.
>
> Please add "or Boundary Scan ID Register" to the paragraph above.
OK.
Chris
> I agree but I could not find a neat way of doing it. How about?
>
> bool use_4tap = host->pdata->flags & TMIO_MMC_HAVE_4TAP_HS400;
>
> if (!(host->mmc->ios.timing == MMC_TIMING_UHS_SDR104) &&
> !(host->mmc->ios.timing == MMC_TIMING_MMC_HS200) &&
> !(host->mmc->ios.timing
On Mon, Jul 23, 2018 at 02:04:13PM +0200, Simon Horman wrote:
> Hi Olof, Hi Kevin, Hi Arnd,
>
> Please consider these Renesas ARM based SoC defconfig updates for v4.19.
>
> Changes since v1:
> * Dropped patch to set CONFIG_LOCALVERSION as requested by Olof
> * Dropped patch to Enable MTD command
On Wed, Jul 25, 2018 at 11:48:09AM +0100, Sudeep Holla wrote:
> Commit 7f9545aa1a91 ("arm64: smp: remove cpu and numa topology
> information when hotplugging out CPU") updates the cpu topology when
> the CPU is hotplugged out. However the PSCI checker code uses the
> topology_core_cpumask pointers
On Mon, Jul 23, 2018 at 02:04:47PM +0200, Simon Horman wrote:
> Hi Olof, Hi Kevin, Hi Arnd,
>
> Please consider these Renesas ARM based SoC DT updates for v4.19.
>
> Changes since v1:
> * Dropped patch which removes MTD partitioning from DT,
> Olof requested more discussion of this
> * Trimmed
Hi Chris,
On Wed, Jul 25, 2018 at 11:22 PM Chris Brandt wrote:
> Add device tree bindings documentation for Renesas RZ/A2 (r7s9210) SoC.
> Also document new option for "renesas,bsid"
>
> Signed-off-by: Chris Brandt
Thanks for ypur patch!
> ---
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