On 25-07-18, 17:27, Yoshihiro Shimoda wrote:
> rcar_dmac_chan_get_residue() should not stop the DMAC, because
> the commit 538603c6026c ("dmaengine: sh: rcar-dmac: avoid to write
> CHCR.TE to 1 if TCR is set to 0") had fixed unexpected re-transferring
> issue. But it had caused the next issue
On Wed, Jul 25, 2018 at 09:38:50AM -0500, Chris Brandt wrote:
> Add R7S9210 (RZ/A2) support.
> Also describe interrupts property in more detail.
>
> Signed-off-by: Chris Brandt
> ---
> v2:
> * Add more details to interrupts property
> * Geert gave a Reviewed-by for V1, but then later said that
On Fri, Jul 27, 2018 at 11:53:33AM -0500, Chris Brandt wrote:
> Add device tree bindings documentation for Renesas RZ/A2 (r7s9210) SoC.
> Also document new option for "renesas,bsid"
>
> Signed-off-by: Chris Brandt
> Reviewed-by: Geert Uytterhoeven
> ---
> v3:
> * added "or Boundary Scan ID
The CAN clock node should precede the "cpus" node in the R8A779{7|8}0
device trees, according to the alphanumeric node sorting rule...
Signed-off-by: Sergei Shtylyov
---
The patch is against the 'renesas-devel-20180726-v4.18-rc6' tag of Simon
Horman's 'renesas.git' repo.
Hi Shimoda-san,
On Mon, Jul 30, 2018 at 1:55 PM Yoshihiro Shimoda
wrote:
> This patch adds PWM device nodes and enables PWM3 and PWM5 for
> R-Car E3 Ebisu board.
Thanks for your patch!
This is used for blacklight control, right?
It may be a good idea to mention that in the comments and/or
On Mon, Jul 30, 2018 at 1:49 PM Yoshihiro Shimoda
wrote:
> From: Takeshi Kihara
>
> This patch adds PWM{0,1,2,3,4,5,6} pins, groups and functions to
> the R8A77990 SoC.
>
> Signed-off-by: Takeshi Kihara
> Signed-off-by: Yoshihiro Shimoda
Reviewed-by: Geert Uytterhoeven
i.e. will queue in
On Mon, Jul 30, 2018 at 1:51 PM Yoshihiro Shimoda
wrote:
> This patch adds bindings for R-Car E3. No driver update is needed.
>
> Signed-off-by: Yoshihiro Shimoda
Reviewed-by: Geert Uytterhoeven
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux
Hi Biju,
On Fri, Jul 27, 2018 at 11:57 AM Biju Das wrote:
> Adding pinctrl support for EtherAVB interface.
>
> Signed-off-by: Biju Das
> Reviewed-by: Fabrizio Castro
Thanks for the update!
> --- a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
> +++ b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
>
On 24 July 2018 at 16:51, Niklas Söderlund
wrote:
> Hi,
>
> Tuning failed on my R-Car H3 ES2.0 board using latest mmc/next while the
> Renesas BSP kernel worked. After some digging I found patches in the BSP
> which remedied this and whit these applied tuning now works for me.
>
> I have done
On 26 July 2018 at 05:28, Masahiro Yamada wrote:
> As commit b6147490e6aa ("mmc: tmio: split core functionality, DMA and
> MFD glue") said, these MMC controllers use the IP from Panasonic.
>
> TMIO (Toshiba Mobile IO) MMC was the first upstreamed user of this IP.
> The common driver code was
On 21 July 2018 at 13:14, Wolfram Sang wrote:
> This patch adds SDHI support for the R8A77990 SoC (R-Car E3). No driver
> changes
> needed for anything except HS400 which we will enable separately later.
>
> Signed-off-by: Wolfram Sang
Thanks, applied for next!
Kind regards
Uffe
> ---
>
>
Hi Biju,
On Fri, Jul 27, 2018 at 11:29 AM Biju Das wrote:
>
> + sergie
>
> > -Original Message-
> > From: Biju Das [mailto:biju@bp.renesas.com]
> > Sent: 27 July 2018 10:22
> > To: Laurent Pinchart ; Geert
> > Uytterhoeven ; Linus Walleij
> >
> > Cc: Biju Das ; linux-renesas-
> >
On Mon, Jul 30, 2018 at 3:17 PM Chris Brandt wrote:
> Some devices with SCIx_SH4_SCIF_REGTYPE have no space between registers.
> Use the register area size to determine the spacing between register.
>
> Signed-off-by: Chris Brandt
> ---
> v2:
> * adjust for case of SCIx_PROBE_REGTYPE
There is no more need for SCIx_RZ_SCIFA_REGTYPE now that
SCIx_SH4_SCIF_REGTYPE can provide the same register/address definitions.
Also, R7S9210 no longer needs a special compatible since the standard
"renesas,scif" will work just fine.
Signed-off-by: Chris Brandt
Reviewed-by: Geert Uytterhoeven
Some SCIF versions mux error and break interrupts together and then provide
a separate interrupt ID for just TEI/DRI.
Allow all 6 types of interrupts to be specified via platform data (or DT)
and for any signals that are muxed together (have the same interrupt
number) simply register one handler.
Some devices with SCIx_SH4_SCIF_REGTYPE have no space between registers.
Use the register area size to determine the spacing between register.
Signed-off-by: Chris Brandt
---
v2:
* adjust for case of SCIx_PROBE_REGTYPE
---
drivers/tty/serial/sh-sci.c | 25 +++--
1 file
This patch series doesn't really provide much new functionality, but
rather provides a cleaner solution for adding RZ/A2 support.
This series applies on top of tty-next
v2:
* Incorporated feedback from Geert
* Added Reviewed-by
Chris Brandt (4):
serial: sh-sci: Improve interrupts description
Describe interrupts property in more detail, especially when there are
more than one interrupt.
Signed-off-by: Chris Brandt
Reviewed-by: Geert Uytterhoeven
---
.../devicetree/bindings/serial/renesas,sci-serial.txt| 16 +++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff
Hi Geert,
On Monday, July 30, 2018, Geert Uytterhoeven wrote:
> That's not the array, but the enum.
>
> The array is in struct sci_port:
>
> int irqs[SCIx_NR_IRQS];
>
> It has four entries, at indices 0..3.
> irqs[SCIx_NR_IRQS] does not exist!
>
>
Hi Chris,
On Mon, Jul 30, 2018 at 2:33 PM Chris Brandt wrote:
> On Monday, July 30, 2018, Geert Uytterhoeven wrote:
> > > if (sci_port->irqs[0] < 0)
> > > return -ENXIO;
> > >
> > > - if (sci_port->irqs[1] < 0) {
> > > - sci_port->irqs[1] =
This patch adds PWM device nodes and enables PWM3 and PWM5 for
R-Car E3 Ebisu board.
Signed-off-by: Yoshihiro Shimoda
---
I have submitted dt-bindings for R-Car E3 (not merged into PWM subsystem yet):
https://patchwork.kernel.org/patch/10548969/
arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
From: Takeshi Kihara
This patch adds PWM{0,1,2,3,4,5,6} pins, groups and functions to
the R8A77990 SoC.
Signed-off-by: Takeshi Kihara
Signed-off-by: Yoshihiro Shimoda
---
drivers/pinctrl/sh-pfc/pfc-r8a77990.c | 211 ++
1 file changed, 211 insertions(+)
diff
On 06/13/2018 01:21 PM, Geert Uytterhoeven wrote:
> Hi Simon,
Hi,
> On Wed, Jun 13, 2018 at 1:06 PM Simon Horman wrote:
>> On Mon, Jun 11, 2018 at 02:15:13PM +0200, Marek Vasut wrote:
>>> Rather than hard-coding the quirk topology, which stopped scaling,
>>> parse the information from DT. The
Add DA9063 PMIC node to the I2C bus.
Signed-off-by: Marek Vasut
Cc: Geert Uytterhoeven
Cc: Kuninori Morimoto
Cc: Simon Horman
Cc: Wolfram Sang
Cc: linux-renesas-soc@vger.kernel.org
---
arch/arm/boot/dts/r8a7794-silk.dts | 12
1 file changed, 12 insertions(+)
diff --git
Add DA9210 DVFS node to the I2C bus and link it to CPU0 for DVFS.
Signed-off-by: Marek Vasut
Cc: Geert Uytterhoeven
Cc: Kuninori Morimoto
Cc: Simon Horman
Cc: Wolfram Sang
Cc: linux-renesas-soc@vger.kernel.org
---
arch/arm/boot/dts/r8a7793-gose.dts | 16
1 file changed, 16
Hi Geert,
Thanks for the feedback.
> -Original Message-
> From: Geert Uytterhoeven [mailto:ge...@linux-m68k.org]
> Sent: 30 July 2018 11:04
> To: Biju Das
> Cc: Linus Walleij ; open list:GPIO SUBSYSTEM
> ; Simon Horman ;
> Geert Uytterhoeven ; Chris Paterson
> ; Fabrizio Castro
> ;
On Fri, Jul 27, 2018 at 11:57 AM Biju Das wrote:
> Specify EtherAVB PHY IRQ in the board specific device tree, now that we
> have GPIO support.
>
> Signed-off-by: Biju Das
> Reviewed-by: Fabrizio Castro
Reviewed-by: Geert Uytterhoeven
Gr{oetje,eeting}s,
Geert
--
Hi Biju,
On Fri, Jul 27, 2018 at 11:57 AM Biju Das wrote:
> Enhance gpio-ranges to support more than one gpio-range.
>
> Signed-off-by: Biju Das
> Reviewed-by: Fabrizio Castro
Thanks for your patch!
However, I'm wondering if this works as intended, as the discontinuity is
not in the pins,
Hi Kaneko-san,
On Wed, Jul 25, 2018 at 10:42 PM Yoshihiro Kaneko wrote:
> From: Dien Pham
>
> This patch adds OPPs table for CA57{0,1} cpu devices
>
> Signed-off-by: Dien Pham
> Signed-off-by: Takeshi Kihara
> Signed-off-by: Yoshihiro Kaneko
Syntax looks good, but I cannot review the actual
On Wed, Jul 25, 2018 at 10:29 AM Yoshihiro Shimoda
wrote:
> rcar_dmac_chan_get_residue() should not stop the DMAC, because
> the commit 538603c6026c ("dmaengine: sh: rcar-dmac: avoid to write
> CHCR.TE to 1 if TCR is set to 0") had fixed unexpected re-transferring
> issue. But it had caused the
Hi Chris,
On Fri, Jul 27, 2018 at 11:09 PM Chris Brandt wrote:
> Some SCIF versions mux error and break interrupts together and then provide
> a separate interrupt ID for just TEI/DRI.
>
> Allow all 6 types of interrupts to be specified via platform data (or DT)
> and for any signals that are
Hi Morimoto-san,
Thanks for your patch.
On 2018-07-30 07:57:22 +, Kuninori Morimoto wrote:
>
> From: Kuninori Morimoto
>
> Signed-off-by: Kuninori Morimoto
Reviewed-by: Niklas Söderlund
> ---
> drivers/thermal/rcar_gen3_thermal.c | 11 +--
> 1 file changed, 1 insertion(+), 10
On 30/07/2018 09:57, Kuninori Morimoto wrote:
>
> From: Kuninori Morimoto
>
> Signed-off-by: Kuninori Morimoto
Reviewed-by: Daniel Lezcano
Adding Cc: Philippe Ombredanne
> ---
> drivers/thermal/rcar_gen3_thermal.c | 11 +--
> 1 file changed, 1 insertion(+), 10 deletions(-)
>
>
On Mon, Jul 30, 2018 at 9:57 AM Kuninori Morimoto
wrote:
> From: Kuninori Morimoto
>
> Signed-off-by: Kuninori Morimoto
Reviewed-by: Geert Uytterhoeven
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In
On Mon, Jul 30, 2018 at 9:56 AM Kuninori Morimoto
wrote:
> From: Kuninori Morimoto
>
> As original license mentioned, it is GPL-2.0 in SPDX.
> Then, MODULE_LICENSE() should be "GPL v2" instead of "GPL".
> See ${LINUX}/include/linux/module.h
>
> "GPL" [GNU Public License v2 or
On 30/07/2018 09:56, Kuninori Morimoto wrote:
>
> From: Kuninori Morimoto
>
> As original license mentioned, it is GPL-2.0 in SPDX.
> Then, MODULE_LICENSE() should be "GPL v2" instead of "GPL".
> See ${LINUX}/include/linux/module.h
>
> "GPL" [GNU Public License v2 or later]
>
On Fri, Jul 27, 2018 at 6:53 PM Chris Brandt wrote:
> Add support for identifying the RZ/A2M (R7S9210) SoC.
+ correct the original RZ/A SoC family name to RZ/A1?
> Also add support for reading the BSID register which is a different format
> than the PRR.
>
> Signed-off-by: Chris Brandt
> ---
>
Hi Chris,
On Sun, Jul 29, 2018 at 1:11 PM Geert Uytterhoeven wrote:
> On Fri, Jul 27, 2018 at 11:09 PM Chris Brandt
> wrote:
> > Some devices with SCIx_SH4_SCIF_REGTYPE have no space between registers.
> > Use the register area size to determine the spacing between register.
> >
> >
From: Kuninori Morimoto
Signed-off-by: Kuninori Morimoto
---
drivers/thermal/rcar_gen3_thermal.c | 11 +--
1 file changed, 1 insertion(+), 10 deletions(-)
diff --git a/drivers/thermal/rcar_gen3_thermal.c
b/drivers/thermal/rcar_gen3_thermal.c
index 766521e..7aed533 100644
---
From: Kuninori Morimoto
As original license mentioned, it is GPL-2.0 in SPDX.
Then, MODULE_LICENSE() should be "GPL v2" instead of "GPL".
See ${LINUX}/include/linux/module.h
"GPL" [GNU Public License v2 or later]
"GPL v2"[GNU Public License v2]
Signed-off-by: Biju Das
Reviewed-by: Chris Paterson
---
Documentation/devicetree/bindings/reset/renesas,rst.txt | 1 +
drivers/soc/renesas/Kconfig | 6 +++---
drivers/soc/renesas/rcar-rst.c | 4 +++-
3 files changed, 7 insertions(+), 4
Add all RZ/G2M Clock Pulse Generator Core Clock Outputs, as listed in
Table 8.2b ("List of Clocks [RZ/G2M]") of the RZ/G2M Hardware User's
Manual.
Signed-off-by: Biju Das
Reviewed-by: Fabrizio Castro
---
include/dt-bindings/clock/r8a774a1-cpg-mssr.h | 59 +++
1 file
Add RZ/G2M (R8A774A1) Clock Pulse Generator / Module Standby and Software
Reset support.
Based on the Table 8.2b of "RZ/G Series, 2nd Generation User's Manual:
Hardware ((Rev. 0.61, June 12, 2018)".
Signed-off-by: Biju Das
Reviewed-by: Fabrizio Castro
---
Add support for RZ/G2M (R8A774A1) SoC power areas to the R-Car SYSC
driver.
Signed-off-by: Biju Das
Reviewed-by: Chris Paterson
---
.../bindings/power/renesas,rcar-sysc.txt | 1 +
drivers/soc/renesas/Kconfig| 5 +++
drivers/soc/renesas/Makefile
This patch adds power domain indices for RZ/G2M.
Signed-off-by: Biju Das
Reviewed-by: Chris Paterson
---
include/dt-bindings/power/r8a774a1-sysc.h | 31 +++
1 file changed, 31 insertions(+)
create mode 100644 include/dt-bindings/power/r8a774a1-sysc.h
diff --git
This patch series aims to add SYSC/RST/Clock support for
for RZ/G2M SoC. RZ/G2M SoC is similar to R-Car Gen3 M3-W SoC.
Biju Das (5):
dt-bindings: power: Add r8a774a1 SYSC power domain definitions
soc: renesas: rcar-sysc: Add r8a774a1 support
soc: renesas: rcar-rst: Add support for RZ/G2M
Add the nodes to enable SATA. Note that MD12 (SW12-7) must be switched
off for that to work.
Signed-off-by: Wolfram Sang
Reviewed-by: Geert Uytterhoeven
---
Changes since v1:
* fixed indentation (Thanks, Geert!)
* merged two patches into one (Thanks, Simon!)
* Added
From: Takeshi Kihara
This patch adds SATA controller node for the R8A77965 SoC.
Signed-off-by: Takeshi Kihara
[wsa: rebased to upstream base]
Reviewed-by: Geert Uytterhoeven
Signed-off-by: Wolfram Sang
---
Changes since v1:
* sorted it according to address (Thanks, Geert!)
*
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