Fix the typo in the comment to #define DTRAN_MODE_CH_NUM_CH1.
Signed-off-by: Sergei Shtylyov
---
drivers/mmc/host/renesas_sdhi_internal_dmac.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Index: mmc/drivers/mmc/host/renesas_sdhi_internal_dmac.c
Fix a stray underscore in the DM_CM_DTRAN_MODE.BUS_WIDTH register field
name.
Signed-off-by: Sergei Shtylyov
---
drivers/mmc/host/renesas_sdhi_internal_dmac.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
Index: mmc/drivers/mmc/host/renesas_sdhi_internal_dmac.c
Hello!
Here's a set of 2 patches against the 'next' branch of Ulf Hannsson's 'mmc.git'
repo.
They fix some typos I noticed...
[1/2] mmc: renesas_sdhi_internal_dmac: fix typo in DM_CM_DTRAN_MODE.BUS_WIDTH
field name
[2/2] mmc: renesas_sdhi_internal_dmac: fix comment typo
MBR. Sergei
I have encountered an interrupt storm during the eMMC chip probing (and
the chip finally didn't get detected). It turned out that U-Boot left
the SDHI DMA interrupts enabled while the Linux driver didn't use those.
Masking those interrupts in renesas_sdhi_internal_dmac_request_dma() gets
rid
Hi Kieran,
On Fri, Aug 17, 2018 at 05:10:06PM +0100, Kieran Bingham wrote:
> Hi Eugeniu,
>
> On 17/08/18 16:56, Eugeniu Rosca wrote:
> > Hello Kieran,
> >
> > On Fri, Aug 17, 2018 at 02:44:25PM +0100, Kieran Bingham wrote:
> >> Hi Eugeniu
> >>
> >> Thank you for the patch.
> >>
> >> On 12/08/18
Hi Eugeniu,
On 17/08/18 16:56, Eugeniu Rosca wrote:
> Hello Kieran,
>
> On Fri, Aug 17, 2018 at 02:44:25PM +0100, Kieran Bingham wrote:
>> Hi Eugeniu
>>
>> Thank you for the patch.
>>
>> On 12/08/18 14:31, Eugeniu Rosca wrote:
>>> Document the support for rcar_can on R8A77965 SoC devices.
>>>
Hello Kieran,
On Fri, Aug 17, 2018 at 02:44:25PM +0100, Kieran Bingham wrote:
> Hi Eugeniu
>
> Thank you for the patch.
>
> On 12/08/18 14:31, Eugeniu Rosca wrote:
> > Document the support for rcar_can on R8A77965 SoC devices.
> > Add R8A77965 to the list of SoCs which require the
Add r8a774a1 specific compatible string.
Signed-off-by: Fabrizio Castro
Reviewed-by: Biju Das
---
This patch applies on top of renesas-drivers-2018-07-31-v4.18-rc7
drivers/thermal/rcar_gen3_thermal.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/thermal/rcar_gen3_thermal.c
Hi Eugeniu,
Thank you for the patch,
On 12/08/18 14:31, Eugeniu Rosca wrote:
> According to R-Car Gen3 HW manual rev1.00, R-Car M3-N has two CAN
> interfaces, similar to H3, M3-W and other SoCs from the same family.
>
> Add CAN placeholder nodes to avoid below DTC errors:
> Error:
Hi Eugeniu,
On 06/08/18 21:14, Eugeniu Rosca wrote:
> Hi Kieran,
>
> On Mon, Aug 06, 2018 at 12:11:22PM +0100, Kieran Bingham wrote:
>> Hi Eugeniu,
>>
>> On 05/08/18 00:11, Eugeniu Rosca wrote:
>>> According to R-Car Gen3 HW manual rev0.55E, R-Car M3-N has two CAN
>>
>> rev 0.55E sounds like
Hi Eugeniu
Thank you for the patch.
On 12/08/18 14:31, Eugeniu Rosca wrote:
> Document the support for rcar_can on R8A77965 SoC devices.
> Add R8A77965 to the list of SoCs which require the "assigned-clocks" and
> "assigned-clock-rates" properties (thanks, Sergei). Rewrap text.
I don't think
Hi!
This series adds CPU idle support for H3 and M3-W. It's a straight
up-port from the BSP.
The part that disables cpuidle for the CA53 cores on M3ULCB is a bit
dodgy. Is it a valid assumption that all M3ULCB boards have an ES1.0
SoC?
CU
Uli
Dien Pham (2):
arm64: dts: r8a7795: Add cpuidle
From: Khiem Nguyen
Enable cpuidle (core shutdown) support for R-Car M3-W CA57 cores.
Parameters were found after evaluation by gaku.inami...@bp.renesas.com; they
help to keep the performance and reduce the power consumption.
Signed-off-by: Khiem Nguyen
Signed-off-by: Takeshi Kihara
From: Khiem Nguyen
Enable cpuidle (core shutdown) support for R-Car H3 CA57 cores.
Parameters were found after evaluation by gaku.inami...@bp.renesas.com; they
help to keep the performance and reduce the power consumption.
Signed-off-by: Khiem Nguyen
[dien.pham.ry: Apply new cpuidle
From: Dien Pham
Enable cpuidle (core shutdown) support for R-Car M3-W CA53 cores.
Signed-off-by: Dien Pham
Signed-off-by: Takeshi Kihara
Signed-off-by: Ulrich Hecht
---
arch/arm64/boot/dts/renesas/r8a7796.dtsi | 14 ++
1 file changed, 14 insertions(+)
diff --git
From: Takeshi Kihara
The revision of the R8A7796 SoC on the M3ULCB board is ES1.0. This revision
can not use cpuidle for CA53 cores.
Therefore, this patch disables cpuidle support for CA53 cores.
Signed-off-by: Takeshi Kihara
Signed-off-by: Ulrich Hecht
---
From: Dien Pham
Enables cpuidle (core shutdown) support for R-Car H3 CA53 cores.
Signed-off-by: Dien Pham
Signed-off-by: Takeshi Kihara
Signed-off-by: Ulrich Hecht
---
arch/arm64/boot/dts/renesas/r8a7795.dtsi | 14 ++
1 file changed, 14 insertions(+)
diff --git
From: Takeshi Kihara
This patch adds I2C{0,3,5} pins, groups and functions to the R8A7796 SoC.
These pins are physically muxed with other pins. Therefore, setup of
MOD_SEL is needed for exclusive control with other pins.
Signed-off-by: Takeshi Kihara
Signed-off-by: Ulrich Hecht
---
From: Takeshi Kihara
This patch adds I2C{0,3,5} pins, groups and functions to the R8A7795 SoC.
These pins are physically muxed with other pins. Therefore, setup of
MOD_SEL is needed for exclusive control with other pins.
Signed-off-by: Takeshi Kihara
Signed-off-by: Ulrich Hecht
---
From: Takeshi Kihara
This patch adds I2C{0,3,5} pins, groups and functions to
the R8A7795 ES1.x SoC.
These pins are physically muxed with other pins. Therefore, setup of
MOD_SEL is needed for exclusive control with other pins.
Signed-off-by: Takeshi Kihara
Signed-off-by: Ulrich Hecht
---
Hi!
This is an up-port from the BSP. Unfortunately I could not test these
because none of those pins seem to be accessible on Salvator boards (not on
ULCB either, AFAICT), so the best thing I can say is that they don't seem to
break anything.
CU
Uli
Takeshi Kihara (3):
pinctrl: sh-pfc:
I have encountered an interrupt storm during the eMMC chip probing (and
the chip finally didn't get detected). It turned out that U-Boot left
the DMAC interrupts enabled while the Linux driver didn't use those.
The SDHI driver's interrupt handler somehow assumes that, even if a
SDIO
On 08/17/2018 11:51 AM, Simon Horman wrote:
Describe the CSI2 and VIN (and their interconnections) in the R8A77980
device tree.
Signed-off-by: Sergei Shtylyov
---
This patch is against the 'renesas-devel-20180802v2-v4.18-rc7' branch of
Simon Horman's
On Mon, Aug 13, 2018 at 08:41:33AM +0100, Biju Das wrote:
> Enable the Renesas RZ/G2M (R8A774A1) SoC in the ARM64 defconfig.
>
> Signed-off-by: Biju Das
Thanks, applied for v4.20.
On Fri, Aug 17, 2018 at 09:46:34AM +, Biju Das wrote:
> Hi Simon,
>
> Thanks for the feedback.
>
> > Subject: Re: [PATCH] arm64: renesas_defconfig: enable R8A774A1 SoC
> >
> > On Tue, Aug 14, 2018 at 11:04:50AM +0100, Biju Das wrote:
> > > Enable the Renesas RZ/G2M (R8A774A1) SoC in the
On Sun, Aug 12, 2018 at 03:31:43PM +0200, Eugeniu Rosca wrote:
> In harmony with ATF and U-Boot outputs [1] and [2], the new board is
> based on M3-N revision ES1.1 and the amount of memory present on SiP
> is 2GiB, contiguously addressed.
>
> The amount of RAM is mentioned based on the
On Fri, Aug 17, 2018 at 04:53:55PM +0900, Yoshihiro Kaneko wrote:
> From: Hiroyuki Yokoyama
>
> This patch adds the device tree binding of the r8a77990 SoC.
>
> Signed-off-by: Hiroyuki Yokoyama
> Signed-off-by: Yoshihiro Kaneko
Reviewed-by: Simon Horman
On Tue, Aug 14, 2018 at 04:45:10PM -0600, Rob Herring wrote:
> On Mon, 13 Aug 2018 14:52:31 +0100, Biju Das wrote:
> > Document PFC support for the R8A774A1 SoC.
> >
> > Signed-off-by: Biju Das
> > Reviewed-by: Fabrizio Castro
> > ---
> >
Hi Simon,
Thanks for the feedback.
> Subject: Re: [PATCH] arm64: renesas_defconfig: enable R8A774A1 SoC
>
> On Tue, Aug 14, 2018 at 11:04:50AM +0100, Biju Das wrote:
> > Enable the Renesas RZ/G2M (R8A774A1) SoC in the ARM64
> renesas_defconfig.
> >
> > Signed-off-by: Biju Das
> > Reviewed-by:
On Tue, Aug 14, 2018 at 11:04:50AM +0100, Biju Das wrote:
> Enable the Renesas RZ/G2M (R8A774A1) SoC in the ARM64 renesas_defconfig.
>
> Signed-off-by: Biju Das
> Reviewed-by: Fabrizio Castro
Thanks,
I have applied this to the topic/renesas-defconfig branch which is included
in the devel
Hi Simon,
On Fri, Aug 17, 2018 at 11:04:03AM +0200, Simon Horman wrote:
> On Sun, Aug 12, 2018 at 03:31:44PM +0200, Eugeniu Rosca wrote:
> > Document the support for rcar_can on R8A77965 SoC devices.
> > Add R8A77965 to the list of SoCs which require the "assigned-clocks" and
> >
On Fri, Aug 17, 2018 at 11:19:56AM +0200, Simon Horman wrote:
> On Mon, Aug 13, 2018 at 07:01:12AM +, Khiem Nguyen wrote:
> > Hi Simon,
> >
> > >
> > > https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas-backport.git
> > > backport/v4.14.61/snapshot-to-v4.18-rc8+fixes-flattened
>
On Mon, Aug 13, 2018 at 07:01:12AM +, Khiem Nguyen wrote:
> Hi Simon,
>
> > https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas-backport.git
> > backport/v4.14.61/snapshot-to-v4.18-rc8+fixes-flattened
> >
> > for you to fetch changes up to
On Sun, Aug 12, 2018 at 03:31:44PM +0200, Eugeniu Rosca wrote:
> Document the support for rcar_can on R8A77965 SoC devices.
> Add R8A77965 to the list of SoCs which require the "assigned-clocks" and
> "assigned-clock-rates" properties (thanks, Sergei). Rewrap text.
>
> Signed-off-by: Eugeniu
Hi Simon,
Thanks for the feedback.
> -Original Message-
> From: devicetree-ow...@vger.kernel.org ow...@vger.kernel.org> On Behalf Of Simon Horman
> Sent: 17 August 2018 09:45
> To: Biju Das
> Cc: Rob Herring ; Mark Rutland
> ; Magnus Damm ;
> linux-renesas-soc@vger.kernel.org;
On Sat, Aug 11, 2018 at 01:25:10PM +0200, Marek Vasut wrote:
> Add DA9063 OnKey subnode to DA9063 PMIC node on Stout.
>
> Signed-off-by: Marek Vasut
> Cc: Geert Uytterhoeven
> Cc: Kuninori Morimoto
> Cc: Simon Horman
> Cc: Wolfram Sang
> Cc: linux-renesas-soc@vger.kernel.org
> ---
>
On Sat, Aug 11, 2018 at 01:02:57PM +0200, Marek Vasut wrote:
> Add DA9063 RTC and OnKey subnode to DA9063 PMIC node on Silk.
>
> Signed-off-by: Marek Vasut
> Cc: Geert Uytterhoeven
> Cc: Kuninori Morimoto
> Cc: Simon Horman
> Cc: Wolfram Sang
> Cc: linux-renesas-soc@vger.kernel.org
> ---
>
On Fri, Aug 10, 2018 at 06:53:38PM +0300, Sergei Shtylyov wrote:
> On 08/09/2018 04:08 PM, Simon Horman wrote:
>
> >> Describe the CSI2 and VIN (and their interconnections) in the R8A77980
> >> device tree.
> >>
> >> Signed-off-by: Sergei Shtylyov
> >>
> >> ---
> >> This patch is against the
On Fri, Aug 10, 2018 at 09:50:15AM -0600, Rob Herring wrote:
> On Fri, Aug 10, 2018 at 5:13 AM Simon Horman wrote:
> >
> > On Fri, Aug 10, 2018 at 07:37:18AM +, Biju Das wrote:
> > > Hi Rob,
> > >
> > > > Subject: Re: [PATCH v2 2/5] soc: renesas: rcar-sysc: Add r8a774a1
> > > > support
> > >
On Fri, Aug 10, 2018 at 01:47:12PM +, Biju Das wrote:
> Hello Simon,
>
> Thanks for the feedback.
>
> > Subject: Re: [PATCH v3 5/5] ARM: dts: iwg23s-sbc: Add pinctl support for
> > EtherAVB
> >
> > On Tue, Aug 07, 2018 at 08:57:06AM +0100, Biju Das wrote:
> > > Adding pinctrl support for
On Fri, Aug 10, 2018 at 01:30:48PM +0100, Kieran Bingham wrote:
> Hi Simon,
>
> On 10/08/18 13:01, Simon Horman wrote:
> > On Tue, Aug 07, 2018 at 04:59:33PM +0100, Kieran Bingham wrote:
> >> Ensure that the ADV748x device addresses do not conflict, and group them
> >> together (visually in
From: Hiroyuki Yokoyama
This patch adds the device tree binding of the r8a77990 SoC.
Signed-off-by: Hiroyuki Yokoyama
Signed-off-by: Yoshihiro Kaneko
---
This patch is based on the devel branch of Simon Horman's renesas tree.
Documentation/devicetree/bindings/sound/renesas,rsnd.txt | 1 +
This patch adds Audio-DMAC0 device node and Sound device node
for the R8A77990 SoC.
The following patches were squashed into this patch:
* Takeshi Kihara
arm64: dts: r8a77990: Add Audio-DMAC device nodes
arm64: dts: r8a77990: Add Sound device node and SSI support
arm64: dts: r8a77990: Add
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