Hi Simon-san,
> From: Simon Horman, Sent: Wednesday, September 5, 2018 7:33 PM
>
> On Fri, Aug 31, 2018 at 05:20:51PM +0900, Yoshihiro Shimoda wrote:
> > R-Car Gen3 needs to enable/deassert clocks/resets of both usb 2.0
> > host (included phy) and peripheral. Otherwise, other side device
> >
Hi Wolfram,
On 2018-09-16 16:48:07 +0200, Wolfram Sang wrote:
>
> > > > > So, we should at least protect this with TMIO_MMC_MIN_RCAR2, I'd
> > > > > think.
> > > > > Maybe we should even move it to renesas_sdhi_core.c, but I am not too
> > > > > sure about that.
> > >
> > > ... this.
> > >
>
On 09/19/2018 11:02 PM, Sergei Shtylyov wrote:
> Describe TPU in the R8A779{7|8}0 device trees.
>
> Based on the original (and large) patches by Vladimir Barinov.
>
> Signed-off-by: Vladimir Barinov
> Signed-off-by: Sergei Shtylyov
>
> ---
> This patch is against
Describe TPU in the R8A779{7|8}0 device trees.
Based on the original (and large) patches by Vladimir Barinov.
Signed-off-by: Vladimir Barinov
Signed-off-by: Sergei Shtylyov
---
This patch is against the 'renesas-devel-20180919-v4.19-rc4' branch of
Simon Horman's 'renesas.git' repo.
arch
The TPU0 clock wasn't present in the original R8A77970 patch by Daisuke
Matsushita, it was added in a later BSP version...
Based on the original (and large) patch by Vladimir Barinov.
Signed-off-by: Vladimir Barinov
Signed-off-by: Sergei Shtylyov
---
This patch is against the 'clk-renesas'
PLL0 runs at 4.8 GHz, i.e. EXTAL x 100.
Signed-off-by: Geert Uytterhoeven
---
To be queued in clk-renesas-for-v4.20.
drivers/clk/renesas/r8a77990-cpg-mssr.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/renesas/r8a77990-cpg-mssr.c
Hi Laurent,
On Wed, Sep 19, 2018 at 2:18 PM Laurent Pinchart
wrote:
> The R8A77990 (E3) SoC has 7 PWM outputs, add pins, groups and functions
> for all of them.
>
> Signed-off-by: Laurent Pinchart
Thanks for yur patch, but PWm has already been added, cfr.
The R8A77990 (E3) SoC has 7 PWM outputs, add pins, groups and functions
for all of them.
Signed-off-by: Laurent Pinchart
---
drivers/pinctrl/sh-pfc/pfc-r8a77990.c | 180 ++
1 file changed, 180 insertions(+)
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
Hello Simon,
Thank you for your feedback.
> Subject: Re: [PATCH 2/2] ARM: dts: r8a77470: Add APMU node and second CPU core
>
> On Wed, Sep 19, 2018 at 10:25:42AM +0200, Simon Horman wrote:
> > On Mon, Sep 17, 2018 at 10:53:16AM +0200, Geert Uytterhoeven wrote:
> > > Perhaps "ARM: dts: r8a77470:
Hello Simon,
Thank you for your feedback.
> Subject: Re: [PATCH 2/2] ARM: dts: r8a77470: Add APMU node and second CPU core
>
> On Mon, Sep 17, 2018 at 10:53:16AM +0200, Geert Uytterhoeven wrote:
> > Perhaps "ARM: dts: r8a77470: Add SMP support"?
> >
> > On Mon, Sep 17, 2018 at 10:44 AM Fabrizio
Hello Geert,
Thank you for your feedback.
> Subject: Re: [PATCH 2/2] ARM: dts: r8a77470: Add APMU node and second CPU core
>
> Perhaps "ARM: dts: r8a77470: Add SMP support"?
Your proposal is with me, Simon do you want me to send a v2 for this?
Thanks,
Fab
>
> On Mon, Sep 17, 2018 at 10:44 AM
Hello Geert,
> Subject: Re: [PATCH 4/5] pinctrl: sh-pfc: r8a77470: Add SDHI2 pin groups
>
> On Tue, Sep 18, 2018 at 3:48 PM Fabrizio Castro
> wrote:
> > Add SDHI2 pin groups and functions to the R8A77470 SoC.
> >
> > Signed-off-by: Fabrizio Castro
> > Reviewed-by: Biju Das
>
> Reviewed-by:
Hello Geert,
> Subject: Re: [PATCH 3/5] pinctrl: sh-pfc: r8a77470: Add QSPI0 pin groups
>
> On Tue, Sep 18, 2018 at 3:48 PM Fabrizio Castro
> wrote:
> > Add QSPI0 pin groups and function to the R8A77470 SoC.
> >
> > Signed-off-by: Fabrizio Castro
> > Reviewed-by: Biju Das
>
> Reviewed-by:
Hello Geert,
Thank you for your feedback.
> Subject: Re: [PATCH 2/5] pinctrl: sh-pfc: r8a77470: Add DU0 pin groups
>
> Hi Fabrizio,
>
> On Tue, Sep 18, 2018 at 3:48 PM Fabrizio Castro
> wrote:
> > Add DU0 pin groups and function to the R8A77470 SoC.
>
> Thanks for your patch!
>
> Same question:
Hello Geert,
Thank you for your feedback.
> Subject: Re: [PATCH 1/5] pinctrl: sh-pfc: r8a77470: Add I2C4 pin groups
>
> Hi Fabrizio,
>
> On Tue, Sep 18, 2018 at 3:48 PM Fabrizio Castro
> wrote:
> > Add I2C4 pin groups and function to the R8A77470 SoC.
>
> Thanks for your patch!
>
> Any specific
On Wed, Sep 19, 2018 at 11:21:42AM +0200, Marek Vasut wrote:
> On 09/19/2018 11:13 AM, Simon Horman wrote:
> > On Tue, Sep 18, 2018 at 02:52:53PM +0200, Geert Uytterhoeven wrote:
> >> On Tue, Sep 18, 2018 at 2:23 PM Marek Vasut wrote:
> >>> Rather than hard-coding the quirk topology, which
Hi Marek,
On Wed, Sep 19, 2018 at 11:36 AM Marek Vasut wrote:
> On 09/19/2018 11:30 AM, Geert Uytterhoeven wrote:
> > On Wed, Sep 19, 2018 at 11:28 AM Geert Uytterhoeven
> > wrote:
> >> On Wed, Sep 19, 2018 at 11:22 AM Marek Vasut wrote:
> >>> On 09/19/2018 11:13 AM, Simon Horman wrote:
>
On Mon, Sep 17, 2018 at 04:18:16PM +0100, Biju Das wrote:
> Renesas RZ/G SoC also have the R-Car gen2/3 compatible DMA controllers.
> Document RZ/G1N (also known as R8A7744) SoC bindings.
>
> Signed-off-by: Biju Das
> Reviewed-by: Fabrizio Castro
Reviewed-by: Simon Horman
> ---
>
On 09/19/2018 11:30 AM, Geert Uytterhoeven wrote:
> Hi Marek,
>
> On Wed, Sep 19, 2018 at 11:28 AM Geert Uytterhoeven
> wrote:
>> On Wed, Sep 19, 2018 at 11:22 AM Marek Vasut wrote:
>>> On 09/19/2018 11:13 AM, Simon Horman wrote:
Marek, these days checkpatch complains if the author of the
Hi Marek,
On Wed, Sep 19, 2018 at 11:22 AM Marek Vasut wrote:
> On 09/19/2018 11:13 AM, Simon Horman wrote:
> > Marek, these days checkpatch complains if the author of the patch does not
> > have a signed offline, and the inconsistency between your
> > from and Sign-off the email address trips
On Wed, Sep 19, 2018 at 11:13:14AM +0200, Geert Uytterhoeven wrote:
> Hi Simon,
>
> On Wed, Sep 19, 2018 at 11:08 AM Simon Horman wrote:
> > On Tue, Sep 18, 2018 at 12:07:50PM +0200, Geert Uytterhoeven wrote:
> > > [*] The only regression I'm aware of is a regression in 4.14-stable,
> > > which
On Wed, Sep 19, 2018 at 10:43:53AM +0200, Geert Uytterhoeven wrote:
> On Wed, Sep 19, 2018 at 10:31 AM Simon Horman wrote:
> > On Mon, Sep 17, 2018 at 01:20:57PM +0200, Geert Uytterhoeven wrote:
> > > On Mon, Sep 17, 2018 at 10:39 AM Magnus Damm
> > > wrote:
> > > > From: Magnus Damm
> > > >
>
Hi Phil,
On Wed, Sep 19, 2018 at 11:18 AM Phil Edworthy
wrote:
> On 19 September 2018 10:15 Simon Horman wrote:
> > On Mon, Sep 17, 2018 at 05:36:09PM +0100, Phil Edworthy wrote:
> > > This provides a pinctrl driver for the Renesas R9A06G032 SoC
> > >
> > > Based on a patch originally written by
On Wed, Sep 19, 2018 at 10:25:42AM +0200, Simon Horman wrote:
> On Mon, Sep 17, 2018 at 10:53:16AM +0200, Geert Uytterhoeven wrote:
> > Perhaps "ARM: dts: r8a77470: Add SMP support"?
> >
> > On Mon, Sep 17, 2018 at 10:44 AM Fabrizio Castro
> > wrote:
> > > Add DT node for the Advanced Power
On Tue, Sep 18, 2018 at 3:48 PM Fabrizio Castro
wrote:
> Add QSPI0 pin groups and function to the R8A77470 SoC.
>
> Signed-off-by: Fabrizio Castro
> Reviewed-by: Biju Das
Reviewed-by: Geert Uytterhoeven
But I missed QSPI1...
Gr{oetje,eeting}s,
Geert
--
Geert
On 09/19/2018 11:13 AM, Simon Horman wrote:
> On Tue, Sep 18, 2018 at 02:52:53PM +0200, Geert Uytterhoeven wrote:
>> On Tue, Sep 18, 2018 at 2:23 PM Marek Vasut wrote:
>>> Rather than hard-coding the quirk topology, which stopped scaling,
>>> parse the information from DT. The code looks for all
On Wed, Sep 19, 2018 at 11:19:42AM +0200, Simon Horman wrote:
> On Wed, Sep 19, 2018 at 09:48:53AM +0200, Geert Uytterhoeven wrote:
> > On Fri, Sep 14, 2018 at 10:17 PM Sergei Shtylyov
> > wrote:
> > > On 09/11/2018 09:26 PM, Sergei Shtylyov wrote:
> > >
> > > >>> Document the R-Car V3{M|H}
On Tue, Sep 18, 2018 at 3:48 PM Fabrizio Castro
wrote:
> Add USB[01] pin groups and functions to the R8A77470 SoC.
>
> Signed-off-by: Fabrizio Castro
> Reviewed-by: Biju Das
Reviewed-by: Geert Uytterhoeven
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's
On Tue, Sep 18, 2018 at 3:48 PM Fabrizio Castro
wrote:
> Add SDHI2 pin groups and functions to the R8A77470 SoC.
>
> Signed-off-by: Fabrizio Castro
> Reviewed-by: Biju Das
Reviewed-by: Geert Uytterhoeven
But there are more SDHI channels?
Gr{oetje,eeting}s,
Geert
--
On Wed, Sep 19, 2018 at 09:47:02AM +0200, Geert Uytterhoeven wrote:
> On Fri, Sep 7, 2018 at 8:58 PM Sergei Shtylyov
> wrote:
> > Describe CMTs in the R8A779{7|8}0 device trees.
> >
> > Based on the original (and large) patches by Vladimir Barinov.
> >
> > Signed-off-by: Vladimir Barinov
> >
On Wed, Sep 19, 2018 at 09:48:53AM +0200, Geert Uytterhoeven wrote:
> On Fri, Sep 14, 2018 at 10:17 PM Sergei Shtylyov
> wrote:
> > On 09/11/2018 09:26 PM, Sergei Shtylyov wrote:
> >
> > >>> Document the R-Car V3{M|H} (R8A779{7|8}0) SoC in the Renesas TMU
> > >>> bindings;
> > >>> the TMU
On Wed, Sep 19, 2018 at 07:24:05AM +, Kuninori Morimoto wrote:
>
> From: Kuninori Morimoto
>
> It can't boot without bootargs settings on Uboot on ulcb board.
> This patch adds missing default bootargs.
> ulcb BSP can overwrite it by own UBoot settings.
>
> Signed-off-by: Kuninori Morimoto
Hi Simon,
On Wed, Sep 19, 2018 at 11:08 AM Simon Horman wrote:
> On Tue, Sep 18, 2018 at 12:07:50PM +0200, Geert Uytterhoeven wrote:
> > [*] The only regression I'm aware of is a regression in 4.14-stable, which
> > can
> > be fixed by "tick/nohz: Prevent bogus softirq pending warning".
> >
On Tue, Sep 18, 2018 at 02:52:53PM +0200, Geert Uytterhoeven wrote:
> On Tue, Sep 18, 2018 at 2:23 PM Marek Vasut wrote:
> > Rather than hard-coding the quirk topology, which stopped scaling,
> > parse the information from DT. The code looks for all compatible
> > PMICs -- da9063 and da9210 --
On Tue, Sep 18, 2018 at 12:07:50PM +0200, Geert Uytterhoeven wrote:
> Hi Simon,
>
> On Tue, Sep 18, 2018 at 10:51 AM Simon Horman wrote:
> > This is intended as a submission to LTSI-4.14. It is the backport
> > of a fixes for safe DMA buffer handling for the SH-Mobile I2C driver
> > and I2C
On Tue, Sep 18, 2018 at 11:24:49AM +0200, Geert Uytterhoeven wrote:
> On Tue, Sep 18, 2018 at 11:14 AM Wolfram Sang
> wrote:
> > The PMIC and EEPROM can operate at 400kHz, so use this speed.
> >
> > Signed-off-by: Wolfram Sang
>
> Reviewed-by: Geert Uytterhoeven
Thanks, applied for v4.20.
Hi Fabrizio,
On Tue, Sep 18, 2018 at 3:48 PM Fabrizio Castro
wrote:
> Add DU0 pin groups and function to the R8A77470 SoC.
Thanks for your patch!
Same question: no need for DU1?
> Signed-off-by: Fabrizio Castro
> Reviewed-by: Biju Das
Reviewed-by: Geert Uytterhoeven
Gr{oetje,eeting}s,
Hi Fabrizio,
On Tue, Sep 18, 2018 at 3:48 PM Fabrizio Castro
wrote:
> Add I2C4 pin groups and function to the R8A77470 SoC.
Thanks for your patch!
Any specific reason you added I2C4 only, and not the other I2C instances?
Usually we add all of them in one run.
> Signed-off-by: Fabrizio Castro
On Wed, Sep 12, 2018 at 3:31 PM Fabrizio Castro
wrote:
> Renesas RZ/G2E (a.k.a. r8a774c0) is pin compatible with R-Car
> E3 (a.k.a. r8a77990), however it doesn't have several automotive
> specific peripherals. Add a r8a77990 specific pin groups/functions
> along with common pin groups/functions
On Wed, Sep 19, 2018 at 10:31 AM Simon Horman wrote:
> On Mon, Sep 17, 2018 at 01:20:57PM +0200, Geert Uytterhoeven wrote:
> > On Mon, Sep 17, 2018 at 10:39 AM Magnus Damm wrote:
> > > From: Magnus Damm
> > >
> > > Update the description of the AG5 entry to follow same style as other
> > >
On Mon, Sep 17, 2018 at 04:06:30PM +0100, Biju Das wrote:
> Enable low-level debugging support for RZ/G1N (R8A7744). RZ/G1N uses
> SCIF0 for the debug console.
>
> Signed-off-by: Biju Das
> Reviewed-by: Fabrizio Castro
Thanks Biju,
applied to the renesas tree for v4.20.
On Mon, Sep 17, 2018 at 04:08:47PM +0100, Biju Das wrote:
> Enable recently added r8a7744 (RZ/G1N) SoC.
>
> Signed-off-by: Biju Das
> Reviewed-by: Fabrizio Castro
Thanks, applied for v4.20.
On Mon, Sep 17, 2018 at 04:06:29PM +0100, Biju Das wrote:
> Enable recently added r8a7744 (RZ/G1N) SoC.
>
> Signed-off-by: Biju Das
> Reviewed-by: Fabrizio Castro
Thanks, applied to the renesas tree for v4.20.
On Mon, Sep 17, 2018 at 01:21:42PM +0200, Geert Uytterhoeven wrote:
> On Mon, Sep 17, 2018 at 10:39 AM Magnus Damm wrote:
> > From: Magnus Damm
> >
> > Include R-Car Gen1 product names for Bock-W and Marzen.
> >
> > The product names are taken from:
> >
On Mon, Sep 17, 2018 at 01:22:22PM +0200, Geert Uytterhoeven wrote:
> On Mon, Sep 17, 2018 at 10:39 AM Magnus Damm wrote:
> > From: Magnus Damm
> >
> > Improve the user friendliness of the DTS code base by including the
> > R-Car product name in each R-Car Gen2 DTSI file.
> >
> > The product
On Mon, Sep 17, 2018 at 10:53:16AM +0200, Geert Uytterhoeven wrote:
> Perhaps "ARM: dts: r8a77470: Add SMP support"?
>
> On Mon, Sep 17, 2018 at 10:44 AM Fabrizio Castro
> wrote:
> > Add DT node for the Advanced Power Management Unit (APMU), add the
> > second CPU core, and use "renesas,apmu" as
On Mon, Sep 17, 2018 at 10:52:19AM +0200, Geert Uytterhoeven wrote:
> On Mon, Sep 17, 2018 at 10:44 AM Fabrizio Castro
> wrote:
> > Document APMU and SMP enable method for RZ/G1C (also known as
> > r8a77470) SoC.
> >
> > Signed-off-by: Fabrizio Castro
> > Reviewed-by: Biju Das
>
> Reviewed-by:
On Mon, Sep 17, 2018 at 05:53:05PM +0900, Magnus Damm wrote:
> From: Magnus Damm
>
> For R-Car V3H hook up SYS-DMAC1 and SYS-DMAC2 to IPMMU-DS1 to match
> information in the R-Car Gen3 Rev.1.00 (April 2018) datasheet.
>
> Signed-off-by: Magnus Damm
Thanks Magnus,
applied for v4.20.
On Mon, Sep 17, 2018 at 10:39:08AM +0200, Simon Horman wrote:
> On Mon, Sep 17, 2018 at 05:19:49PM +0900, Magnus Damm wrote:
> > From: Magnus Damm
> >
> > For R-Car E3 hook up SYS-DMAC0, SYS-DMAC1 and SYS-DMAC2 to
> > IPMMU-DS0 and IPMMU-DS1 in same way as for R-Car H3.
> > This follows the
On Fri, Sep 14, 2018 at 10:17 PM Sergei Shtylyov
wrote:
> On 09/11/2018 09:26 PM, Sergei Shtylyov wrote:
>
> >>> Document the R-Car V3{M|H} (R8A779{7|8}0) SoC in the Renesas TMU bindings;
> >>> the TMU hardware in those is the Renesas standard 3-channel timer unit.
> >>>
> >>> Signed-off-by:
On Fri, Sep 7, 2018 at 8:58 PM Sergei Shtylyov
wrote:
> Describe CMTs in the R8A779{7|8}0 device trees.
>
> Based on the original (and large) patches by Vladimir Barinov.
>
> Signed-off-by: Vladimir Barinov
> Signed-off-by: Sergei Shtylyov
Reviewed-by: Geert Uytterhoeven
Gr{oetje,eeting}s,
From: Kuninori Morimoto
It can't boot without bootargs settings on Uboot on ulcb board.
This patch adds missing default bootargs.
ulcb BSP can overwrite it by own UBoot settings.
Signed-off-by: Kuninori Morimoto
---
arch/arm64/boot/dts/renesas/ulcb.dtsi | 1 +
1 file changed, 1 insertion(+)
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