The driver fixed the TXA CSI-2 transmitter in 4-lane mode while it could
operate using 1-, 2- and 4-lanes. Update the driver to support all
available modes.
The driver makes use of large tables of static register/value writes
when powering up/down the TXA and TXB transmitters which include the
wri
Extend the MIPI CSI-2 power up sequence to match the power up sequence
in the hardware manual chapter "9.5.1 Power Up Sequence". This change
allows the power up functions to be reused when initializing the
hardware reducing code duplicating as well aligning with the
documentation.
Signed-off-by: N
The CSI-2 transmitters can use a different number of lanes to transmit
data. Make the data-lanes mandatory for the endpoints that describe the
transmitters as no good default can be set to fallback on.
Signed-off-by: Niklas Söderlund
---
* Changes since v3
- Add paragraph to describe the accepte
The adv748x CSI-2 transmitters TXA and TXB can use different number of
lanes to transmit data. In order to be able to configure the device
correctly this information need to be parsed from device tree and stored
in each TX private data structure.
TXA supports 1, 2 and 4 lanes while TXB supports 1
Hi,
This series allows the TXA CSI-2 transmitter of the adv748x to function
in 1-, 2- and 4- lane mode. Currently the driver fixes the hardware in
4-lane mode. The driver looks at the standard DT property 'data-lanes'
to determine which mode it should operate in.
Patch 1/4 lists the 'data-lanes'
Hi Geert,
On 2018-11-28 19:02:33 +0100, Niklas Söderlund wrote:
> Hi Geert,
>
> Thanks for your feedback.
>
> On 2018-11-05 16:45:39 +0100, Geert Uytterhoeven wrote:
> > Hi Niklas,
> >
> > On Mon, Nov 5, 2018 at 4:07 PM Niklas Söderlund
> > wrote:
> > > On 2018-11-05 11:43:24 +0100, Geert Uytt
Document the known use cases of the different clock settings. This is
useful as different SoC and ES versions uses different settings to do
the same thing as there are more then one combination to achieve the
same SDn clock speed.
Signed-off-by: Niklas Söderlund
Reviewed-by: Wolfram Sang
---
dr
On H3 (ES1.x, ES2.0) and M3-W (ES1.0, ES1.1) the clock setting for HS400
needs a quirk to function properly. The reason for the quirk is that
there are two settings which produces same divider value for the SDn
clock. On the effected boards the one currently selected results in
HS400 not working.
Hi Geert,
This series aims to solve the clock quirk needed to enabled HS400 on
SoCs needing special clock handeling. It uses the same method as v1 of
this series and which was discussed during the SDHI hackathon. However
patch 2/2 have been completely rewritten to take your comments from v1
in
The driver tries to figure out which state a SD clock is in when the
clock is register instead of setting a known state. This can be
problematic for two reasons.
1. If the clock driver can't figure out the state of the clock
registration of the clock fails and setting of a known state by a
c
Hi Wolfram,
On 2018-11-28 23:06:37 +0100, Niklas Söderlund wrote:
> Hi Wolfram,
>
> On 2018-11-28 22:56:20 +0100, Wolfram Sang wrote:
> > Hi Niklas,
> >
> > thanks for the updates! Do you happen to have a branch ready for
> > testing?
>
> I will push a new branch once I'm done updating the cloc
Hi Wolfram,
On 2018-11-28 22:56:20 +0100, Wolfram Sang wrote:
> Hi Niklas,
>
> thanks for the updates! Do you happen to have a branch ready for
> testing?
I will push a new branch once I'm done updating the clock patch so all
changes can be tested in one go. Will let you know once that is
avai
Hi Niklas,
thanks for the updates! Do you happen to have a branch ready for
testing?
Thanks,
Wolfram
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On Wed, Nov 28, 2018 at 7:37 PM Stephen Boyd wrote:
> This is only used in this file, so mark it static to silence a sparse
> warning.
>
> Cc: Geert Uytterhoeven
> Signed-off-by: Stephen Boyd
Reviewed-by: Geert Uytterhoeven
Gr{oetje,eeting}s,
Geert
--
Geert Uytterho
This is only used in this file, so mark it static to silence a sparse
warning.
Cc: Geert Uytterhoeven
Signed-off-by: Stephen Boyd
---
I've applied this to clk-renesas branch already, just not pushed out
yet.
drivers/clk/renesas/r7s9210-cpg-mssr.c | 2 +-
1 file changed, 1 insertion(+), 1 dele
Quoting Geert Uytterhoeven (2018-11-23 00:56:35)
> Hi Mike, Stephen,
>
> The following changes since commit 651022382c7f8da46cb4872a545ee1da6d097d2a:
>
> Linux 4.20-rc1 (2018-11-04 15:37:52 -0800)
>
> are available in the Git repository at:
>
> git://git.kernel.org/pub/scm/linux/ker
Hi Geert,
Thanks for your feedback.
On 2018-11-05 16:45:39 +0100, Geert Uytterhoeven wrote:
> Hi Niklas,
>
> On Mon, Nov 5, 2018 at 4:07 PM Niklas Söderlund
> wrote:
> > On 2018-11-05 11:43:24 +0100, Geert Uytterhoeven wrote:
> > > On Thu, Nov 1, 2018 at 12:26 AM Niklas Söderlund
> > > wrote:
Hi Biju,
On Wednesday, 28 November 2018 15:20:58 EET Biju Das wrote:
> Hi all,
>
> On the past, I have tested vsp source on rcar gen2 koelsch board, using the
> patches series below(Apart from the below patch series, I have enabled
> "CONFIG_DRM_RCAR_VSP=y")
> https://git.linuxtv.org/pinchartl/
Add VSP support to SoC DT.
Signed-off-by: Biju Das
---
arch/arm/boot/dts/r8a7744.dtsi | 27 +++
1 file changed, 27 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
index 3b8aa3b..0937349 100644
--- a/arch/arm/boot/dts/r8a7744.dts
Add TPU support to SoC DT.
Signed-off-by: Biju Das
---
arch/arm/boot/dts/r8a7744.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
index 43da6a0..40de227 100644
--- a/arch/arm/boot/dts/r8a7744.dtsi
+++ b/arch/arm/
Add the definitions for pwm[0123456] to the SoC dtsi.
Signed-off-by: Biju Das
---
arch/arm/boot/dts/r8a7744.dtsi | 70 ++
1 file changed, 70 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
index 152431c..43da6a0
Add the six IPMMU instances found in the r8a7744 to DT with a disabled
status.
Signed-off-by: Biju Das
---
arch/arm/boot/dts/r8a7744.dtsi | 58 ++
1 file changed, 58 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dts
Add VIN[012] support to SoC dt.
Signed-off-by: Biju Das
---
arch/arm/boot/dts/r8a7744.dtsi | 33 +
1 file changed, 33 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
index 2eae905..3b8aa3b 100644
--- a/arch/arm/boot/dts/
This patch series aims to add support for some more interfaces
to RZ/G1N SoC (IPMMU, VSP, VIN, PWM and TPU).
This patch series tested against renesas-dev.
it depends on the the below patch series.
https://patchwork.kernel.org/project/linux-renesas-soc/list/?series=48065
Biju Das (5):
ARM: dts:
It was though all ES revisions of H3 and M3-W SoCs required the
TMIO_MMC_HAVE_4TAP_HS400 flag. Recent datasheet updates tells us this is
not true, only early ES revisions of the SoC do.
Since quirk matching based on ES revisions is now used to handle the
flag it's possible to align all Gen3 compat
The Renesas BSP confirms that H3 ES1.x and M3-W ES1.[012] do not
properly support HS400. Add a quirk to indicate this and disable HS400
in the MMC capabilities if the quirk is set.
Signed-off-by: Niklas Söderlund
Tested-by: Wolfram Sang
Reviewed-by: Wolfram Sang
Reviewed-by: Simon Horman
---
Latest datasheet makes it clear that not all ES revisions of the H3 and
M3-W have the 4-tap HS400 mode quirk, currently the quirk is set
unconditionally for these two SoCs. Prepare to handle the quirk based on
SoC revision instead of compatibility value by using soc_device_match()
and set the TMIO_
Hi,
Recent datasheet updates have made it clear that some quirks are not SoC
specific but SoC + ES version specific. Currently the quirks are
selected using compatibility values but whit this new information that
is not enough.
Patch 1/3 adds support to select quirks based on SoC + ES revision us
> -Original Message-
> From: linux-renesas-soc-ow...@vger.kernel.org ow...@vger.kernel.org> On Behalf Of Simon Horman
> Sent: 28 November 2018 13:24
> To: Biju Das
> Cc: Sergei Shtylyov ; Rob Herring
> ; Mark Rutland ; Magnus
> Damm ; linux-renesas-soc@vger.kernel.org;
> devicet...@vger
On Tue, Nov 27, 2018 at 02:22:12PM +, Biju Das wrote:
> Hello Sergei,
>
> Thanks for the feedback.
>
> > -Original Message-
> > From: Sergei Shtylyov
> > Sent: 27 November 2018 14:17
> > To: Biju Das ; Rob Herring
> > ; Mark Rutland
> > Cc: Simon Horman ; Magnus Damm
> > ; linux-ren
On Mon, Nov 26, 2018 at 06:02:46PM +0100, Niklas Söderlund wrote:
> SD / MMC did not operate properly when suspend transition failed.
> Because the SCC was not reset at resume, issue of the command failed.
> Call the host specific reset function and reset the hardware in order to
> add reset of SCC
Hi all,
On the past, I have tested vsp source on rcar gen2 koelsch board, using the
patches series below(Apart from the below patch series, I have enabled
"CONFIG_DRM_RCAR_VSP=y")
https://git.linuxtv.org/pinchartl/media.git/log/?h=drm/du/panels
1) [HACK] ARM: shmobile: r8a7791: Link the VSP1
From: Biju Das
This patch enables cmt0 support on the iWave iwg23s sbc.
Signed-off-by: Biju Das
Reviewed-by: Fabrizio Castro
Signed-off-by: Simon Horman
---
arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/r8a77470-iwg23s-sbc
From: Biju Das
Add CMT[01] support to r8a77470 SoC DT.
Signed-off-by: Biju Das
Reviewed-by: Fabrizio Castro
Signed-off-by: Simon Horman
---
arch/arm/boot/dts/r8a77470.dtsi | 32
1 file changed, 32 insertions(+)
diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/
From: Fabrizio Castro
Add QSPI[01] support to the RZ/G1C SoC specific device tree.
Signed-off-by: Fabrizio Castro
Signed-off-by: Simon Horman
---
arch/arm/boot/dts/r8a77470.dtsi | 32
1 file changed, 32 insertions(+)
diff --git a/arch/arm/boot/dts/r8a77470.dt
From: Phil Edworthy
Harmless mistake, but it's incorrect. The DT spec provides recommendations
for the node names:
"The name of a node should be somewhat generic, reflecting the function
of the device and not its precise programming model. If appropriate, the
name should be one of the following c
From: Biju Das
Adding pinctrl support for EtherAVB interface.
Signed-off-by: Biju Das
Reviewed-by: Fabrizio Castro
Reviewed-by: Geert Uytterhoeven
Signed-off-by: Fabrizio Castro
Signed-off-by: Simon Horman
---
arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts | 8
1 file changed, 8 insert
From: Biju Das
This patch enables watchdog support on the iWave iwg23s sbc.
Signed-off-by: Biju Das
Reviewed-by: Fabrizio Castro
Signed-off-by: Simon Horman
---
arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/r8a77470-iwg23
From: Biju Das
This patch adds USB DMAC nodes.
Signed-off-by: Biju Das
Reviewed-by: Fabrizio Castro
Signed-off-by: Simon Horman
---
arch/arm/boot/dts/r8a77470.dtsi | 56 +
1 file changed, 56 insertions(+)
diff --git a/arch/arm/boot/dts/r8a77470.dtsi b
From: Laurent Pinchart
The LVDS0 encoder on Koelsh and Porter, and the LVDS1 encoder on Lager,
are enabled in DT but have no device connected to their output. This
result in spurious messages being printed to the kernel log such as
rcar-du feb0.display: no connector for encoder /soc/lvds@feb
From: Magnus Damm
Update the R-Mobile A1 (r8a7740), Emma Mobile EV2 (emev2) and
SH-Mobile AG5 (sh72a0) DTSI to include product name.
Signed-off-by: Magnus Damm
[simon: squashed similar patches]
Signed-off-by: Simon Horman
---
arch/arm/boot/dts/emev2.dtsi | 2 +-
arch/arm/boot/dts/r8a7740.dt
From: Fabrizio Castro
This commit adds QSPI flash support to the iwg23s board specific
device tree.
Signed-off-by: Fabrizio Castro
Signed-off-by: Simon Horman
---
arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts | 26 ++
1 file changed, 26 insertions(+)
diff --git a/arch/arm
From: Biju Das
This patch adds watchdog support to the r8a77470 SoC dtsi.
Signed-off-by: Biju Das
Reviewed-by: Fabrizio Castro
[simon: moved node to preserve sort order]
Signed-off-by: Simon Horman
---
arch/arm/boot/dts/r8a77470.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff --
From: Fabrizio Castro
Add uSD card and eMMC support to the iwg23s single board
computer powered by the RZ/G1C SoC (a.k.a. r8a77470).
Signed-off-by: Fabrizio Castro
Reviewed-by: Biju Das
Signed-off-by: Simon Horman
---
arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts | 76 +++
From: Phil Edworthy
This provides a pinctrl driver for the Renesas R9A06G032 SoC
Based on a patch originally written by Michel Pollet at Renesas.
Signed-off-by: Phil Edworthy
Reviewed-by: Geert Uytterhoeven
Signed-off-by: Simon Horman
---
arch/arm/boot/dts/r9a06g032.dtsi | 8
1 fil
From: Fabrizio Castro
Add device tree nodes for the I2C[0123] controllers. Also, add
the aliases node.
Signed-off-by: Fabrizio Castro
Reviewed-by: Biju Das
Reviewed-by: Geert Uytterhoeven
Signed-off-by: Simon Horman
---
arch/arm/boot/dts/r8a77470.dtsi | 64 ++
From: Fabrizio Castro
RZ/G1C comes with two different types of IP for the SDHI
interfaces, SDHI0 and SDHI2 share the same IP type, and
such an IP is also compatible with the one found in R-Car
Gen2. SDHI1 IP on the other hand is compatible with R-Car
Gen3 with internal DMA.
This patch completes t
From: Fabrizio Castro
Althought interface SDHI1 found on the RZ/G1C SoC (a.k.a.
r8a77470) is compatible with the R-Car Gen3 ones, its OF
compatibility is restricted to the SoC specific compatible
string to avoid confusion, as from a more generic perspective
the RZ/G1C is sharing the most similari
Hi Olof, Hi Kevin, Hi Arnd,
Please consider these Renesas ARM based SoC DT updates for v4.21.
I am sending out this pull-request at this time as there are a number
of patches queued up in my arm (32) DT branch and I hope that this
will ease the burden later on in the development cycle. I expect t
Hi Sakari,
Thank you for your review,
On 20/11/2018 08:34, Sakari Ailus wrote:
> Hi Kieran,
>
> On Fri, Nov 02, 2018 at 03:47:23PM +, Kieran Bingham wrote:
>> From: Kieran Bingham
>>
>> The RDACM20 is a GMSL camera supporting 1280x800 resolution images
>> developed by IMI based on an Omnivi
On Mon, Nov 26, 2018 at 01:54:03PM +0100, Simon Horman wrote:
> From: Phil Edworthy
>
> This provides a pinctrl driver for the Renesas R9A06G032 SoC
>
> Based on a patch originally written by Michel Pollet at Renesas.
>
> Signed-off-by: Phil Edworthy
> Geert Uytterhoeven
The tag above is gar
On Tue, Nov 13, 2018 at 2:35 PM Geert Uytterhoeven
wrote:
> In some SoCs multiple hardware blocks may share a reset control.
> The reset control API for shared resets will only assert such a reset
> when the drivers for all hardware blocks agree.
> The exclusive reset control API still allows to a
Some R-Car Gen3 SoCs has hardware restrictions on the IPMMU. So,
to check whether this R-Car Gen3 SoC can use the IPMMU correctly,
this patch modifies the ipmmu_slave_whitelist().
Signed-off-by: Yoshihiro Shimoda
Reviewed-by: Geert Uytterhoeven
---
drivers/iommu/ipmmu-vmsa.c | 34 ++
This patch set is based on iommu.git / latest next branch
(commit id = f262283c224537962cba0f41b8823e3be9f7b0ff)
I talked with Geert-san about this topic on below:
https://patchwork.kernel.org/patch/10651375/
Also Simon-san suggests we should keep the whitelist.
So, not to change behavior of R-C
To avoid adding copy and pasted strcmp codes in the future,
this patch adds an array "rcar_gen3_slave_whitelist" to check
whether the device can work with the IPMMU or not.
Signed-off-by: Yoshihiro Shimoda
Reviewed-by: Geert Uytterhoeven
---
drivers/iommu/ipmmu-vmsa.c | 13 -
1 file
Hi Geert-san,
> From: Geert Uytterhoeven, Sent: Wednesday, November 28, 2018 5:48 PM
>
> Hi Shimoda-san,
>
> On Wed, Nov 28, 2018 at 7:10 AM Yoshihiro Shimoda
> wrote:
> > To avoid adding copy and pasted strcmp codes in the future,
> > this patch adds an array "rcar_gen3_slave_whitelist" to che
Hi Geert-san,
> From: Geert Uytterhoeven, Sent: Wednesday, November 28, 2018 5:47 PM
>
> Hi Shimoda-san,
>
> On Wed, Nov 28, 2018 at 7:10 AM Yoshihiro Shimoda
> wrote:
> > Some R-Car Gen3 SoCs has hardware restrictions on the IPMMU. So,
> > to check whether this R-Car Gen3 SoC can use the IPMMU
This patch adds toggling phy reset if PHY is not attached. Otherwise,
some boards (e.g. R-Car H3 Salvator-XS) cannot link up correctly if
we do the following method:
1) Kernel boots by using initramfs.
--> No open the nic, so phy_device_register() and phy_probe()
deasserts the reset.
2) Ke
This patch fixes an issue that mdio_bus_phy_resume() doesn't call
phy_resume() if the PHY is not attached.
Fixes: 803dd9c77ac3 ("net: phy: avoid suspending twice a PHY")
Signed-off-by: Yoshihiro Shimoda
---
drivers/net/phy/phy_device.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletio
This patch set is for R-Car Gen3 Salvator-XS boards. If we do
the following method, the phy cannot link up correctly.
1) Kernel boots by using initramfs.
--> No open the nic, so phy_device_register() and phy_probe()
deasserts the reset.
2) Kernel enters the suspend.
--> So, keep the reset
Hi Shimoda-san,
On Wed, Nov 28, 2018 at 7:10 AM Yoshihiro Shimoda
wrote:
> To avoid adding copy and pasted strcmp codes in the future,
> this patch adds an array "rcar_gen3_slave_whitelist" to check
> whether the device can work with the IPMMU or not.
>
> Signed-off-by: Yoshihiro Shimoda
Review
Hi Shimoda-san,
On Wed, Nov 28, 2018 at 7:10 AM Yoshihiro Shimoda
wrote:
> Some R-Car Gen3 SoCs has hardware restrictions on the IPMMU. So,
> to check whether this R-Car Gen3 SoC can use the IPMMU correctly,
> this patch modifies the ipmmu_slave_whitelist().
>
> Signed-off-by: Yoshihiro Shimoda
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