DMA transfer to/from SRC
DMA DMApp
[MEM] -> [SRC] -> [SSIU] -> [SSI]
DMA DMApp
[MEM] <- [SRC] <- [SSIU] <- [SSI]
Current sound driver is supporting SSI/SRC random connection.
So, this patch is trying
SSI3 -> SRC3
SSI4 <- SRC4
Signed-off-by: Biju Das
Enable sound PIO support on carrier board.
Signed-off-by: Biju Das <biju@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.cas...@bp.renesas.com>
---
arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts | 46 +
1 file changed, 46 insertions(+)
diff --gi
This patch enables SGTL5000 audio codec on the carrier board.
Signed-off-by: Biju Das <biju@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.cas...@bp.renesas.com>
---
arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts | 28
1 file changed, 28 inserti
Describe the external audio clocks required by the sound driver.
Boards that provide audio clocks need to override the clock frequencies.
Signed-off-by: Biju Das <biju@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.cas...@bp.renesas.com>
---
arch/arm/boot/dts/r8a77
This series aims to add sound support for iWave RZ/G1E board.
Biju Das (9):
ARM: dts: r8a7745: Add audio clocks
ARM: dts: r8a7745: Add audio DMAC support
ARM: dts: r8a7745: Add sound support
ARM: dts: iwg22d-sodimm: Enable SGTL5000 audio codec
ARM: dts: iwg22d-sodimm: Sound PIO support
Instantiate the audio DMA controller on the r8a7745 device tree.
Signed-off-by: Biju Das <biju@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.cas...@bp.renesas.com>
---
arch/arm/boot/dts/r8a7745.dtsi | 31 +++
1 file changed, 31 insertions(+)
Add the missing clock to CA7 CPU1 node.
Signed-off-by: Biju Das <biju@bp.renesas.com>
---
arch/arm/boot/dts/r8a7745.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi
index 835a282..ae918e9 100644
--- a/arch/arm/bo
Add RZ/G2M (R8A774A1) Clock Pulse Generator / Module Standby and Software
Reset support.
Based on the Table 8.2b of "RZ/G Series, 2nd Generation User's Manual:
Hardware ((Rev. 0.61, June 12, 2018)".
Signed-off-by: Biju Das
Reviewed-by: Fabrizio Castro
---
V1-->V2
* Added OS
Add support for RZ/G2M (R8A774A1) SoC power areas to the R-Car SYSC
driver.
Signed-off-by: Biju Das
Reviewed-by: Chris Paterson
Reviewed-by: Geert Uytterhoeven
---
V1-->V2
* No change
---
.../bindings/power/renesas,rcar-sysc.txt | 1 +
drivers/soc/renesas/Kcon
Add all RZ/G2M Clock Pulse Generator Core Clock Outputs, as listed in
Table 8.2b ("List of Clocks [RZ/G2M]") of the RZ/G2M Hardware User's
Manual.
Signed-off-by: Biju Das
Reviewed-by: Fabrizio Castro
Reviewed-by: Geert Uytterhoeven
---
V1--> V2
* Removed internal clock POST2.
--
Signed-off-by: Biju Das
Reviewed-by: Chris Paterson
Reviewed-by: Geert Uytterhoeven
---
V1-->V2
* No change
---
Documentation/devicetree/bindings/reset/renesas,rst.txt | 1 +
drivers/soc/renesas/Kconfig | 6 +++---
drivers/soc/renesas/rcar-rs
Hi Geert,
> Subject: Re: [PATCH v2 1/5] gpio: rcar: Add GPIO hole support
> On Thu, Aug 2, 2018 at 4:17 PM Biju Das wrote:
> > GPIO hole is present in RZ/G1C SoC. Valid GPIO pins on bank3 are in
> > the range GP3_0 to GP3_16 and GP3_27 to GP3_29. The GPIO pins
> between
Hi Geert,
Thanks for the feedback.
> -Original Message-
> From: devicetree-ow...@vger.kernel.org ow...@vger.kernel.org> On Behalf Of Geert Uytterhoeven
> Sent: 03 August 2018 10:10
> To: Biju Das
> Cc: Rob Herring ; Mark Rutland
> ; Simon Horman ; Magnus
>
Hi Geert,
Thanks for the feedback.
> -Original Message-
> From: Geert Uytterhoeven [mailto:ge...@linux-m68k.org]
> Sent: 30 July 2018 11:04
> To: Biju Das
> Cc: Linus Walleij ; open list:GPIO SUBSYSTEM
> ; Simon Horman ;
> Geert Uytterhoeven ; Chris Paterso
+ sergie
> -Original Message-
> From: Biju Das [mailto:biju@bp.renesas.com]
> Sent: 27 July 2018 10:22
> To: Laurent Pinchart ; Geert
> Uytterhoeven ; Linus Walleij
>
> Cc: Biju Das ; linux-renesas-
> s...@vger.kernel.org; linux-g...@vger.kernel.org; Simon H
Add EtherAVB groups and functions definitions for R8A77470 SoC.
Signed-off-by: Biju Das
Reviewed-by: Fabrizio Castro
---
This patch is based on the following discussion
https://www.mail-archive.com/linux-renesas-soc@vger.kernel.org/msg27480.html
and
https://en.wikipedia.org/wiki/Media
Describe GPIO blocks in the R8A77470 device tree.
Signed-off-by: Biju Das
Reviewed-by: Fabrizio Castro
---
arch/arm/boot/dts/r8a77470.dtsi | 90 +
1 file changed, 90 insertions(+)
diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470
This patch series aims to add GPIO and EAVB Pinctrl support
for RZ/G1C SoC.
Biju Das (4):
gpio: rcar: Enhance gpio-ranges support
ARM: dts: r8a77470: Add GPIO support
ARM: dts: iwg23s-sbc: specify EtherAVB PHY IRQ
ARM: dts: iwg23s-sbc: Add pinctl support for EtherAVB
arch/arm/boot/dts
Adding pinctrl support for EtherAVB interface.
Signed-off-by: Biju Das
Reviewed-by: Fabrizio Castro
---
This patch depends upon
https://patchwork.kernel.org/patch/10546801/
---
arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot
Specify EtherAVB PHY IRQ in the board specific device tree, now that we
have GPIO support.
Signed-off-by: Biju Das
Reviewed-by: Fabrizio Castro
---
arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
b
Enhance gpio-ranges to support more than one gpio-range.
Signed-off-by: Biju Das
Reviewed-by: Fabrizio Castro
---
cat /sys/kernel/debug/pinctrl/e606.pin-controller-sh-pfc/gpio-
GPIO ranges handled:
0: e605.gpio GPIOS [1001 - 1023] PINS [0 - 22]
0: e6051000.gpio GPIOS [978 - 1000] PINS
Hi Geert,
Thanks for the feedback.
Subject: Re: [PATCH 4/4] ARM: dts: iwg23s-sbc: Add pinctl support for
> > {
> > + avb_pins: avb {
> > + groups = "avb_mdio", "avb_gmii_tx_rx";
>
> avb_crs is wired, but deemed unused, right?
Yes, CRS is not used in full duplex mode.
>
Hi Geert,
> Subject: Re: [PATCH 1/4] gpio: rcar: Enhance gpio-ranges support
> A simple way to work around this is to set ngpios to the highest bit number in
> use + 1. But you still need a mechanism to avoid accessing the unused bits in
> the gap between 16 and 27.
>
I will send V2 with
Hi Geert,
Thanks for the feedback.
> Subject: Re: [PATCH 5/5] clk: renesas: cpg-mssr: Add r8a774a1 support
>
> Hi Biju,
>
> On Mon, Jul 30, 2018 at 9:54 AM Biju Das wrote:
> > Add RZ/G2M (R8A774A1) Clock Pulse Generator / Module Standby and
> > Software Reset support.
Hi Geert,
Thanks for the feedback.
> Subject: Re: [PATCH 4/5] clk: renesas: Add r8a774a1 CPG Core Clock
> Definitions
>
> Hi Biju,
>
> On Mon, Jul 30, 2018 at 9:54 AM Biju Das wrote:
> > Add all RZ/G2M Clock Pulse Generator Core Clock Outputs, as listed in
> > T
Update the DT bindings documentation with the optional gpio-reserved-ranges
properties.
Signed-off-by: Biju Das
Reviewed-by: Fabrizio Castro
---
Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings
GPIO hole is present in RZ/G1C SoC. Valid GPIO pins on bank3 are in the
range GP3_0 to GP3_16 and GP3_27 to GP3_29. The GPIO pins between GP3_17
to GP3_26 are unused. Add support for handling unused GPIO's.
Signed-off-by: Biju Das
Reviewed-by: Fabrizio Castro
---
V1-->V2
* Added g
Describe GPIO blocks in the R8A77470 device tree.
Signed-off-by: Biju Das
Reviewed-by: Fabrizio Castro
---
This patch has runtime depency on the gpio driver patch.
gpioblock3 has gpio-reserved-ranges property.
---
arch/arm/boot/dts/r8a77470.dtsi | 91
Adding pinctrl support for EtherAVB interface.
Signed-off-by: Biju Das
Reviewed-by: Fabrizio Castro
Reviewed-by: Geert Uytterhoeven
---
V1-->V2
* No change
Depend onthe below patch
https://patchwork.kernel.org/patch/10546801/
---
arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
This patch series aims to add GPIO and EAVB Pinctrl support
for RZ/G1C SoC.
V1-->V2
Add support for gpio-reserved-ranges
Biju Das (5):
gpio: rcar: Add GPIO hole support
dt-bindings: gpio: rcar: Add gpio-reserved-ranges support
ARM: dts: r8a77470: Add GPIO support
ARM: dts: iwg
Specify EtherAVB PHY IRQ in the board specific device tree, now that we
have GPIO support.
Signed-off-by: Biju Das
Reviewed-by: Fabrizio Castro
Reviewed-by: Geert Uytterhoeven
---
V1-->V2
* No change
* compile time dependency on gpio dtsi patch
---
arch/arm/boot/dts/r8a77470-iwg
This patch series aims to add SYSC/RST/Clock support for
for RZ/G2M SoC. RZ/G2M SoC is similar to R-Car Gen3 M3-W SoC.
V1-->V2
* Incorporated review comments
----
Biju Das (5):
dt-bindings: power: Add r8a774a1 SYSC power domain definitions
soc: renesas: rcar-sysc: Add r8a77
This patch adds power domain indices for RZ/G2M.
Signed-off-by: Biju Das
Reviewed-by: Chris Paterson
Reviewed-by: Geert Uytterhoeven
---
V1-->V2
* No change
---
include/dt-bindings/power/r8a774a1-sysc.h | 31 +++
1 file changed, 31 insertions(+)
create m
Add RZ/G2M (R8A774A1) Clock Pulse Generator / Module Standby and Software
Reset support.
Based on the Table 8.2b of "RZ/G Series, 2nd Generation User's Manual:
Hardware ((Rev. 0.61, June 12, 2018)".
Signed-off-by: Biju Das
Reviewed-by: Fabrizio Castro
---
.../devicetree/bindings/clo
Add support for RZ/G2M (R8A774A1) SoC power areas to the R-Car SYSC
driver.
Signed-off-by: Biju Das
Reviewed-by: Chris Paterson
---
.../bindings/power/renesas,rcar-sysc.txt | 1 +
drivers/soc/renesas/Kconfig| 5 +++
drivers/soc/renesas/Makefile
Signed-off-by: Biju Das
Reviewed-by: Chris Paterson
---
Documentation/devicetree/bindings/reset/renesas,rst.txt | 1 +
drivers/soc/renesas/Kconfig | 6 +++---
drivers/soc/renesas/rcar-rst.c | 4 +++-
3 files changed, 7 insertions(+), 4
Add all RZ/G2M Clock Pulse Generator Core Clock Outputs, as listed in
Table 8.2b ("List of Clocks [RZ/G2M]") of the RZ/G2M Hardware User's
Manual.
Signed-off-by: Biju Das
Reviewed-by: Fabrizio Castro
---
include/dt-bindings/clock/r8a774a1-cpg-mssr.h | 59 +
This patch series aims to add SYSC/RST/Clock support for
for RZ/G2M SoC. RZ/G2M SoC is similar to R-Car Gen3 M3-W SoC.
Biju Das (5):
dt-bindings: power: Add r8a774a1 SYSC power domain definitions
soc: renesas: rcar-sysc: Add r8a774a1 support
soc: renesas: rcar-rst: Add support for RZ/G2M
This patch adds power domain indices for RZ/G2M.
Signed-off-by: Biju Das
Reviewed-by: Chris Paterson
---
include/dt-bindings/power/r8a774a1-sysc.h | 31 +++
1 file changed, 31 insertions(+)
create mode 100644 include/dt-bindings/power/r8a774a1-sysc.h
diff --git
HI Geert,
Thanks for the feedback.
> -Original Message-
> From: Geert Uytterhoeven
> Sent: 04 August 2018 10:25
> To: Biju Das
> Cc: Linus Walleij ; open list:GPIO SUBSYSTEM
> ; Simon Horman ;
> Geert Uytterhoeven ; Chris Paterson
> ; Fabrizio Cas
Add a check for unused gpios to avoid chip->request() call to client
driver for unused gpios.
Signed-off-by: Biju Das
Reviewed-by: Fabrizio Castro
---
drivers/gpio/gpiolib.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpio/gpiolib.c b/drivers/g
Hi Chris,
Thanks for the feedback.
> Subject: RE: [PATCH 2/2] pinctrl: sh-pfc: r8a7796: Add R8A774A1 PFC support
>
> Hello Biju,
>
> > From: Biju Das
> > Sent: 13 August 2018 14:53
> >
> > Renesas RZ/G2M (r8a774a1) is pin compatible with R-Car M3-W (r8a7796),
Enable the Renesas RZ/G2M (R8A774A1) SoC in the ARM64 renesas_defconfig.
Signed-off-by: Biju Das
Reviewed-by: Fabrizio Castro
---
arch/arm64/configs/renesas_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/renesas_defconfig
b/arch/arm64/configs
Hi Simon,
Thanks for the feedback.
> -Original Message-
> From: devicetree-ow...@vger.kernel.org ow...@vger.kernel.org> On Behalf Of Simon Horman
> Sent: 17 August 2018 09:45
> To: Biju Das
> Cc: Rob Herring ; Mark Rutland
> ; Magnus Damm ;
> linux-renesas-soc@
Hi Simon,
Thanks for the feedback.
> Subject: Re: [PATCH] arm64: renesas_defconfig: enable R8A774A1 SoC
>
> On Tue, Aug 14, 2018 at 11:04:50AM +0100, Biju Das wrote:
> > Enable the Renesas RZ/G2M (R8A774A1) SoC in the ARM64
> renesas_defconfig.
> >
> > Signed-
Describe GPIO blocks in the R8A77470 device tree.
Signed-off-by: Biju Das
Reviewed-by: Fabrizio Castro
Reviewed-by: Geert Uytterhoeven
---
V2-->V3
* Moved gpio-reserved-ranges property just below gpio-ranges
---
arch/arm/boot/dts/r8a77470.dtsi |
Update the DT bindings documentation with the optional gpio-reserved-ranges
properties.
Signed-off-by: Biju Das
Reviewed-by: Fabrizio Castro
---
V2 --> V3
* Incorporated review comments.
---
.../devicetree/bindings/gpio/renesas,gpio-rcar.txt | 61 +-
1 file changed,
GPIO hole is present in RZ/G1C SoC. Valid GPIO pins on bank3 are in the
range GP3_0 to GP3_16 and GP3_27 to GP3_29. The GPIO pins between GP3_17
to GP3_26 are unused. Add support for handling unused GPIO's.
Signed-off-by: Biju Das
---
V1-->V2
* Added gpio-reserved-ranges support for handl
This patch series aims to add GPIO and EAVB Pinctrl support for RZ/G1C SoC.
V1-->V2
* Add support for gpio-reserved-ranges
V2-->V3
* Updated binding documentation
* Rework based on Geert's comment.
----
Biju Das (5):
gpio: rcar: Add GPIO hole support
dt-bindings: gpio: rca
Specify EtherAVB PHY IRQ in the board specific device tree, now that we
have GPIO support.
Signed-off-by: Biju Das
Reviewed-by: Fabrizio Castro
Reviewed-by: Geert Uytterhoeven
---
---
V1-->V2
* No change
V2-->V3
* No change
* compile time dependency on gpio dtsi
Adding pinctrl support for EtherAVB interface.
Signed-off-by: Biju Das
Reviewed-by: Fabrizio Castro
Reviewed-by: Geert Uytterhoeven
---
V1-->V2
* No change
V2-->V3
* No change
Depend onthe below patch
https://patchwork.kernel.org/patch/10546801/
---
arch/arm/bo
to a crash.
gpiochip_add_data_with_key() calls gpiochip_init_valid_mask() with of_node
as NULL. of_gpiochip_add() fills "of_node" and calls
of_gpiochip_init_valid_mask().
The fix is to move the assignment to chip->of_node from of_gpiochip_add()
to gpiochip_add_data_with_key().
Signed-off
Hi Linus,
Thanks for the feedback.
> Subject: Re: [PATCH v2 2/5] dt-bindings: gpio: rcar: Add gpio-reserved-ranges
> support
> > Update the DT bindings documentation with the optional
> > gpio-reserved-ranges properties.
> >
> > Signed-off-by: Biju Das
&g
Hello Fabrizio,
> Hello Biju,
>
> Thank you for your patch.
>
> > -Original Message-----
> > From: Biju Das
> > Sent: 13 August 2018 08:42
> > To: Rob Herring ; Mark Rutland
> > ; Catalin Marinas ;
> > Will Deacon
> > Cc: Biju Das ;
Hello Fab,
> > Subject: RE: [PATCH] arm64: dts: renesas: Initial r8a774a1 SoC device
> > tree
> >
> > Hello Fabrizio,
> >
> > > Hello Biju,
> > >
> > > Thank you for your patch.
> > >
> > > > -Original Message--
> > > > Subject: RE: [PATCH] arm64: dts: renesas: Initial r8a774a1 SoC
> > > > device tree
> > > >
> > > > Hello Fabrizio,
> > > >
> > > > > Hello Biju,
> > > > >
> > > > > Thank you for your patc
Enable the Renesas RZ/G2M (R8A774A1) SoC in the ARM64 defconfig.
Signed-off-by: Biju Das
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 4327f62..1c953ff 100644
--- a/arch/arm64/configs
Basic support for the RZ/G2M SoC.
Signed-off-by: Biju Das
---
arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 192 ++
1 file changed, 192 insertions(+)
create mode 100644 arch/arm64/boot/dts/renesas/r8a774a1.dtsi
diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
Basic support for the RZ/G2M SoC.
Signed-off-by: Biju Das
Reviewed-by: Fabrizio Castro
---
V1-->V2
* Removed the macro CPG_AUDIO_CLK_I, since at this point we don't
know whether we will have a common board for RZ/G2 H/M/N.
---
arch/arm64/boot/dts/renesas/r8a774a1.dtsi |
This patch series aims to add PFC support for RZ/G2M SoC.
Biju Das (2):
dt-bindings: pinctrl: sh-pfc: Document r8a774a1 PFC support
pinctrl: sh-pfc: r8a7796: Add R8A774A1 PFC support
.../bindings/pinctrl/renesas,pfc-pinctrl.txt | 1 +
drivers/pinctrl/sh-pfc/Kconfig
Document PFC support for the R8A774A1 SoC.
Signed-off-by: Biju Das
Reviewed-by: Fabrizio Castro
---
Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
b
Renesas RZ/G2M (r8a774a1) is pin compatible with R-Car M3-W (r8a7796),
however it doesn't have several automotive specific peripherals. Add
a r8a7796 specific pin groups/functions along with common pin
groups/functions for supporting both r8a7796 and r8a7794a1 SoC.
Signed-off-by: Biju Das
il says " Rob's (experimental) review
bot".
Previously for RZ/G1C upstreaming I have submitted the patches in similar
fashion.
Is anything changed?
> On Thu, 2 Aug 2018 15:56:34 +0100, Biju Das wrote:
> > Add all RZ/G2M Clock Pulse Generator Core Clock Outputs, as listed in
&
says " Rob's (experimental) review
bot".
Previously for RZ/G1C upstreaming I have submitted the patches in similar
fashion.
Is anything changed?
> On Thu, 2 Aug 2018 15:53:19 +0100, Biju Das wrote:
> > Add support for RZ/G2M (R8A774A1) SoC power areas to the R-Car SYSC
> > dr
Hello Simon,
Thanks for the feedback.
> Subject: Re: [PATCH v3 5/5] ARM: dts: iwg23s-sbc: Add pinctl support for
> EtherAVB
>
> On Tue, Aug 07, 2018 at 08:57:06AM +0100, Biju Das wrote:
> > Adding pinctrl support for EtherAVB interface.
> >
> > Signed-off-by: Biju
This patch series aims to add support for SYS-DMAC/INTC-EX/SCIF/HSCIF/
EAVB/RWDT on RZ/G2M SoC dtsi.
THis patch series based on renesas-devel-20180822-v4.18.
Biju Das (3):
arm64: dts: renesas: r8a774a1: Add SYS-DMAC controller nodes
arm64: dts: renesas: r8a774a1: Add INTC-EX device node
Add a device node for the Watchdog Timer (RWDT) controller on the Renesas
RZ/G2M (r8a774a1) SoC.
Signed-off-by: Biju Das
Reviewed-by: Fabrizio Castro
---
arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas
Add support for the Interrupt Controller for External Devices
(INTC-EX) on RZ/G2M.
Signed-off-by: Biju Das
Reviewed-by: Fabrizio Castro
---
arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 16
1 file changed, 16 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
From: Fabrizio Castro
This patch adds the SoC specific part of the Ethernet AVB
device tree node.
Signed-off-by: Fabrizio Castro
Reviewed-by: Biju Das
---
arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 45 +++
1 file changed, 45 insertions(+)
diff --git a/arch/arm64
-off-by: Fabrizio Castro
Reviewed-by: Biju Das
---
arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 185 ++
1 file changed, 185 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
index 4a4cf35..81fba7f 100644
Add sys-dmac[0-2] device nodes for RZ/G2M (r8a774a1) SoC.
Signed-off-by: Biju Das
Reviewed-by: Fabrizio Castro
---
arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 102 ++
1 file changed, 102 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
b/arch
This patch series aims to add USB2.0/USB3.0 Host/Function support
for RZ/G2M SoC. RZ/G2M SoC is similar to R-Car Gen3 M3-W SoC.
---
This patch series depend on
https://patchwork.kernel.org/patch/10574109/
---
Biju Das (3):
arm64: dts: renesas: r8a774a1: Add USB2.0 phy and host(EHCI/OHCI
Add usb dmac and hsusb device nodes on RZ/G2M SoC dtsi.
Signed-off-by: Biju Das
Reviewed-by: Fabrizio Castro
---
arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 45 +++
1 file changed, 45 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
b/arch
Add usb3.0 phy, host and function device nodes on RZ/G2M SoC dtsi.
Signed-off-by: Biju Das
Reviewed-by: Fabrizio Castro
---
arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 35 +++
1 file changed, 35 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
Add USB2.0 phy and host (EHCI/OHCI) device nodes on RZ/G2M SoC dtsi.
Signed-off-by: Biju Das
Reviewed-by: Fabrizio Castro
---
arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 73 +++
1 file changed, 73 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
Hi Kieran,
Thanks for the feedback.
> Subject: Re: Regarding VIN test(cvbs capture:- PAL resolution)
> On 29/08/18 11:41, Biju Das wrote:
> > Hi All,
> >
> >
> >
> > I started testing vin on R-Car Gen3(CVBS input from DVD player
> > connected to R-Ca
Hi Niklas,
Thanks for the feedback. I confirm it works.
> Subject: Re: Regarding VIN test(cvbs capture:- PAL resolution)
>
> Hi Biju,
>
> On 2018-08-29 10:41:16 +, Biju Das wrote:
> > Hi All,
> >
> > I started testing vin on R-Car Gen3(CVBS input from DVD
Adding pinctrl support for scif1 interface.
Signed-off-by: Biju Das
Reviewed-by: Chris Paterson
---
arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
Define the generic R8A77470 part of the PFC device node.
Signed-off-by: Biju Das
Reviewed-by: Fabrizio Castro
---
Commit 73dacc3403436fc2 ("pinctrl: sh-pfc: Add r8a77470 PFC support")
is in Linus' tree
---
arch/arm/boot/dts/r8a77470.dtsi | 5 +
1 file changed, 5 insertions(+)
Replace the hardcoded power domain indices by R8A77470_PD_* symbols.
Signed-off-by: Biju Das
Reviewed-by: Chris Paterson
---
Commit 964f7c0dd23de68c0 ("soc: renesas: rcar-sysc: Add r8a77470 support")
is in Linus' tree
---
arch/arm/boot/dts/r8a77470.dtsi | 27 ++--
Add device tree bindings documentation for Renesas RZ/G2M (r8a774a1) SoC.
Signed-off-by: Biju Das
Reviewed-by: Chris Paterson
---
Documentation/devicetree/bindings/arm/shmobile.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt
b
Add configuration option for the RZ/G2M (R8A774A1) SoC.
Signed-off-by: Biju Das
Reviewed-by: Chris Paterson
---
arch/arm64/Kconfig.platforms | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index d5aeac3..6b9f487 100644
This patch adds support for identifying the RZ/G2M (r8a774a1) SoC.
It corrects the original RZ/G SoC family name to RZ/G1 and also
adds support for the new RZ/G2 SoC family.
Signed-off-by: Biju Das
Reviewed-by: Chris Paterson
---
This patch corrects the RZ/G family name. Can it be
considered
This patch series aims to add SoC identification support
for RZ/G2M SoC. RZ/G2M SoC is similar to R-Car Gen3 M3-W SoC.
Biju Das (3):
dt-bindings: arm: Document RZ/G2M SoC DT bindings
arm64: Add Renesas R8A774A1 support
soc: renesas: Identify RZ/G2M
Documentation/devicetree/bindings/arm
Hi Geert,
Thanks for the patch.
> -Original Message-
> From: Geert Uytterhoeven [mailto:geert+rene...@glider.be]
> Sent: 17 July 2018 14:26
> To: Simon Horman ; Magnus Damm
> ; Biju Das
> Cc: linux-renesas-soc@vger.kernel.org; Geert Uytterhoeven
>
> Subject: [P
Hello Marc,
Sorry to bother you. Do you get a chance to sync up with Thomas for this patch
to make it into
4.18?
Regards,
Biju
> -Original Message-
> From: Marc Zyngier [mailto:marc.zyng...@arm.com]
> Sent: 27 June 2018 09:58
> To: Biju Das
> Cc: Thomas Gleixner
Hi Sergie,
Thanks for the patch
> -Original Message-
> From: devicetree-ow...@vger.kernel.org ow...@vger.kernel.org> On Behalf Of Sergei Shtylyov
> Sent: 05 September 2018 21:32
> To: Daniel Lezcano ; Thomas Gleixner
> ; Rob Herring ;
> devicet...@vger.kernel.org
> Cc:
Add VIN and CSI-2 nodes to RZ/G2M SoC dtsi.
Signed-off-by: Biju Das
Reviewed-by: Fabrizio Castro
---
arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 367 ++
1 file changed, 367 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
b/arch/arm64/boot/dts
Hi Sergie,
Thanks for the patch.
> Subject: [PATCH] clocksource: sh_cmt: fixup for 64-bit machines
>
> When trying to use CMT for clockevents on R-Car gen3 SoCs, I noticed that
> the maximum delta (in ns) for the broadcast timer was diplayed as 1000 in
%s/ diplayed/displayed
Regards,
Biju
Signed-off-by: Biju Das
Reviewed-by: Fabrizio Castro
---
drivers/soc/renesas/rcar-rst.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/soc/renesas/rcar-rst.c b/drivers/soc/renesas/rcar-rst.c
index a447873..1e11776 100644
--- a/drivers/soc/renesas/rcar-rst.c
+++ b/drivers/soc
Add minimal support for the RZ/G1N (R8A7744) SoC.
Signed-off-by: Biju Das
Reviewed-by: Fabrizio Castro
---
arch/arm/mach-shmobile/Kconfig | 5 +
arch/arm/mach-shmobile/setup-rcar-gen2.c | 2 ++
2 files changed, 7 insertions(+)
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch
Add power domain indices for RZ/G1N (R8A7744) SoC.
Signed-off-by: Biju Das
Reviewed-by: Fabrizio Castro
---
include/dt-bindings/power/r8a7744-sysc.h | 24
1 file changed, 24 insertions(+)
create mode 100644 include/dt-bindings/power/r8a7744-sysc.h
diff --git
Add support for RZ/G1N (R8A7744) SoC power areas to the R-Car SYSC driver.
Signed-off-by: Biju Das
Reviewed-by: Fabrizio Castro
---
drivers/soc/renesas/Kconfig | 2 +-
drivers/soc/renesas/rcar-sysc.c | 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/soc/renesas
Add the compatible strings for supporting the generic cpufreq driver on
the Renesas RZ/G1N (R8A7744) SoC.
Signed-off-by: Biju Das
Reviewed-by: Fabrizio Castro
---
drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c
b
Document bindings for the RZ/G1N (R8A7744) reset module.
Signed-off-by: Biju Das
Reviewed-by: Fabrizio Castro
---
Documentation/devicetree/bindings/reset/renesas,rst.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/reset/renesas,rst.txt
b/Documentation
Add binding documentation for the RZ/G1N (R8A7744) Clock Pulse
Generator driver.
Signed-off-by: Biju Das
Reviewed-by: Fabrizio Castro
---
Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/Documentation
Add RZ/G1N (R8A7744) Clock Pulse Generator / Module Standby and Software
Reset support.
Signed-off-by: Biju Das
Reviewed-by: Fabrizio Castro
---
drivers/clk/renesas/Kconfig| 2 +-
drivers/clk/renesas/r8a7743-cpg-mssr.c | 13 -
drivers/clk/renesas/renesas-cpg-mssr.c
Add all RZ/G1N Clock Pulse Generator Core Clock Outputs, as listed in
Table 7.2b ("List of Clocks [RZ/G1M/N]") of the RZ/G1 Hardware User's
Manual.
Signed-off-by: Biju Das
Reviewed-by: Fabrizio Castro
---
include/dt-bindings/clock/r8a7744-cpg-mssr.h | 39 ++
Hi Rafael,
Thanks for the feedback.
> -Original Message-
> From: Rafael J. Wysocki
> Sent: 11 September 2018 11:59
> To: Biju Das
> Cc: Rafael J. Wysocki ; Viresh Kumar
> ; Linux PM ; Simon
> Horman ; Geert Uytterhoeven
> ; Chris Paterson
> ; Fabrizio
This patch series aims to add support for RZ/G1N (R8A7744) PFC driver.
RZ/G1N SoC is similar to RZ/G1M and R-Car Gen2 M2-W/M2-N SoC.
This patchset is based on renesas-devel-20180906-v4.19-rc2.
Biju Das (2):
dt-bindings: pinctrl: sh-pfc: Document r8a7744 PFC support
pinctrl: sh-pfc: r8a7791
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