[PATCH v2 01/11] soc: renesas: Rename SYSC_R8A7796 to SYSC_R8A77960
Rename CONFIG_SYSC_R8A7796 for R-Car M3-W (R8A77960) to
CONFIG_SYSC_R8A77960, to avoid confusion with R-Car M3-W+ (R8A77961),
which will use CONFIG_SYSC_R8A77961.
Rename r8a7796_sysc_info and r8a7796_sysc_init for consistency.
Signed-off-by: Geert Uytterhoeven
---
v2:
- New.
---
drivers/soc/renesas/Kconfig| 4 ++--
drivers/soc/renesas/Makefile | 2 +-
drivers/soc/renesas/r8a7796-sysc.c | 8
drivers/soc/renesas/rcar-sysc.c| 4 ++--
drivers/soc/renesas/rcar-sysc.h| 2 +-
5 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig
index 3bd0c218bf30992a..328d7c409202e6a5 100644
--- a/drivers/soc/renesas/Kconfig
+++ b/drivers/soc/renesas/Kconfig
@@ -202,7 +202,7 @@ config ARCH_R8A7795
config ARCH_R8A7796
bool "Renesas R-Car M3-W SoC Platform"
select ARCH_RCAR_GEN3
- select SYSC_R8A7796
+ select SYSC_R8A77960
help
This enables support for the Renesas R-Car M3-W SoC.
@@ -292,7 +292,7 @@ config SYSC_R8A7795
bool "R-Car H3 System Controller support" if COMPILE_TEST
select SYSC_RCAR
-config SYSC_R8A7796
+config SYSC_R8A77960
bool "R-Car M3-W System Controller support" if COMPILE_TEST
select SYSC_RCAR
diff --git a/drivers/soc/renesas/Makefile b/drivers/soc/renesas/Makefile
index e99dc37ea1209444..d8a7cfdc9c9cc45f 100644
--- a/drivers/soc/renesas/Makefile
+++ b/drivers/soc/renesas/Makefile
@@ -15,7 +15,7 @@ obj-$(CONFIG_SYSC_R8A7791)+= r8a7791-sysc.o
obj-$(CONFIG_SYSC_R8A7792) += r8a7792-sysc.o
obj-$(CONFIG_SYSC_R8A7794) += r8a7794-sysc.o
obj-$(CONFIG_SYSC_R8A7795) += r8a7795-sysc.o
-obj-$(CONFIG_SYSC_R8A7796) += r8a7796-sysc.o
+obj-$(CONFIG_SYSC_R8A77960)+= r8a7796-sysc.o
obj-$(CONFIG_SYSC_R8A77965)+= r8a77965-sysc.o
obj-$(CONFIG_SYSC_R8A77970)+= r8a77970-sysc.o
obj-$(CONFIG_SYSC_R8A77980)+= r8a77980-sysc.o
diff --git a/drivers/soc/renesas/r8a7796-sysc.c
b/drivers/soc/renesas/r8a7796-sysc.c
index d374622a667bbfbd..c2accd8d76686ef4 100644
--- a/drivers/soc/renesas/r8a7796-sysc.c
+++ b/drivers/soc/renesas/r8a7796-sysc.c
@@ -47,16 +47,16 @@ static const struct soc_device_attribute r8a7796es1[]
__initconst = {
{ /* sentinel */ }
};
-static int __init r8a7796_sysc_init(void)
+static int __init r8a77960_sysc_init(void)
{
if (soc_device_match(r8a7796es1))
- r8a7796_sysc_info.extmask_val = 0;
+ r8a77960_sysc_info.extmask_val = 0;
return 0;
}
-struct rcar_sysc_info r8a7796_sysc_info __initdata = {
- .init = r8a7796_sysc_init,
+struct rcar_sysc_info r8a77960_sysc_info __initdata = {
+ .init = r8a77960_sysc_init,
.areas = r8a7796_areas,
.num_areas = ARRAY_SIZE(r8a7796_areas),
.extmask_offs = 0x2f8,
diff --git a/drivers/soc/renesas/rcar-sysc.c b/drivers/soc/renesas/rcar-sysc.c
index d4f2ed52b2b363be..5f17b12e9d0c6a87 100644
--- a/drivers/soc/renesas/rcar-sysc.c
+++ b/drivers/soc/renesas/rcar-sysc.c
@@ -313,8 +313,8 @@ static const struct of_device_id rcar_sysc_matches[]
__initconst = {
#ifdef CONFIG_SYSC_R8A7795
{ .compatible = "renesas,r8a7795-sysc", .data = &r8a7795_sysc_info },
#endif
-#ifdef CONFIG_SYSC_R8A7796
- { .compatible = "renesas,r8a7796-sysc", .data = &r8a7796_sysc_info },
+#ifdef CONFIG_SYSC_R8A77960
+ { .compatible = "renesas,r8a7796-sysc", .data = &r8a77960_sysc_info },
#endif
#ifdef CONFIG_SYSC_R8A77965
{ .compatible = "renesas,r8a77965-sysc", .data = &r8a77965_sysc_info },
diff --git a/drivers/soc/renesas/rcar-sysc.h b/drivers/soc/renesas/rcar-sysc.h
index e4c9854f5dc00492..379a6b2661ebce87 100644
--- a/drivers/soc/renesas/rcar-sysc.h
+++ b/drivers/soc/renesas/rcar-sysc.h
@@ -61,7 +61,7 @@ extern const struct rcar_sysc_info r8a7791_sysc_info;
extern const struct rcar_sysc_info r8a7792_sysc_info;
extern const struct rcar_sysc_info r8a7794_sysc_info;
extern struct rcar_sysc_info r8a7795_sysc_info;
-extern struct rcar_sysc_info r8a7796_sysc_info;
+extern struct rcar_sysc_info r8a77960_sysc_info;
extern const struct rcar_sysc_info r8a77965_sysc_info;
extern const struct rcar_sysc_info r8a77970_sysc_info;
extern const struct rcar_sysc_info r8a77980_sysc_info;
--
2.17.1
[PATCH v2 08/11] arm64: dts: renesas: Add Renesas R8A77961 SoC support
Add initial support for the Renesas R-Car M3-W+ (R8A77961) SoC.
This includes:
- Cortex-A57 and Cortex-A53 CPU cores
(incl. L2 caches and power state definitions),
- Power Management Unit,
- PSCI firmware,
- Pin Function Controller,
- Clock, Reset, System, and Interrupt Controllers,
- SCIF2 serial console,
- Product Register,
- ARM Architectured Timer,
and various placeholders to allow to use salvator-xs.dtsi.
Based on r8a7796.dtsi.
Signed-off-by: Geert Uytterhoeven
Reviewed-by: Yoshihiro Shimoda
Tested-by: Yoshihiro Shimoda
---
v2:
- Add Reviewed-by, Tested-by.
---
arch/arm64/boot/dts/renesas/r8a77961.dtsi | 723 ++
1 file changed, 723 insertions(+)
create mode 100644 arch/arm64/boot/dts/renesas/r8a77961.dtsi
diff --git a/arch/arm64/boot/dts/renesas/r8a77961.dtsi
b/arch/arm64/boot/dts/renesas/r8a77961.dtsi
new file mode 100644
index ..64466c86b698826d
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a77961.dtsi
@@ -0,0 +1,723 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the R-Car M3-W+ (R8A77961) SoC
+ *
+ * Copyright (C) 2016-2017 Renesas Electronics Corp.
+ */
+
+#include
+#include
+#include
+
+#define CPG_AUDIO_CLK_IR8A77961_CLK_S0D4
+
+/ {
+ compatible = "renesas,r8a77961";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ /*
+* The external audio clocks are configured as 0 Hz fixed frequency
+* clocks by default.
+* Boards that provide audio clocks should override them.
+*/
+ audio_clk_a: audio_clk_a {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ audio_clk_b: audio_clk_b {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ audio_clk_c: audio_clk_c {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ /* External CAN clock - to be overridden by boards that provide it */
+ can_clk: can {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ cluster0_opp: opp_table0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-5 {
+ opp-hz = /bits/ 64 <5>;
+ opp-microvolt = <82>;
+ clock-latency-ns = <30>;
+ };
+ opp-10 {
+ opp-hz = /bits/ 64 <10>;
+ opp-microvolt = <82>;
+ clock-latency-ns = <30>;
+ };
+ opp-15 {
+ opp-hz = /bits/ 64 <15>;
+ opp-microvolt = <82>;
+ clock-latency-ns = <30>;
+ };
+ opp-16 {
+ opp-hz = /bits/ 64 <16>;
+ opp-microvolt = <90>;
+ clock-latency-ns = <30>;
+ turbo-mode;
+ };
+ opp-17 {
+ opp-hz = /bits/ 64 <17>;
+ opp-microvolt = <90>;
+ clock-latency-ns = <30>;
+ turbo-mode;
+ };
+ opp-18 {
+ opp-hz = /bits/ 64 <18>;
+ opp-microvolt = <96>;
+ clock-latency-ns = <30>;
+ turbo-mode;
+ };
+ };
+
+ cluster1_opp: opp_table1 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-8 {
+ opp-hz = /bits/ 64 <8>;
+ opp-microvolt = <82>;
+ clock-latency-ns = <30>;
+ };
+ opp-10 {
+ opp-hz = /bits/ 64 <10>;
+ opp-microvolt = <82>;
+ clock-latency-ns = <30>;
+ };
+ opp-12 {
+ opp-hz = /bits/ 64 <12>;
+ opp-microvolt = <82>;
+ clock-latency-ns = <30>;
+ };
+ opp-13 {
+ opp-hz = /bits/ 64 <13>;
+
[PATCH v2 02/11] soc: renesas: Add ARCH_R8A77960 for existing R-Car M3-W
Add CONFIG_ARCH_R8A77960 as a new config symbol for R-Car M3-W
(R8A77960), to replace CONFIG_ARCH_R8A7796, and avoid confusion with
R-Car M3-W+ (R8A77961), which will use CONFIG_ARCH_R8A77961.
Note that for now, CONFIG_ARCH_R8A7796 is retained, and just selects
CONFIG_ARCH_R8A77960. This relaxes dependencies of other subsystems on
the SoC configuration symbol, and provides a smooth transition path for
config files through "make oldconfig".
Signed-off-by: Geert Uytterhoeven
---
v2:
- New.
---
drivers/soc/renesas/Kconfig | 8 ++--
drivers/soc/renesas/renesas-soc.c | 2 +-
2 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig
index 328d7c409202e6a5..ce8e86a037d1d704 100644
--- a/drivers/soc/renesas/Kconfig
+++ b/drivers/soc/renesas/Kconfig
@@ -199,10 +199,14 @@ config ARCH_R8A7795
help
This enables support for the Renesas R-Car H3 SoC.
-config ARCH_R8A7796
- bool "Renesas R-Car M3-W SoC Platform"
+config ARCH_R8A77960
+ bool
select ARCH_RCAR_GEN3
select SYSC_R8A77960
+
+config ARCH_R8A7796
+ bool "Renesas R-Car M3-W SoC Platform"
+ select ARCH_R8A77960
help
This enables support for the Renesas R-Car M3-W SoC.
diff --git a/drivers/soc/renesas/renesas-soc.c
b/drivers/soc/renesas/renesas-soc.c
index 45135bc88e277d34..319e47bb1d99cfcf 100644
--- a/drivers/soc/renesas/renesas-soc.c
+++ b/drivers/soc/renesas/renesas-soc.c
@@ -262,7 +262,7 @@ static const struct of_device_id renesas_socs[] __initconst
= {
#ifdef CONFIG_ARCH_R8A7795
{ .compatible = "renesas,r8a7795", .data = &soc_rcar_h3 },
#endif
-#ifdef CONFIG_ARCH_R8A7796
+#ifdef CONFIG_ARCH_R8A77960
{ .compatible = "renesas,r8a7796", .data = &soc_rcar_m3_w },
#endif
#ifdef CONFIG_ARCH_R8A77965
--
2.17.1
[PATCH v2 07/11] arm64: dts: renesas: Prepare for rename of ARCH_R8A7796 to ARCH_R8A77960
CONFIG_ARCH_R8A7796 for R-Car M3-W (R8A77960) will be renamed to CONFIG_ARCH_R8A77960, to avoid confusion with R-Car M3-W+ (R8A77961), which will use CONFIG_ARCH_R8A77961. Relax dependencies by handling both symbols. Signed-off-by: Geert Uytterhoeven --- v2: - New. --- arch/arm64/boot/dts/renesas/Makefile | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile index 72234e1709a9f19c..937a3e4c3fadebb3 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -12,6 +12,9 @@ dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-es1-h3ulcb-kf.dtb dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-x.dtb r8a7796-m3ulcb.dtb dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-m3ulcb-kf.dtb dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-xs.dtb +dtb-$(CONFIG_ARCH_R8A77960) += r8a7796-salvator-x.dtb r8a7796-m3ulcb.dtb +dtb-$(CONFIG_ARCH_R8A77960) += r8a7796-m3ulcb-kf.dtb +dtb-$(CONFIG_ARCH_R8A77960) += r8a7796-salvator-xs.dtb dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-salvator-x.dtb r8a77965-salvator-xs.dtb dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-m3nulcb.dtb dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-m3nulcb-kf.dtb -- 2.17.1
[PATCH v2 06/11] soc: renesas: rcar-sysc: Add R8A77961 support
Add support for the power areas in the Renesas R-Car M3-W+ (R8A77961)
SoC to the R-Car System Controller driver.
R-Car M3-W+ (aka R-Car M3-W ES3.0) is very similar to R-Car
M3-W (R8A77960), which allows for both SoCs to share a driver:
- R-Car M3-W+ lacks the A2VC power area, so its area must be
nullified,
- The existing support for the SYSCEXTMASK register added in commit
9bd645af9d2a49ac ("soc: renesas: r8a7796-sysc: Fix power request
conflicts") applies to ES3.0 and later only.
As R-Car M3-W+ uses a different compatible value, differentiate
based on that, instead of on the ES version.
Based on a patch in the BSP by Dien Pham .
Signed-off-by: Geert Uytterhoeven
Reviewed-by: Yoshihiro Shimoda
Tested-by: Yoshihiro Shimoda
---
v2:
- Add Reviewed-by, Tested-by,
- Move r8a7796_sysc_info rename to a prerequisite patch,
- Wrap SoC-specific parts in #ifdefs.
---
drivers/soc/renesas/Kconfig| 5 +
drivers/soc/renesas/Makefile | 1 +
drivers/soc/renesas/r8a7796-sysc.c | 27 +++
drivers/soc/renesas/rcar-sysc.c| 3 +++
drivers/soc/renesas/rcar-sysc.h| 3 ++-
5 files changed, 26 insertions(+), 13 deletions(-)
diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig
index 7b00daa290924445..f93492b72c04e237 100644
--- a/drivers/soc/renesas/Kconfig
+++ b/drivers/soc/renesas/Kconfig
@@ -213,6 +213,7 @@ config ARCH_R8A7796
config ARCH_R8A77961
bool "Renesas R-Car M3-W+ SoC Platform"
select ARCH_RCAR_GEN3
+ select SYSC_R8A77961
help
This enables support for the Renesas R-Car M3-W+ SoC.
@@ -306,6 +307,10 @@ config SYSC_R8A77960
bool "R-Car M3-W System Controller support" if COMPILE_TEST
select SYSC_RCAR
+config SYSC_R8A77961
+ bool "R-Car M3-W+ System Controller support" if COMPILE_TEST
+ select SYSC_RCAR
+
config SYSC_R8A77965
bool "R-Car M3-N System Controller support" if COMPILE_TEST
select SYSC_RCAR
diff --git a/drivers/soc/renesas/Makefile b/drivers/soc/renesas/Makefile
index d8a7cfdc9c9cc45f..e595c3c3bd104122 100644
--- a/drivers/soc/renesas/Makefile
+++ b/drivers/soc/renesas/Makefile
@@ -16,6 +16,7 @@ obj-$(CONFIG_SYSC_R8A7792)+= r8a7792-sysc.o
obj-$(CONFIG_SYSC_R8A7794) += r8a7794-sysc.o
obj-$(CONFIG_SYSC_R8A7795) += r8a7795-sysc.o
obj-$(CONFIG_SYSC_R8A77960)+= r8a7796-sysc.o
+obj-$(CONFIG_SYSC_R8A77961)+= r8a7796-sysc.o
obj-$(CONFIG_SYSC_R8A77965)+= r8a77965-sysc.o
obj-$(CONFIG_SYSC_R8A77970)+= r8a77970-sysc.o
obj-$(CONFIG_SYSC_R8A77980)+= r8a77980-sysc.o
diff --git a/drivers/soc/renesas/r8a7796-sysc.c
b/drivers/soc/renesas/r8a7796-sysc.c
index c2accd8d76686ef4..471bd5b3b6ada18d 100644
--- a/drivers/soc/renesas/r8a7796-sysc.c
+++ b/drivers/soc/renesas/r8a7796-sysc.c
@@ -1,19 +1,19 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Renesas R-Car M3-W System Controller
+ * Renesas R-Car M3-W/W+ System Controller
*
* Copyright (C) 2016 Glider bvba
+ * Copyright (C) 2018-2019 Renesas Electronics Corporation
*/
#include
#include
-#include
#include
#include "rcar-sysc.h"
-static const struct rcar_sysc_area r8a7796_areas[] __initconst = {
+static struct rcar_sysc_area r8a7796_areas[] __initdata = {
{ "always-on", 0, 0, R8A7796_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
{ "ca57-scu", 0x1c0, 0, R8A7796_PD_CA57_SCU, R8A7796_PD_ALWAYS_ON,
PD_SCU },
@@ -41,24 +41,27 @@ static const struct rcar_sysc_area r8a7796_areas[]
__initconst = {
};
-/* Fixups for R-Car M3-W ES1.x revision */
-static const struct soc_device_attribute r8a7796es1[] __initconst = {
- { .soc_id = "r8a7796", .revision = "ES1.*" },
- { /* sentinel */ }
+#ifdef CONFIG_SYSC_R8A77960
+const struct rcar_sysc_info r8a77960_sysc_info __initconst = {
+ .areas = r8a7796_areas,
+ .num_areas = ARRAY_SIZE(r8a7796_areas),
};
+#endif /* CONFIG_SYSC_R8A77960 */
-static int __init r8a77960_sysc_init(void)
+#ifdef CONFIG_SYSC_R8A77961
+static int __init r8a77961_sysc_init(void)
{
- if (soc_device_match(r8a7796es1))
- r8a77960_sysc_info.extmask_val = 0;
+ rcar_sysc_nullify(r8a7796_areas, ARRAY_SIZE(r8a7796_areas),
+ R8A7796_PD_A2VC0);
return 0;
}
-struct rcar_sysc_info r8a77960_sysc_info __initdata = {
- .init = r8a77960_sysc_init,
+const struct rcar_sysc_info r8a77961_sysc_info __initconst = {
+ .init = r8a77961_sysc_init,
.areas = r8a7796_areas,
.num_areas = ARRAY_SIZE(r8a7796_areas),
.extmask_offs = 0x2f8,
.extmask_val = BIT(0),
};
+#endif /* CONFIG_SYSC_R8A77961 */
diff --git a/drivers/soc/renesas/rcar-sysc.c b/drivers/soc/renesas/rcar-sysc.c
index 5f17b12e9d0c6a87..f0b291e02b8aba1b 100644
--- a/drivers/soc/renesas/rcar-sysc.c
+++ b/drivers/soc/renesas/rcar-sysc
[PATCH v2 10/11] arm64: defconfig: Enable R8A77961 SoC
Enable the Renesas R-Car M3-W+ (R8A77961) SoC in the ARM64 defconfig. Signed-off-by: Geert Uytterhoeven Reviewed-by: Yoshihiro Shimoda Tested-by: Yoshihiro Shimoda --- v2: - Add Reviewed-by, Tested-by. --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index c9adae41bac03e60..4a4e338c457e45db 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -745,6 +745,7 @@ CONFIG_ARCH_R8A774B1=y CONFIG_ARCH_R8A774C0=y CONFIG_ARCH_R8A7795=y CONFIG_ARCH_R8A7796=y +CONFIG_ARCH_R8A77961=y CONFIG_ARCH_R8A77965=y CONFIG_ARCH_R8A77970=y CONFIG_ARCH_R8A77980=y -- 2.17.1
[PATCH v2 03/11] soc: renesas: Add ARCH_R8A77961 for new R-Car M3-W+
Add CONFIG_ARCH_R8A77961 as a configuration symbol for the new Renesas R-Car M3-W+ (R8A77961) SoC. Signed-off-by: Geert Uytterhoeven Reviewed-by: Yoshihiro Shimoda Tested-by: Yoshihiro Shimoda --- v2: - Add Reviewed-by, Tested-by, - Reword. --- drivers/soc/renesas/Kconfig | 6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig index ce8e86a037d1d704..7b00daa290924445 100644 --- a/drivers/soc/renesas/Kconfig +++ b/drivers/soc/renesas/Kconfig @@ -210,6 +210,12 @@ config ARCH_R8A7796 help This enables support for the Renesas R-Car M3-W SoC. +config ARCH_R8A77961 + bool "Renesas R-Car M3-W+ SoC Platform" + select ARCH_RCAR_GEN3 + help + This enables support for the Renesas R-Car M3-W+ SoC. + config ARCH_R8A77965 bool "Renesas R-Car M3-N SoC Platform" select ARCH_RCAR_GEN3 -- 2.17.1
[PATCH/LOCAL v2 11/11] arm64: renesas_defconfig: Enable R8A77961 SoC
Enable the Renesas R-Car M3-W+ (R8A77961) SoC in the ARM64 renesas_defconfig. Signed-off-by: Geert Uytterhoeven Reviewed-by: Yoshihiro Shimoda Tested-by: Yoshihiro Shimoda --- Not intended for upstream inclusion. v2: - Add Reviewed-by, Tested-by. --- arch/arm64/configs/renesas_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/renesas_defconfig b/arch/arm64/configs/renesas_defconfig index 2ad65929c95b63bf..8c3a3323b1859c7d 100644 --- a/arch/arm64/configs/renesas_defconfig +++ b/arch/arm64/configs/renesas_defconfig @@ -287,6 +287,7 @@ CONFIG_ARCH_R8A774B1=y CONFIG_ARCH_R8A774C0=y CONFIG_ARCH_R8A7795=y CONFIG_ARCH_R8A7796=y +CONFIG_ARCH_R8A77961=y CONFIG_ARCH_R8A77965=y CONFIG_ARCH_R8A77970=y CONFIG_ARCH_R8A77980=y -- 2.17.1
[PATCH v2 00/11] arm64: renesas: Add r8a77961 support
Hi all,
This patch series adds initial support for the Renesas R-Car M3-W+
(R8A77961) SoC, and for the Salvator-XS development board equipped with
this SoC. As R-Car M3-W+ is very similar to R-Car M3-W (R8A77960), the
existing RST and SYSC drivers are updated to handle both.
To avoid confusion between R-Car M3-W and M3-W+, a new config symbol
(ARCH_R8A77960) is introduced for M3-W, to replace the old symbol
(ARCH_R8A7796) later. The old symbol will be removed when all users in
other subsystems have been converted to use the new symbol.
The existing config symbol for M3-W SYSC is renamed to SYSC_R8A77960.
Changes compared to v1[1]:
- Split in per-subsystem series,
- Add Reviewed-by, Tested-by,
- Rename SYSC_R8A7796,
- Add ARCH_R8A77960,
- Prepare for future removal of ARCH_R8A7796,
- Wrap SoC-specific parts in #ifdefs.
I intend to queue this series in renesas-devel for v5.5 (except for the
local defconfig patch).
Note that arch/arm64/boot/dts/renesas/r8a77961.dtsi depends on the power
domain and clock domain indices from:
- "[PATCH v2 5/5] dt-bindings: power: Add r8a77961 SYSC power domain
definitions"[2],
- "[PATCH v2 2/4] dt-bindings: clock: Add r8a77961 CPG Core Clock
Definitions"[3],
which will be put on a branch shared by drivers and DTS.
For testing, I pushed this and all dependencies[2-5] to the
topic/r8a77961-v2 branch of my renesas-drivers git repository at
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git.
Thanks for your comments!
[1] "[PATCH/RFC 00/19] arm64: dts: renesas: Initial support for R-Car M3-W+"
https://lore.kernel.org/linux-renesas-soc/20191007102332.12196-1-geert+rene...@glider.be/
[2] "[PATCH v2 0/5] dt-bindings: arm: renesas: Add core r8a77961 support"
(https://lore.kernel.org/linux-renesas-soc/20191023122911.12166-1-geert+rene...@glider.be/)
[3] "[PATCH v2 0/4] clk: renesas: Add r8a77961 support"
(https://lore.kernel.org/linux-renesas-soc/20191023122941.12342-1-geert+rene...@glider.be/)
[4] "[PATCH v2 0/3] pinctrl: sh-pfc: Add r8a77961 support"
(https://lore.kernel.org/linux-renesas-soc/20191023122955.12420-1-geert+rene...@glider.be/)
[5] "[PATCH v2] dt-bindings: serial: sh-sci: Document r8a77961 bindings"
(https://lore.kernel.org/linux-renesas-soc/20191023123010.12501-1-geert+rene...@glider.be/)
Geert Uytterhoeven (11):
soc: renesas: Rename SYSC_R8A7796 to SYSC_R8A77960
soc: renesas: Add ARCH_R8A77960 for existing R-Car M3-W
soc: renesas: Add ARCH_R8A77961 for new R-Car M3-W+
soc: renesas: Identify R-Car M3-W+
soc: renesas: rcar-rst: Add R8A77961 support
soc: renesas: rcar-sysc: Add R8A77961 support
arm64: dts: renesas: Prepare for rename of ARCH_R8A7796 to
ARCH_R8A77960
arm64: dts: renesas: Add Renesas R8A77961 SoC support
arm64: dts: renesas: Add support for Salvator-XS with R-Car M3-W+
arm64: defconfig: Enable R8A77961 SoC
[LOCAL] arm64: renesas_defconfig: Enable R8A77961 SoC
arch/arm64/boot/dts/renesas/Makefile | 4 +
.../boot/dts/renesas/r8a77961-salvator-xs.dts | 31 +
arch/arm64/boot/dts/renesas/r8a77961.dtsi | 723 ++
arch/arm64/configs/defconfig | 1 +
arch/arm64/configs/renesas_defconfig | 1 +
drivers/soc/renesas/Kconfig | 21 +-
drivers/soc/renesas/Makefile | 3 +-
drivers/soc/renesas/r8a7796-sysc.c| 27 +-
drivers/soc/renesas/rcar-rst.c| 1 +
drivers/soc/renesas/rcar-sysc.c | 7 +-
drivers/soc/renesas/rcar-sysc.h | 3 +-
drivers/soc/renesas/renesas-soc.c | 5 +-
12 files changed, 807 insertions(+), 20 deletions(-)
create mode 100644 arch/arm64/boot/dts/renesas/r8a77961-salvator-xs.dts
create mode 100644 arch/arm64/boot/dts/renesas/r8a77961.dtsi
--
2.17.1
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
[PATCH v2 04/11] soc: renesas: Identify R-Car M3-W+
Add support for identifying the R-Car M3-W+ (R8A77961) SoC, which shares
the Product ID Number with R-Car M3-W (R8A77960), but differs in CUT
Number (Ver. 3.0), and uses a different compatible value.
Signed-off-by: Geert Uytterhoeven
Reviewed-by: Yoshihiro Shimoda
Tested-by: Yoshihiro Shimoda
---
v2:
- Add Reviewed-by, Tested-by,
- Reword.
---
drivers/soc/renesas/renesas-soc.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/soc/renesas/renesas-soc.c
b/drivers/soc/renesas/renesas-soc.c
index 319e47bb1d99cfcf..573cc6a98177ba2c 100644
--- a/drivers/soc/renesas/renesas-soc.c
+++ b/drivers/soc/renesas/renesas-soc.c
@@ -265,6 +265,9 @@ static const struct of_device_id renesas_socs[] __initconst
= {
#ifdef CONFIG_ARCH_R8A77960
{ .compatible = "renesas,r8a7796", .data = &soc_rcar_m3_w },
#endif
+#ifdef CONFIG_ARCH_R8A77961
+ { .compatible = "renesas,r8a77961", .data = &soc_rcar_m3_w },
+#endif
#ifdef CONFIG_ARCH_R8A77965
{ .compatible = "renesas,r8a77965", .data = &soc_rcar_m3_n },
#endif
--
2.17.1
[PATCH v2 05/11] soc: renesas: rcar-rst: Add R8A77961 support
Add support for the Reset block in the R-Car M3-W+ (R8A77961) SoC to the
Renesas R-Car RST driver.
Signed-off-by: Geert Uytterhoeven
Reviewed-by: Yoshihiro Shimoda
Tested-by: Yoshihiro Shimoda
---
v2:
- Add Reviewed-by, Tested-by,
- Reword.
---
drivers/soc/renesas/rcar-rst.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/soc/renesas/rcar-rst.c b/drivers/soc/renesas/rcar-rst.c
index cd5592977cefc22b..14d05a070dd3ecea 100644
--- a/drivers/soc/renesas/rcar-rst.c
+++ b/drivers/soc/renesas/rcar-rst.c
@@ -59,6 +59,7 @@ static const struct of_device_id rcar_rst_matches[]
__initconst = {
/* R-Car Gen3 */
{ .compatible = "renesas,r8a7795-rst", .data = &rcar_rst_gen3 },
{ .compatible = "renesas,r8a7796-rst", .data = &rcar_rst_gen3 },
+ { .compatible = "renesas,r8a77961-rst", .data = &rcar_rst_gen3 },
{ .compatible = "renesas,r8a77965-rst", .data = &rcar_rst_gen3 },
{ .compatible = "renesas,r8a77970-rst", .data = &rcar_rst_gen3 },
{ .compatible = "renesas,r8a77980-rst", .data = &rcar_rst_gen3 },
--
2.17.1
[PATCH v2 09/11] arm64: dts: renesas: Add support for Salvator-XS with R-Car M3-W+
Add initial support for the Renesas Salvator-X 2nd version development
board equipped with an R-Car M3-W+ SiP with 8 (2 x 4) GiB of RAM.
The memory map is as follows:
- Bank0: 4GiB RAM : 0x4800 -> 0x000bfff
0x00048000 -> 0x004
- Bank1: 4GiB RAM : 0x0006 -> 0x006
Based on a patch in the BSP by Takeshi Kihara
.
Signed-off-by: Geert Uytterhoeven
Reviewed-by: Yoshihiro Shimoda
Tested-by: Yoshihiro Shimoda
---
v2:
- Add Reviewed-by, Tested-by.
---
arch/arm64/boot/dts/renesas/Makefile | 1 +
.../boot/dts/renesas/r8a77961-salvator-xs.dts | 31 +++
2 files changed, 32 insertions(+)
create mode 100644 arch/arm64/boot/dts/renesas/r8a77961-salvator-xs.dts
diff --git a/arch/arm64/boot/dts/renesas/Makefile
b/arch/arm64/boot/dts/renesas/Makefile
index 937a3e4c3fadebb3..8fdbd2267384186b 100644
--- a/arch/arm64/boot/dts/renesas/Makefile
+++ b/arch/arm64/boot/dts/renesas/Makefile
@@ -15,6 +15,7 @@ dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-xs.dtb
dtb-$(CONFIG_ARCH_R8A77960) += r8a7796-salvator-x.dtb r8a7796-m3ulcb.dtb
dtb-$(CONFIG_ARCH_R8A77960) += r8a7796-m3ulcb-kf.dtb
dtb-$(CONFIG_ARCH_R8A77960) += r8a7796-salvator-xs.dtb
+dtb-$(CONFIG_ARCH_R8A77961) += r8a77961-salvator-xs.dtb
dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-salvator-x.dtb r8a77965-salvator-xs.dtb
dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-m3nulcb.dtb
dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-m3nulcb-kf.dtb
diff --git a/arch/arm64/boot/dts/renesas/r8a77961-salvator-xs.dts
b/arch/arm64/boot/dts/renesas/r8a77961-salvator-xs.dts
new file mode 100644
index ..4abd78ac1cd597d9
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a77961-salvator-xs.dts
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the Salvator-X 2nd version board with R-Car M3-W+
+ *
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+#include "r8a77961.dtsi"
+#include "salvator-xs.dtsi"
+
+/ {
+ model = "Renesas Salvator-X 2nd version board based on r8a77961";
+ compatible = "renesas,salvator-xs", "renesas,r8a77961";
+
+ memory@4800 {
+ device_type = "memory";
+ /* first 128MB is reserved for secure area. */
+ reg = <0x0 0x4800 0x0 0x7800>;
+ };
+
+ memory@4 {
+ device_type = "memory";
+ reg = <0x4 0x8000 0x0 0x8000>;
+ };
+
+ memory@6 {
+ device_type = "memory";
+ reg = <0x6 0x 0x1 0x>;
+ };
+};
--
2.17.1
[PATCH v2] dt-bindings: serial: sh-sci: Document r8a77961 bindings
Document support for the SCIF and HSCIF serial ports in the Renesas R-Car M3-W+ (R8A77961) SoC. Update all references to R-Car M3-W from "r8a7796" to "r8a77960", to avoid confusion between R-Car M3-W (R8A77960) and M3-W+. No driver update is needed. Signed-off-by: Geert Uytterhoeven Reviewed-by: Yoshihiro Shimoda --- v2: - Split v1[1] in per-subsystem series, - Add Reviewed-by, - Update R-Car M3-W references. [1] "[PATCH/RFC 00/19] arm64: dts: renesas: Initial support for R-Car M3-W+" https://lore.kernel.org/linux-renesas-soc/20191007102332.12196-1-geert+rene...@glider.be/ --- .../devicetree/bindings/serial/renesas,sci-serial.txt | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt index b143d9a21b2de13e..a5edf4b70c7ab657 100644 --- a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt +++ b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt @@ -54,8 +54,10 @@ Required properties: - "renesas,hscif-r8a7794" for R8A7794 (R-Car E2) HSCIF compatible UART. - "renesas,scif-r8a7795" for R8A7795 (R-Car H3) SCIF compatible UART. - "renesas,hscif-r8a7795" for R8A7795 (R-Car H3) HSCIF compatible UART. -- "renesas,scif-r8a7796" for R8A7796 (R-Car M3-W) SCIF compatible UART. -- "renesas,hscif-r8a7796" for R8A7796 (R-Car M3-W) HSCIF compatible UART. +- "renesas,scif-r8a7796" for R8A77960 (R-Car M3-W) SCIF compatible UART. +- "renesas,hscif-r8a7796" for R8A77960 (R-Car M3-W) HSCIF compatible UART. +- "renesas,scif-r8a77961" for R8A77961 (R-Car M3-W+) SCIF compatible UART. +- "renesas,hscif-r8a77961" for R8A77961 (R-Car M3-W+) HSCIF compatible UART. - "renesas,scif-r8a77965" for R8A77965 (R-Car M3-N) SCIF compatible UART. - "renesas,hscif-r8a77965" for R8A77965 (R-Car M3-N) HSCIF compatible UART. - "renesas,scif-r8a77970" for R8A77970 (R-Car V3M) SCIF compatible UART. -- 2.17.1
[PATCH v2 0/4] clk: renesas: Add r8a77961 support
Hi all,
This patch series adds support for the Clock Pulse Generator / Module
Standby and Software Reset block in the Renesas R-Car M3-W+ (R8A77961)
SoC. As R-Car M3-W+ is very similar to R-Car M3-W (R8A77960), the
existing driver for R-Car M3-W is updated to handle both.
To avoid confusion between R-Car M3-W and M3-W+, the existing config
symbol for M3-W is renamed to CLK_R8A77960 in a dependency-free way, and
references to r8a7796 are updated.
Changes compared to v1[1]:
- Split in per-subsystem series,
- Add Reviewed-by, Tested-by,
- Rename CLK_R8A7796,
- Update r8a7796 references,
I intend to queue this series in clk-renesas-for-v5.5.
The second patch will be put on a branch shared between driver and DTS.
Thanks for your comments!
[1] "[PATCH/RFC 00/19] arm64: dts: renesas: Initial support for R-Car M3-W+"
https://lore.kernel.org/linux-renesas-soc/20191007102332.12196-1-geert+rene...@glider.be/
Geert Uytterhoeven (4):
dt-bindings: clock: renesas: cpg-mssr: Document r8a77961 support
dt-bindings: clock: Add r8a77961 CPG Core Clock Definitions
clk: renesas: Rename CLK_R8A7796 to CLK_R8A77960
clk: renesas: r8a7796: Add R8A77961 CPG/MSSR support
.../bindings/clock/renesas,cpg-mssr.txt | 11 ++--
drivers/clk/renesas/Kconfig | 9 ++-
drivers/clk/renesas/Makefile | 3 +-
drivers/clk/renesas/r8a7796-cpg-mssr.c| 24 +--
drivers/clk/renesas/renesas-cpg-mssr.c| 8 ++-
include/dt-bindings/clock/r8a77961-cpg-mssr.h | 65 +++
6 files changed, 107 insertions(+), 13 deletions(-)
create mode 100644 include/dt-bindings/clock/r8a77961-cpg-mssr.h
--
2.17.1
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
[PATCH v2 3/5] dt-bindings: reset: rcar-rst: Document r8a77961 support
Add DT binding documentation for the Reset block in the Renesas R-Car M3-W+ (R8A77961) SoC. Signed-off-by: Geert Uytterhoeven Reviewed-by: Yoshihiro Shimoda --- v2: - Add Reviewed-by. --- Documentation/devicetree/bindings/reset/renesas,rst.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/reset/renesas,rst.txt b/Documentation/devicetree/bindings/reset/renesas,rst.txt index d6d6769a0c42735f..de7f06ccd003da9f 100644 --- a/Documentation/devicetree/bindings/reset/renesas,rst.txt +++ b/Documentation/devicetree/bindings/reset/renesas,rst.txt @@ -31,6 +31,7 @@ Required properties: - "renesas,r8a7794-rst" (R-Car E2) - "renesas,r8a7795-rst" (R-Car H3) - "renesas,r8a7796-rst" (R-Car M3-W) + - "renesas,r8a77961-rst" (R-Car M3-W+) - "renesas,r8a77965-rst" (R-Car M3-N) - "renesas,r8a77970-rst" (R-Car V3M) - "renesas,r8a77980-rst" (R-Car V3H) -- 2.17.1
[PATCH v2 3/3] pinctrl: sh-pfc: r8a7796: Add R8A77961 PFC support
Add support for the Pin Function Controller in the R-Car M3-W+
(R8A77961) SoC.
R-Car M3-W+ is pin compatible with R-Car M3-W (R8A77960), which allows
for both SoCs to share a driver.
Signed-off-by: Geert Uytterhoeven
Reviewed-by: Yoshihiro Shimoda
Tested-by: Yoshihiro Shimoda
---
v2:
- Add Reviewed-by, Tested-by,
- Move r8a7796_pinmux_info rename to a prerequisite patch.
---
drivers/pinctrl/sh-pfc/Kconfig | 4
drivers/pinctrl/sh-pfc/Makefile | 1 +
drivers/pinctrl/sh-pfc/core.c| 6 ++
drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 29 +++-
drivers/pinctrl/sh-pfc/sh_pfc.h | 1 +
5 files changed, 40 insertions(+), 1 deletion(-)
diff --git a/drivers/pinctrl/sh-pfc/Kconfig b/drivers/pinctrl/sh-pfc/Kconfig
index 93d6034be4ff63f2..28d66e7cb098863b 100644
--- a/drivers/pinctrl/sh-pfc/Kconfig
+++ b/drivers/pinctrl/sh-pfc/Kconfig
@@ -28,6 +28,7 @@ config PINCTRL_SH_PFC
select PINCTRL_PFC_R8A7794 if ARCH_R8A7794
select PINCTRL_PFC_R8A7795 if ARCH_R8A7795
select PINCTRL_PFC_R8A77960 if ARCH_R8A77960 || ARCH_R8A7796
+ select PINCTRL_PFC_R8A77961 if ARCH_R8A77961
select PINCTRL_PFC_R8A77965 if ARCH_R8A77965
select PINCTRL_PFC_R8A77970 if ARCH_R8A77970
select PINCTRL_PFC_R8A77980 if ARCH_R8A77980
@@ -120,6 +121,9 @@ config PINCTRL_PFC_R8A7795
config PINCTRL_PFC_R8A77960
bool "R-Car M3-W pin control support" if COMPILE_TEST
+config PINCTRL_PFC_R8A77961
+ bool "R-Car M3-W+ pin control support" if COMPILE_TEST
+
config PINCTRL_PFC_R8A77965
bool "R-Car M3-N pin control support" if COMPILE_TEST
diff --git a/drivers/pinctrl/sh-pfc/Makefile b/drivers/pinctrl/sh-pfc/Makefile
index e3594cd2620386af..3bc05666e1a6652e 100644
--- a/drivers/pinctrl/sh-pfc/Makefile
+++ b/drivers/pinctrl/sh-pfc/Makefile
@@ -21,6 +21,7 @@ obj-$(CONFIG_PINCTRL_PFC_R8A7794) += pfc-r8a7794.o
obj-$(CONFIG_PINCTRL_PFC_R8A7795) += pfc-r8a7795.o
obj-$(CONFIG_PINCTRL_PFC_R8A7795) += pfc-r8a7795-es1.o
obj-$(CONFIG_PINCTRL_PFC_R8A77960) += pfc-r8a7796.o
+obj-$(CONFIG_PINCTRL_PFC_R8A77961) += pfc-r8a7796.o
obj-$(CONFIG_PINCTRL_PFC_R8A77965) += pfc-r8a77965.o
obj-$(CONFIG_PINCTRL_PFC_R8A77970) += pfc-r8a77970.o
obj-$(CONFIG_PINCTRL_PFC_R8A77980) += pfc-r8a77980.o
diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c
index e3292abd6c9456f8..2959623e9b724f40 100644
--- a/drivers/pinctrl/sh-pfc/core.c
+++ b/drivers/pinctrl/sh-pfc/core.c
@@ -591,6 +591,12 @@ static const struct of_device_id sh_pfc_of_table[] = {
.data = &r8a77960_pinmux_info,
},
#endif
+#ifdef CONFIG_PINCTRL_PFC_R8A77961
+ {
+ .compatible = "renesas,pfc-r8a77961",
+ .data = &r8a77961_pinmux_info,
+ },
+#endif
#ifdef CONFIG_PINCTRL_PFC_R8A77965
{
.compatible = "renesas,pfc-r8a77965",
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
index 9de2909c7ad9dff0..a2496baca85d23f8 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * R8A7796 processor support - PFC hardware block.
+ * R8A7796 (R-Car M3-W/W+) support - PFC hardware block.
*
* Copyright (C) 2016-2019 Renesas Electronics Corp.
*
@@ -6236,3 +6236,30 @@ const struct sh_pfc_soc_info r8a77960_pinmux_info = {
.pinmux_data_size = ARRAY_SIZE(pinmux_data),
};
#endif
+
+#ifdef CONFIG_PINCTRL_PFC_R8A77961
+const struct sh_pfc_soc_info r8a77961_pinmux_info = {
+ .name = "r8a77961_pfc",
+ .ops = &r8a7796_pinmux_ops,
+ .unlock_reg = 0xe606, /* PMMR */
+
+ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
+
+ .pins = pinmux_pins,
+ .nr_pins = ARRAY_SIZE(pinmux_pins),
+ .groups = pinmux_groups.common,
+ .nr_groups = ARRAY_SIZE(pinmux_groups.common) +
+ ARRAY_SIZE(pinmux_groups.automotive),
+ .functions = pinmux_functions.common,
+ .nr_functions = ARRAY_SIZE(pinmux_functions.common) +
+ ARRAY_SIZE(pinmux_functions.automotive),
+
+ .cfg_regs = pinmux_config_regs,
+ .drive_regs = pinmux_drive_regs,
+ .bias_regs = pinmux_bias_regs,
+ .ioctrl_regs = pinmux_ioctrl_regs,
+
+ .pinmux_data = pinmux_data,
+ .pinmux_data_size = ARRAY_SIZE(pinmux_data),
+};
+#endif
diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h
index a7eb527fdc60ae25..640d2a4cb838804f 100644
--- a/drivers/pinctrl/sh-pfc/sh_pfc.h
+++ b/drivers/pinctrl/sh-pfc/sh_pfc.h
@@ -321,6 +321,7 @@ extern const struct sh_pfc_soc_info r8a7794_pinmux_info;
extern const struct sh_pfc_soc_info r8a7795_pinmux_info;
extern const struct sh_pfc_soc_info r8a7795es1_pinmux_info;
extern const struct sh_pfc_soc_info r8a77960_pinmux_info;
+extern
[PATCH v2 2/3] pinctrl: sh-pfc: Rename PINCTRL_PFC_R8A7796 to PINCTRL_PFC_R8A77960
Rename CONFIG_PINCTRL_PFC_R8A7796 for R-Car M3-W (R8A77960) to
CONFIG_PINCTRL_PFC_R8A77960, to avoid confusion with R-Car M3-W+
(R8A77961), which will use CONFIG_PINCTRL_PFC_R8A77961.
Extend the dependency of CONFIG_PINCTRL_PFC_R8A77960 from
CONFIG_ARCH_R8A7796 to CONFIG_ARCH_R8A77960, to relax dependencies for a
future rename of the SoC configuration symbol.
Rename r8a7796_pinmux_info to r8a77960_pinmux_info, as it contains an
r8a77960-based name.
Signed-off-by: Geert Uytterhoeven
---
v2:
- New.
---
drivers/pinctrl/sh-pfc/Kconfig | 4 ++--
drivers/pinctrl/sh-pfc/Makefile | 2 +-
drivers/pinctrl/sh-pfc/core.c| 4 ++--
drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 4 ++--
drivers/pinctrl/sh-pfc/sh_pfc.h | 2 +-
5 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/pinctrl/sh-pfc/Kconfig b/drivers/pinctrl/sh-pfc/Kconfig
index de2a33ab945bf1c2..93d6034be4ff63f2 100644
--- a/drivers/pinctrl/sh-pfc/Kconfig
+++ b/drivers/pinctrl/sh-pfc/Kconfig
@@ -27,7 +27,7 @@ config PINCTRL_SH_PFC
select PINCTRL_PFC_R8A7793 if ARCH_R8A7793
select PINCTRL_PFC_R8A7794 if ARCH_R8A7794
select PINCTRL_PFC_R8A7795 if ARCH_R8A7795
- select PINCTRL_PFC_R8A7796 if ARCH_R8A7796
+ select PINCTRL_PFC_R8A77960 if ARCH_R8A77960 || ARCH_R8A7796
select PINCTRL_PFC_R8A77965 if ARCH_R8A77965
select PINCTRL_PFC_R8A77970 if ARCH_R8A77970
select PINCTRL_PFC_R8A77980 if ARCH_R8A77980
@@ -117,7 +117,7 @@ config PINCTRL_PFC_R8A7794
config PINCTRL_PFC_R8A7795
bool "R-Car H3 pin control support" if COMPILE_TEST
-config PINCTRL_PFC_R8A7796
+config PINCTRL_PFC_R8A77960
bool "R-Car M3-W pin control support" if COMPILE_TEST
config PINCTRL_PFC_R8A77965
diff --git a/drivers/pinctrl/sh-pfc/Makefile b/drivers/pinctrl/sh-pfc/Makefile
index 00b12af651ebe744..e3594cd2620386af 100644
--- a/drivers/pinctrl/sh-pfc/Makefile
+++ b/drivers/pinctrl/sh-pfc/Makefile
@@ -20,7 +20,7 @@ obj-$(CONFIG_PINCTRL_PFC_R8A7793) += pfc-r8a7791.o
obj-$(CONFIG_PINCTRL_PFC_R8A7794) += pfc-r8a7794.o
obj-$(CONFIG_PINCTRL_PFC_R8A7795) += pfc-r8a7795.o
obj-$(CONFIG_PINCTRL_PFC_R8A7795) += pfc-r8a7795-es1.o
-obj-$(CONFIG_PINCTRL_PFC_R8A7796) += pfc-r8a7796.o
+obj-$(CONFIG_PINCTRL_PFC_R8A77960) += pfc-r8a7796.o
obj-$(CONFIG_PINCTRL_PFC_R8A77965) += pfc-r8a77965.o
obj-$(CONFIG_PINCTRL_PFC_R8A77970) += pfc-r8a77970.o
obj-$(CONFIG_PINCTRL_PFC_R8A77980) += pfc-r8a77980.o
diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c
index f8cbd33b4511be69..e3292abd6c9456f8 100644
--- a/drivers/pinctrl/sh-pfc/core.c
+++ b/drivers/pinctrl/sh-pfc/core.c
@@ -585,10 +585,10 @@ static const struct of_device_id sh_pfc_of_table[] = {
},
#endif /* DEBUG */
#endif
-#ifdef CONFIG_PINCTRL_PFC_R8A7796
+#ifdef CONFIG_PINCTRL_PFC_R8A77960
{
.compatible = "renesas,pfc-r8a7796",
- .data = &r8a7796_pinmux_info,
+ .data = &r8a77960_pinmux_info,
},
#endif
#ifdef CONFIG_PINCTRL_PFC_R8A77965
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
index 3689f769f2eadf93..9de2909c7ad9dff0 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
@@ -6210,8 +6210,8 @@ const struct sh_pfc_soc_info r8a774a1_pinmux_info = {
};
#endif
-#ifdef CONFIG_PINCTRL_PFC_R8A7796
-const struct sh_pfc_soc_info r8a7796_pinmux_info = {
+#ifdef CONFIG_PINCTRL_PFC_R8A77960
+const struct sh_pfc_soc_info r8a77960_pinmux_info = {
.name = "r8a77960_pfc",
.ops = &r8a7796_pinmux_ops,
.unlock_reg = 0xe606, /* PMMR */
diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h
index 12d15b646da4cd1d..a7eb527fdc60ae25 100644
--- a/drivers/pinctrl/sh-pfc/sh_pfc.h
+++ b/drivers/pinctrl/sh-pfc/sh_pfc.h
@@ -320,7 +320,7 @@ extern const struct sh_pfc_soc_info r8a7793_pinmux_info;
extern const struct sh_pfc_soc_info r8a7794_pinmux_info;
extern const struct sh_pfc_soc_info r8a7795_pinmux_info;
extern const struct sh_pfc_soc_info r8a7795es1_pinmux_info;
-extern const struct sh_pfc_soc_info r8a7796_pinmux_info;
+extern const struct sh_pfc_soc_info r8a77960_pinmux_info;
extern const struct sh_pfc_soc_info r8a77965_pinmux_info;
extern const struct sh_pfc_soc_info r8a77970_pinmux_info;
extern const struct sh_pfc_soc_info r8a77980_pinmux_info;
--
2.17.1
[PATCH v2 2/4] dt-bindings: clock: Add r8a77961 CPG Core Clock Definitions
Add all Clock Pulse Generator Core Clock Outputs for the Renesas R-Car
M3-W+ (R8A77961) SoC, as listed in Table 8.2b ("List of Clocks [R-Car
M3-W/R-Car M3-W+]") of the R-Car Series, 3rd Generation Hardware User's
Manual (Rev. 2.00, Jul. 31, 2019). A gap is added for CSIREF, to
preserve compatibility with the definitions for R-Car M3-W (R8A77960).
Note that internal CPG clocks (S0, S1, S2, S3, SDSRC, SSPSRC, and POST2)
are not included, as they are used as internal clock sources only, and
never referenced from DT.
Signed-off-by: Geert Uytterhoeven
Reviewed-by: Yoshihiro Shimoda
---
v2:
- Add Reviewed-by.
---
include/dt-bindings/clock/r8a77961-cpg-mssr.h | 65 +++
1 file changed, 65 insertions(+)
create mode 100644 include/dt-bindings/clock/r8a77961-cpg-mssr.h
diff --git a/include/dt-bindings/clock/r8a77961-cpg-mssr.h
b/include/dt-bindings/clock/r8a77961-cpg-mssr.h
new file mode 100644
index ..7921d785546d12ce
--- /dev/null
+++ b/include/dt-bindings/clock/r8a77961-cpg-mssr.h
@@ -0,0 +1,65 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ * Copyright (C) 2019 Renesas Electronics Corp.
+ */
+#ifndef __DT_BINDINGS_CLOCK_R8A77961_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A77961_CPG_MSSR_H__
+
+#include
+
+/* r8a77961 CPG Core Clocks */
+#define R8A77961_CLK_Z 0
+#define R8A77961_CLK_Z21
+#define R8A77961_CLK_ZR2
+#define R8A77961_CLK_ZG3
+#define R8A77961_CLK_ZTR 4
+#define R8A77961_CLK_ZTRD2 5
+#define R8A77961_CLK_ZT6
+#define R8A77961_CLK_ZX7
+#define R8A77961_CLK_S0D1 8
+#define R8A77961_CLK_S0D2 9
+#define R8A77961_CLK_S0D3 10
+#define R8A77961_CLK_S0D4 11
+#define R8A77961_CLK_S0D6 12
+#define R8A77961_CLK_S0D8 13
+#define R8A77961_CLK_S0D12 14
+#define R8A77961_CLK_S1D1 15
+#define R8A77961_CLK_S1D2 16
+#define R8A77961_CLK_S1D4 17
+#define R8A77961_CLK_S2D1 18
+#define R8A77961_CLK_S2D2 19
+#define R8A77961_CLK_S2D4 20
+#define R8A77961_CLK_S3D1 21
+#define R8A77961_CLK_S3D2 22
+#define R8A77961_CLK_S3D4 23
+#define R8A77961_CLK_LB24
+#define R8A77961_CLK_CL25
+#define R8A77961_CLK_ZB3 26
+#define R8A77961_CLK_ZB3D2 27
+#define R8A77961_CLK_ZB3D4 28
+#define R8A77961_CLK_CR29
+#define R8A77961_CLK_CRD2 30
+#define R8A77961_CLK_SD0H 31
+#define R8A77961_CLK_SD0 32
+#define R8A77961_CLK_SD1H 33
+#define R8A77961_CLK_SD1 34
+#define R8A77961_CLK_SD2H 35
+#define R8A77961_CLK_SD2 36
+#define R8A77961_CLK_SD3H 37
+#define R8A77961_CLK_SD3 38
+#define R8A77961_CLK_SSP2 39
+#define R8A77961_CLK_SSP1 40
+#define R8A77961_CLK_SSPRS 41
+#define R8A77961_CLK_RPC 42
+#define R8A77961_CLK_RPCD2 43
+#define R8A77961_CLK_MSO 44
+#define R8A77961_CLK_CANFD 45
+#define R8A77961_CLK_HDMI 46
+#define R8A77961_CLK_CSI0 47
+/* CLK_CSIREF was removed */
+#define R8A77961_CLK_CP49
+#define R8A77961_CLK_CPEX 50
+#define R8A77961_CLK_R 51
+#define R8A77961_CLK_OSC 52
+
+#endif /* __DT_BINDINGS_CLOCK_R8A77961_CPG_MSSR_H__ */
--
2.17.1
[PATCH v2 1/3] dt-bindings: pinctrl: sh-pfc: Document r8a77961 support
Add DT binding documentation for the Pin Function Controller in the Renesas R-Car M3-W+ (R8A77961) SoC. Update all references to R-Car M3-W from "r8a7796" to "r8a77960", to avoid confusion between R-Car M3-W (R8A77960) and M3-W+. Signed-off-by: Geert Uytterhoeven Reviewed-by: Yoshihiro Shimoda --- v2: - Add Reviewed-by, - Update R-Car M3-W references. --- .../devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt| 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt index c1b9eb4c8696d547..6eada23eaa31e430 100644 --- a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt @@ -28,7 +28,8 @@ Required Properties: - "renesas,pfc-r8a7793": for R8A7793 (R-Car M2-N) compatible pin-controller. - "renesas,pfc-r8a7794": for R8A7794 (R-Car E2) compatible pin-controller. - "renesas,pfc-r8a7795": for R8A7795 (R-Car H3) compatible pin-controller. -- "renesas,pfc-r8a7796": for R8A7796 (R-Car M3-W) compatible pin-controller. +- "renesas,pfc-r8a7796": for R8A77960 (R-Car M3-W) compatible pin-controller. +- "renesas,pfc-r8a77961": for R8A77961 (R-Car M3-W+) compatible pin-controller. - "renesas,pfc-r8a77965": for R8A77965 (R-Car M3-N) compatible pin-controller. - "renesas,pfc-r8a77970": for R8A77970 (R-Car V3M) compatible pin-controller. - "renesas,pfc-r8a77980": for R8A77980 (R-Car V3H) compatible pin-controller. -- 2.17.1
[PATCH v2 0/3] pinctrl: sh-pfc: Add r8a77961 support
Hi all,
This patch series adds support for the Pin Function Controller in the
Renesas R-Car M3-W+ (R8A77961) SoC. As R-Car M3-W+ is very similar to
R-Car M3-W (R8A77960), the existing driver for R-Car M3-W is updated to
handle both.
To avoid confusion between R-Car M3-W and M3-W+, the existing config
symbol for M3-W is renamed to PINCTRL_PFC_R8A77960 in a dependency-free
way, and references to r8a7796 are updated.
Changes compared to v1[1]:
- Split in per-subsystem series,
- Add Reviewed-by, Tested-by,
- Rename PINCTRL_PFC_R8A7796,
- Update r8a7796 references,
I intend to queue this series in sh-pfc-for-v5.5.
Thanks for your comments!
[1] "[PATCH/RFC 00/19] arm64: dts: renesas: Initial support for R-Car M3-W+"
https://lore.kernel.org/linux-renesas-soc/20191007102332.12196-1-geert+rene...@glider.be/
Geert Uytterhoeven (3):
dt-bindings: pinctrl: sh-pfc: Document r8a77961 support
pinctrl: sh-pfc: Rename PINCTRL_PFC_R8A7796 to PINCTRL_PFC_R8A77960
pinctrl: sh-pfc: r8a7796: Add R8A77961 PFC support
.../bindings/pinctrl/renesas,pfc-pinctrl.txt | 3 +-
drivers/pinctrl/sh-pfc/Kconfig| 8 +++--
drivers/pinctrl/sh-pfc/Makefile | 3 +-
drivers/pinctrl/sh-pfc/core.c | 10 --
drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 33 +--
drivers/pinctrl/sh-pfc/sh_pfc.h | 3 +-
6 files changed, 50 insertions(+), 10 deletions(-)
--
2.17.1
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
[PATCH v2 2/5] dt-bindings: arm: renesas: Add Salvator-XS board with R-Car M3-W+
Add device tree binding documentation for the Renesas Salvator-XS board equipped with an R-Car M3-W+ (R8A77961) SoC. Signed-off-by: Geert Uytterhoeven Reviewed-by: Yoshihiro Shimoda --- v2: - Add Reviewed-by, - Add board part number. --- Documentation/devicetree/bindings/arm/renesas.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/arm/renesas.yaml index b78e4e33e7c7ef22..99b290ca418a8a92 100644 --- a/Documentation/devicetree/bindings/arm/renesas.yaml +++ b/Documentation/devicetree/bindings/arm/renesas.yaml @@ -207,6 +207,8 @@ properties: - description: R-Car M3-W+ (R8A77961) items: + - enum: + - renesas,salvator-xs # Salvator-XS (Salvator-X 2nd version, RTP0RC7796SIPB0012SA5A) - const: renesas,r8a77961 - description: Kingfisher (SBEV-RCAR-KF-M03) -- 2.17.1
[PATCH v2 1/4] dt-bindings: clock: renesas: cpg-mssr: Document r8a77961 support
Add DT binding documentation for the Clock Pulse Generator / Module Standby and Software Reset block in the Renesas R-Car M3-W+ (R8A77961) SoC. Update all references to R-Car M3-W from "r8a7796" to "r8a77960", to avoid confusion between R-Car M3-W (R8A77960) and M3-W+. Signed-off-by: Geert Uytterhoeven Reviewed-by: Yoshihiro Shimoda --- v2: - Add Reviewed-by, - Update R-Car M3-W references. --- .../devicetree/bindings/clock/renesas,cpg-mssr.txt| 11 ++- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt index b5edebeb12b40638..d67f57e0dfd22fbe 100644 --- a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt +++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt @@ -27,7 +27,8 @@ Required Properties: - "renesas,r8a7793-cpg-mssr" for the r8a7793 SoC (R-Car M2-N) - "renesas,r8a7794-cpg-mssr" for the r8a7794 SoC (R-Car E2) - "renesas,r8a7795-cpg-mssr" for the r8a7795 SoC (R-Car H3) - - "renesas,r8a7796-cpg-mssr" for the r8a7796 SoC (R-Car M3-W) + - "renesas,r8a7796-cpg-mssr" for the r8a77960 SoC (R-Car M3-W) + - "renesas,r8a77961-cpg-mssr" for the r8a77961 SoC (R-Car M3-W+) - "renesas,r8a77965-cpg-mssr" for the r8a77965 SoC (R-Car M3-N) - "renesas,r8a77970-cpg-mssr" for the r8a77970 SoC (R-Car V3M) - "renesas,r8a77980-cpg-mssr" for the r8a77980 SoC (R-Car V3H) @@ -42,10 +43,10 @@ Required Properties: - clock-names: List of external parent clock names. Valid names are: - "extal" (r7s9210, r8a7743, r8a7744, r8a7745, r8a77470, r8a774a1, r8a774b1, r8a774c0, r8a7790, r8a7791, r8a7792, r8a7793, -r8a7794, r8a7795, r8a7796, r8a77965, r8a77970, r8a77980, -r8a77990, r8a77995) - - "extalr" (r8a774a1, r8a774b1, r8a7795, r8a7796, r8a77965, r8a77970, - r8a77980) +r8a7794, r8a7795, r8a77960, r8a77961, r8a77965, r8a77970, +r8a77980, r8a77990, r8a77995) + - "extalr" (r8a774a1, r8a774b1, r8a7795, r8a77960, r8a77961, r8a77965, + r8a77970, r8a77980) - "usb_extal" (r8a7743, r8a7744, r8a7745, r8a77470, r8a7790, r8a7791, r8a7793, r8a7794) -- 2.17.1
[PATCH v2 4/4] clk: renesas: r8a7796: Add R8A77961 CPG/MSSR support
Add support for the R-Car M3-W+ (R8A77961) SoC to the Renesas Clock
Pulse Generator / Module Standby and Software Reset driver.
R-Car M3-W+ is very similar to R-Car M3-W (R8A77960), which allows for
both SoCs to share a driver. R-Car M3-W+ lacks a few modules, so their
clocks must be nullified.
Based on a patch in the BSP by Takeshi Kihara
.
Signed-off-by: Geert Uytterhoeven
Reviewed-by: Yoshihiro Shimoda
Tested-by: Yoshihiro Shimoda
---
v2:
- Add Reviewed-by, Tested-by,
- Add "R-Car M3-W/W+" comment at the top of r8a7796-cpg-mssr.c.
---
drivers/clk/renesas/Kconfig| 5 +
drivers/clk/renesas/Makefile | 1 +
drivers/clk/renesas/r8a7796-cpg-mssr.c | 24
drivers/clk/renesas/renesas-cpg-mssr.c | 6 ++
4 files changed, 32 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig
index a48f75ec1400c090..4cd846bc98cc2ec0 100644
--- a/drivers/clk/renesas/Kconfig
+++ b/drivers/clk/renesas/Kconfig
@@ -22,6 +22,7 @@ config CLK_RENESAS
select CLK_R8A7794 if ARCH_R8A7794
select CLK_R8A7795 if ARCH_R8A7795
select CLK_R8A77960 if ARCH_R8A77960 || ARCH_R8A7796
+ select CLK_R8A77961 if ARCH_R8A77961
select CLK_R8A77965 if ARCH_R8A77965
select CLK_R8A77970 if ARCH_R8A77970
select CLK_R8A77980 if ARCH_R8A77980
@@ -113,6 +114,10 @@ config CLK_R8A77960
bool "R-Car M3-W clock support" if COMPILE_TEST
select CLK_RCAR_GEN3_CPG
+config CLK_R8A77961
+ bool "R-Car M3-W+ clock support" if COMPILE_TEST
+ select CLK_RCAR_GEN3_CPG
+
config CLK_R8A77965
bool "R-Car M3-N clock support" if COMPILE_TEST
select CLK_RCAR_GEN3_CPG
diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile
index 58211d0f04bf4d4b..4a722bc5aac755c8 100644
--- a/drivers/clk/renesas/Makefile
+++ b/drivers/clk/renesas/Makefile
@@ -19,6 +19,7 @@ obj-$(CONFIG_CLK_R8A7792) += r8a7792-cpg-mssr.o
obj-$(CONFIG_CLK_R8A7794) += r8a7794-cpg-mssr.o
obj-$(CONFIG_CLK_R8A7795) += r8a7795-cpg-mssr.o
obj-$(CONFIG_CLK_R8A77960) += r8a7796-cpg-mssr.o
+obj-$(CONFIG_CLK_R8A77961) += r8a7796-cpg-mssr.o
obj-$(CONFIG_CLK_R8A77965) += r8a77965-cpg-mssr.o
obj-$(CONFIG_CLK_R8A77970) += r8a77970-cpg-mssr.o
obj-$(CONFIG_CLK_R8A77980) += r8a77980-cpg-mssr.o
diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c
b/drivers/clk/renesas/r8a7796-cpg-mssr.c
index 90cc6a1026028fa8..e8420d3ada94ca45 100644
--- a/drivers/clk/renesas/r8a7796-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c
@@ -1,9 +1,10 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * r8a7796 Clock Pulse Generator / Module Standby and Software Reset
+ * r8a7796 (R-Car M3-W/W+) Clock Pulse Generator / Module Standby and Software
+ * Reset
*
- * Copyright (C) 2016 Glider bvba
- * Copyright (C) 2018 Renesas Electronics Corp.
+ * Copyright (C) 2016-2019 Glider bvba
+ * Copyright (C) 2018-2019 Renesas Electronics Corp.
*
* Based on r8a7795-cpg-mssr.c
*
@@ -14,6 +15,7 @@
#include
#include
#include
+#include
#include
#include
@@ -116,7 +118,7 @@ static const struct cpg_core_clk r8a7796_core_clks[]
__initconst = {
DEF_BASE("r", R8A7796_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
};
-static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = {
+static struct mssr_mod_clk r8a7796_mod_clks[] __initdata = {
DEF_MOD("fdp1-0",119, R8A7796_CLK_S0D1),
DEF_MOD("scif5", 202, R8A7796_CLK_S3D4),
DEF_MOD("scif4", 203, R8A7796_CLK_S3D4),
@@ -304,6 +306,14 @@ static const struct rcar_gen3_cpg_pll_config
cpg_pll_configs[16] __initconst = {
{ 2,192,1, 192,1, 32, },
};
+ /*
+* Fixups for R-Car M3-W+
+*/
+
+static const unsigned int r8a77961_mod_nullify[] __initconst = {
+ MOD_CLK_ID(617),/* FCPCI0 */
+};
+
static int __init r8a7796_cpg_mssr_init(struct device *dev)
{
const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
@@ -320,6 +330,12 @@ static int __init r8a7796_cpg_mssr_init(struct device *dev)
return -EINVAL;
}
+ if (of_device_is_compatible(dev->of_node, "renesas,r8a77961-cpg-mssr"))
+ mssr_mod_nullify(r8a7796_mod_clks,
+ARRAY_SIZE(r8a7796_mod_clks),
+r8a77961_mod_nullify,
+ARRAY_SIZE(r8a77961_mod_nullify));
+
return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode);
}
diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c
b/drivers/clk/renesas/renesas-cpg-mssr.c
index c2f96e63498e14cc..a2663fbbd7a51067 100644
--- a/drivers/clk/renesas/renesas-cpg
[PATCH v2 3/4] clk: renesas: Rename CLK_R8A7796 to CLK_R8A77960
Rename CONFIG_CLK_R8A7796 for R-Car M3-W (R8A77960) to
CONFIG_CLK_R8A77960, to avoid confusion with R-Car M3-W+ (R8A77961),
which will use CONFIG_CLK_R8A77961.
Extend the dependency of CONFIG_CLK_R8A77960 from CONFIG_ARCH_R8A7796 to
CONFIG_ARCH_R8A77960, to relax dependencies for a future rename of the
SoC configuration symbol.
Signed-off-by: Geert Uytterhoeven
---
v2:
- New.
---
drivers/clk/renesas/Kconfig| 4 ++--
drivers/clk/renesas/Makefile | 2 +-
drivers/clk/renesas/renesas-cpg-mssr.c | 2 +-
3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig
index be03bb74801252bc..a48f75ec1400c090 100644
--- a/drivers/clk/renesas/Kconfig
+++ b/drivers/clk/renesas/Kconfig
@@ -21,7 +21,7 @@ config CLK_RENESAS
select CLK_R8A7792 if ARCH_R8A7792
select CLK_R8A7794 if ARCH_R8A7794
select CLK_R8A7795 if ARCH_R8A7795
- select CLK_R8A7796 if ARCH_R8A7796
+ select CLK_R8A77960 if ARCH_R8A77960 || ARCH_R8A7796
select CLK_R8A77965 if ARCH_R8A77965
select CLK_R8A77970 if ARCH_R8A77970
select CLK_R8A77980 if ARCH_R8A77980
@@ -109,7 +109,7 @@ config CLK_R8A7795
bool "R-Car H3 clock support" if COMPILE_TEST
select CLK_RCAR_GEN3_CPG
-config CLK_R8A7796
+config CLK_R8A77960
bool "R-Car M3-W clock support" if COMPILE_TEST
select CLK_RCAR_GEN3_CPG
diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile
index ef0fdd00d2b741b2..58211d0f04bf4d4b 100644
--- a/drivers/clk/renesas/Makefile
+++ b/drivers/clk/renesas/Makefile
@@ -18,7 +18,7 @@ obj-$(CONFIG_CLK_R8A7791) += r8a7791-cpg-mssr.o
obj-$(CONFIG_CLK_R8A7792) += r8a7792-cpg-mssr.o
obj-$(CONFIG_CLK_R8A7794) += r8a7794-cpg-mssr.o
obj-$(CONFIG_CLK_R8A7795) += r8a7795-cpg-mssr.o
-obj-$(CONFIG_CLK_R8A7796) += r8a7796-cpg-mssr.o
+obj-$(CONFIG_CLK_R8A77960) += r8a7796-cpg-mssr.o
obj-$(CONFIG_CLK_R8A77965) += r8a77965-cpg-mssr.o
obj-$(CONFIG_CLK_R8A77970) += r8a77970-cpg-mssr.o
obj-$(CONFIG_CLK_R8A77980) += r8a77980-cpg-mssr.o
diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c
b/drivers/clk/renesas/renesas-cpg-mssr.c
index 35966678148e2c8b..c2f96e63498e14cc 100644
--- a/drivers/clk/renesas/renesas-cpg-mssr.c
+++ b/drivers/clk/renesas/renesas-cpg-mssr.c
@@ -749,7 +749,7 @@ static const struct of_device_id cpg_mssr_match[] = {
.data = &r8a7795_cpg_mssr_info,
},
#endif
-#ifdef CONFIG_CLK_R8A7796
+#ifdef CONFIG_CLK_R8A77960
{
.compatible = "renesas,r8a7796-cpg-mssr",
.data = &r8a7796_cpg_mssr_info,
--
2.17.1
[PATCH v2 0/5] dt-bindings: arm: renesas: Add core r8a77961 support
Hi all,
This patch series updates the Renesas DT binding documentation for core
components on the new R-Car M3-W+ (R8A77961) SoC, and for the
Salvator-XS development board equipped with this SoC.
Changes compared to v1[1]:
- Split in per-subsystem series,
- Add Reviewed-by,
- Add board part number.
I intend to queue this series in renesas-devel for v5.5.
The last patch will be put on a branch shared between driver and DTS.
Thanks for your comments!
[1] "[PATCH/RFC 00/19] arm64: dts: renesas: Initial support for R-Car M3-W+"
https://lore.kernel.org/linux-renesas-soc/20191007102332.12196-1-geert+rene...@glider.be/
Geert Uytterhoeven (5):
dt-bindings: arm: renesas: Document R-Car M3-W+ SoC DT bindings
dt-bindings: arm: renesas: Add Salvator-XS board with R-Car M3-W+
dt-bindings: reset: rcar-rst: Document r8a77961 support
dt-bindings: power: rcar-sysc: Document r8a77961 support
dt-bindings: power: Add r8a77961 SYSC power domain definitions
.../devicetree/bindings/arm/renesas.yaml | 6
.../bindings/power/renesas,rcar-sysc.txt | 1 +
.../devicetree/bindings/reset/renesas,rst.txt | 1 +
include/dt-bindings/power/r8a77961-sysc.h | 32 +++
4 files changed, 40 insertions(+)
create mode 100644 include/dt-bindings/power/r8a77961-sysc.h
--
2.17.1
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
[PATCH v2 5/5] dt-bindings: power: Add r8a77961 SYSC power domain definitions
Add power domain indices for the R-Car M3-W+ (R8A77961) SoC. Based on Rev. 2.00 of the R-Car Series, 3rd Generation, Hardware User’s Manual (Jul. 31, 2019). Signed-off-by: Geert Uytterhoeven Reviewed-by: Yoshihiro Shimoda --- v2: - Add Reviewed-by. --- include/dt-bindings/power/r8a77961-sysc.h | 32 +++ 1 file changed, 32 insertions(+) create mode 100644 include/dt-bindings/power/r8a77961-sysc.h diff --git a/include/dt-bindings/power/r8a77961-sysc.h b/include/dt-bindings/power/r8a77961-sysc.h new file mode 100644 index ..7a3800996f7c0252 --- /dev/null +++ b/include/dt-bindings/power/r8a77961-sysc.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2019 Glider bvba + */ +#ifndef __DT_BINDINGS_POWER_R8A77961_SYSC_H__ +#define __DT_BINDINGS_POWER_R8A77961_SYSC_H__ + +/* + * These power domain indices match the numbers of the interrupt bits + * representing the power areas in the various Interrupt Registers + * (e.g. SYSCISR, Interrupt Status Register) + */ + +#define R8A77961_PD_CA57_CPU0 0 +#define R8A77961_PD_CA57_CPU1 1 +#define R8A77961_PD_CA53_CPU0 5 +#define R8A77961_PD_CA53_CPU1 6 +#define R8A77961_PD_CA53_CPU2 7 +#define R8A77961_PD_CA53_CPU3 8 +#define R8A77961_PD_CA57_SCU 12 +#define R8A77961_PD_CR713 +#define R8A77961_PD_A3VC 14 +#define R8A77961_PD_3DG_A 17 +#define R8A77961_PD_3DG_B 18 +#define R8A77961_PD_CA53_SCU 21 +#define R8A77961_PD_A3IR 24 +#define R8A77961_PD_A2VC1 26 + +/* Always-on power area */ +#define R8A77961_PD_ALWAYS_ON 32 + +#endif /* __DT_BINDINGS_POWER_R8A77961_SYSC_H__ */ -- 2.17.1
[PATCH v2 4/5] dt-bindings: power: rcar-sysc: Document r8a77961 support
Add DT binding documentation for the System Controller in the Renesas R-Car M3-W+ (R8A77961) SoC. Signed-off-by: Geert Uytterhoeven Reviewed-by: Yoshihiro Shimoda --- v2: - Add Reviewed-by. --- Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt b/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt index 712caa5726f7cb91..acb41fade926e2de 100644 --- a/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt +++ b/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt @@ -22,6 +22,7 @@ Required properties: - "renesas,r8a7794-sysc" (R-Car E2) - "renesas,r8a7795-sysc" (R-Car H3) - "renesas,r8a7796-sysc" (R-Car M3-W) + - "renesas,r8a77961-sysc" (R-Car M3-W+) - "renesas,r8a77965-sysc" (R-Car M3-N) - "renesas,r8a77970-sysc" (R-Car V3M) - "renesas,r8a77980-sysc" (R-Car V3H) -- 2.17.1
[PATCH v2 1/5] dt-bindings: arm: renesas: Document R-Car M3-W+ SoC DT bindings
Add device tree binding documentation for the Renesas R-Car M3-W+ (R8A77961) SoC. Signed-off-by: Geert Uytterhoeven Reviewed-by: Yoshihiro Shimoda --- v2: - Add Reviewed-by. --- Documentation/devicetree/bindings/arm/renesas.yaml | 4 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/arm/renesas.yaml index bc0b4ec54756d6ae..b78e4e33e7c7ef22 100644 --- a/Documentation/devicetree/bindings/arm/renesas.yaml +++ b/Documentation/devicetree/bindings/arm/renesas.yaml @@ -205,6 +205,10 @@ properties: - renesas,salvator-xs # Salvator-XS (Salvator-X 2nd version, RTP0RC7796SIPB0012S) - const: renesas,r8a7796 + - description: R-Car M3-W+ (R8A77961) +items: + - const: renesas,r8a77961 + - description: Kingfisher (SBEV-RCAR-KF-M03) items: - const: shimafuji,kingfisher -- 2.17.1
Re: [PATCH 2/2] arm64: dts: renesas: r8a774b1: Add SATA controller node
On Tue, Oct 22, 2019 at 6:21 PM Fabrizio Castro
wrote:
> Add the SATA controller node to the RZ/G2N SoC specific
> dtsi.
>
> Signed-off-by: Fabrizio Castro
Reviewed-by: Geert Uytterhoeven
i.e. will queue in renesas-devel for v5.5.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Re: [PATCH 1/2] ata: sata_rcar: Add r8a774b1 support
dt-bindings: ?
On Tue, Oct 22, 2019 at 6:21 PM Fabrizio Castro
wrote:
> Document SATA support for the RZ/G2N, no driver change required.
>
> Signed-off-by: Fabrizio Castro
Reviewed-by: Geert Uytterhoeven
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Re: [PATCH] arm64: dts: renesas: r8a774b1: Add VIN and CSI-2 support
On Tue, Oct 15, 2019 at 1:01 PM Biju Das wrote:
> Add VIN and CSI-2 support to the RZ/G2N SoC specific dtsi.
>
> Signed-off-by: Biju Das
Reviewed-by: Geert Uytterhoeven
i.e. will queue in renesas-devel for v5.5.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Re: [PATCH v2 0/8] clk: renesas: rcar-gen2/gen3: Switch to .determine_rate()
Hi Stephen,
On Wed, Sep 11, 2019 at 6:24 PM Stephen Boyd wrote:
> Quoting Geert Uytterhoeven (2019-09-03 23:51:10)
> > On Wed, Sep 4, 2019 at 12:09 AM Stephen Boyd wrote:
> > > Quoting Geert Uytterhoeven (2019-08-30 06:45:07)
> > > > As the .round_rate() callback returns a long clock rate, it cannot
> > > > return clock rates that do not fit in signed long, but do fit in
> > > > unsigned long. The newer .determine_rate() callback does not suffer
> > > > from this limitation. In addition, .determine_rate() provides the
> > > > ability to specify a rate range.
> > > >
> > > > This patch series performs the customary preparatory cleanups, and
> > > > switches the Z (CPU) and SD clocks in the R-Car Gen2 and Gen3 clock
> > > > drivers from the .round_rate() to the .determine_rate() callback.
> > > > Note that the "div6" clock driver hasn't been converted yet, so div6
> > > > clocks still use .round_rate().
> > > >
> > > > Changes compared to v1[1]:
> > > > - Add preparatory arithmetic division improvements
> > > > - Split off cpg_sd_clock_calc_div() absorption and SD clock best rate
> > > > calculation,
> > > > - Use div_u64() for division by unsigned long,
> > > >
> > > > This has been tested on R-Car M2-W and various R-Car Gen3, and should
> > > > have no behavioral impact.
> > >
> > > From what I recall the rate range code is broken but I can't remember
> > > how. Anyway, I was just curious if you ran into any issues with that
> > > code.
> >
> > I didn't ran into any issues. But please note that in all tested cases, the
> > limits were 0 and ULONG_MAX anyway, so probably it didn't trigger the
> > broken cases in the rate range code.
> >
> > So, is it good to have .determine_rate() support in individual clock drivers
> > now, or do you want me to postpone the last 3 patches of my series until the
> > rate range code is fixed?
> >
>
> It's fine to use .determine_rate() because we'll fix the problems in the
> clk framework. So no concern from me here. Just curious if you ran into
> any problems.
Thanks, queued in clk-renesas-for-v5.5.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Re: [PATCH V3 2/3] PCI: rcar: Do not abort on too many inbound dma-ranges
t;>>> In short, what's the benefit of adding more dma-ranges regions to
> >>>>>>> the
> >>>>>>> DT (and consequently handling them in the kernel) ?
> >>>>>>
> >>>>>> The benefit is programming the controller inbound windows correctly.
> >>>>>> But if there is a better way to do that, I am open to implement that.
> >>>>>> Are there any suggestions / examples of that ?
> >>>>>
> >>>>> The crucial thing is that once we improve the existing "dma-ranges"
> >>>>> handling in the DMA layer such that it *does* consider multiple
> >>>>> entries
> >>>>> properly, platforms presenting ranges which don't actually exist will
> >>>>> almost certainly start going wrong, and are either going to have to
> >>>>> fix
> >>>>> their broken bootloaders or try to make a case for platform-specific
> >>>>> workarounds in core code.
> >>>> Again, this is exactly the other way around, the dma-ranges
> >>>> populated by
> >>>> U-Boot cover only existing DRAM. The single dma-range in Linux DT
> >>>> covers
> >>>> even the holes without existing DRAM.
> >>>>
> >>>> So even if the Linux dma-ranges handling changes, there should be no
> >>>> problem.
> >>>
> >>> Say you have a single hardware window, and this DT property (1-cell
> >>> numbers for simplicity:
> >>>
> >>> dma-ranges = <0x 0x 0x8000>;
> >>>
> >>> Driver reads one entry and programs the window to 2GB@0, DMA setup
> >>> parses the first entry and sets device masks to 0x7fff, and
> >>> everything's fine.
> >>>
> >>> Now say we describe the exact same address range this way instead:
> >>>
> >>> dma-ranges = <0x 0x 0x4000,
> >>>0x4000 0x4000 0x4000>;
> >>>
> >>> Driver reads one entry and programs the window to 1GB@0, DMA setup
> >>> parses the first entry and sets device masks to 0x3fff, and *today*,
> >>> things are suboptimal but happen to work.
> >>>
> >>> Now say we finally get round to fixing the of_dma code to properly
> >>> generate DMA masks that actually include all usable address bits, a user
> >>> upgrades their kernel package, and reboots with that same DT...
> >>>
> >>> Driver reads one entry and programs the window to 1GB@0, DMA setup
> >>> parses all entries and sets device masks to 0x7fff, devices start
> >>> randomly failing or throwing DMA errors half the time, angry user looks
> >>> at the changelog to find that somebody decided their now-corrupted
> >>> filesystem is less important than the fact that hey, at least the
> >>> machine didn't refuse to boot because the DT was obviously wrong. Are
> >>> you sure that shouldn't be a problem?
> >>
> >> I think you picked a rather special case here and arrived as a DMA mask
> >> which just fails in this special case. Such special case doesn't happen
> >> here, and even if it did, I would expect Linux to merge those two ranges
> >> or do something sane ? If the DMA mask is set incorrectly, that's a bug
> >> of the DMA code I would think.
> >
> > The mask is not set incorrectly - DMA masks represent the number of
> > address bits the device (or intermediate interconnect in the case of the
> > bus mask) is capable of driving. Thus when DMA is limited to a specific
> > address range, the masks should be wide enough to cover the topmost
> > address of that range (unless the device's own capability is inherently
> > narrower).
>
> Then the mask should be 0x7fff in both cases I'd say.
>
> >> What DMA mask would you get if those two entries had a gap inbetween
> >> them ? E.g.:
> >>
> >> dma-ranges = <0x 0x 0x2000,
> >> 0x4000 0x4000 0x2000>;
> >
> > OK, here's an real non-simplified example
>
> I would really like an answer to the simple example above before we
> start inventing convoluted ones.
I'd say that depends on the actual memory configuration, i.e. does memory
exist in the gap? Does memory exist above 0x5fff?
BTW, reading Devicetree Specification, Release v0.2: dma-ranges
describes bus address space translation; it does not describe if the
full address space is backed by physical RAM (see the /memory node).
Hence if there's no memory in the gap, I see no reason to have 2 entries
in dma-ranges, as the translation offsets are the same, so they could be
covered by a single larger entry.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
[PULL 3/5] Renesas ARM64 DT updates for v5.5
The following changes since commit 54ecb8f7028c5eb3d740bb82b0f1d90f2df63c5c: Linux 5.4-rc1 (2019-09-30 10:35:40 -0700) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel.git tags/renesas-arm64-dt-for-v5.5-tag1 for you to fetch changes up to 3fa08cbb0662acc6cbd1a481956570a52dba8875: arm64: dts: renesas: r8a774b1: Add CAN and CAN FD support (2019-10-14 12:04:59 +0200) Renesas ARM64 DT updates for v5.5 - Support for the RZ/G2N (r8a774b1) SoC and the HiHope RZ/G2N board, - CPU idle support for R-Car H3 and M3-W, - LVDS and backlight support on the HiHope RZ/G2M and RZ/G2N boards, with Advantech idk-1110wr LVDS panel, - Minor fixes and improvements. Biju Das (34): dt-bindings: power: Add r8a774b1 SYSC power domain definitions dt-bindings: clk: Add r8a774b1 CPG Core Clock Definitions arm64: dts: renesas: r8a774c0: Create thermal zone to support IPA arm64: dts: renesas: r8a774c0: Add dynamic power coefficient arm64: dts: renesas: Initial r8a774b1 SoC device tree arm64: dts: renesas: Add HiHope RZ/G2N main board support arm64: dts: renesas: r8a774a1: Remove audio port node arm64: dts: renesas: r8a774b1-hihope-rzg2n: Enable HS400 mode arm64: dts: renesas: r8a774b1: Add SYS-DMAC device nodes arm64: dts: renesas: r8a774b1: Add SCIF and HSCIF nodes arm64: dts: renesas: r8a774b1: Add GPIO device nodes arm64: dts: renesas: r8a774b1: Add Ethernet AVB node arm64: dts: renesas: Add HiHope RZ/G2N sub board support arm64: dts: renesas: r8a774b1: Add OPPs table for cpu devices arm64: dts: renesas: r8a774b1: Add RZ/G2N thermal support arm64: dts: renesas: r8a774b1: Add CMT device nodes arm64: dts: renesas: r8a774b1: Add TMU device nodes arm64: dts: renesas: r8a774b1: Add SDHI support arm64: dts: renesas: r8a774b1: Add I2C and IIC-DVFS support arm64: dts: renesas: r8a774b1: Add IPMMU device nodes arm64: dts: renesas: r8a774b1: Add FCPF and FCPV instances arm64: dts: renesas: r8a774b1: Add VSP instances arm64: dts: renesas: r8a774b1: Tie SYS-DMAC to IPMMU-DS0/1 arm64: dts: renesas: r8a774b1: Connect Ethernet-AVB to IPMMU-DS0 arm64: dts: renesas: hihope-common: Move du clk properties out of common dtsi arm64: dts: renesas: r8a774b1: Add DU device to DT arm64: dts: renesas: r8a774b1: Add HDMI encoder instance arm64: dts: renesas: r8a774b1-hihope-rzg2n: Add display clock properties arm64: dts: renesas: r8a774b1: Add FDP1 device nodes arm64: dts: renesas: r8a774b1: Add PWM device nodes arm64: dts: renesas: hihope-rzg2-ex: Enable backlight arm64: dts: renesas: hihope-rzg2-ex: Add LVDS support arm64: dts: renesas: Add support for Advantech idk-1110wr LVDS panel arm64: dts: renesas: r8a774b1: Add Sound and Audio DMAC device nodes Dien Pham (2): arm64: dts: r8a7795: Add cpuidle support for CA53 cores arm64: dts: r8a7796: Add cpuidle support for CA53 cores Fabrizio Castro (9): arm64: dts: renesas: r8a774b1: Add RWDT node arm64: dts: renesas: r8a774b1: Add all MSIOF nodes arm64: dts: renesas: r8a774b1: Add PCIe device nodes arm64: dts: renesas: hihope-rzg2-ex: Let the board specific DT decide about pciec1 arm64: dts: renesas: r8a774b1: Add USB2.0 phy and host (EHCI/OHCI) device nodes arm64: dts: renesas: r8a774b1: Add USB-DMAC and HSUSB device nodes arm64: dts: renesas: r8a774b1: Add USB3.0 device nodes arm64: dts: renesas: r8a774b1: Add INTC-EX device node arm64: dts: renesas: r8a774b1: Add CAN and CAN FD support Jacopo Mondi (1): arm64: dts: renesas: Add LIF channel indices to vsps properties Khiem Nguyen (2): arm64: dts: r8a7795: Add cpuidle support for CA57 cores arm64: dts: r8a7796: Add cpuidle support for CA57 cores Kieran Bingham (1): arm64: dts: renesas: r8a77970: Fix PWM3 Yoshihiro Shimoda (1): arm64: dts: renesas: Add iommus to R-Car Gen3 SDHI/MMC nodes arch/arm64/boot/dts/renesas/Makefile |2 + arch/arm64/boot/dts/renesas/hihope-common.dtsi | 28 +- arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi| 51 +- .../boot/dts/renesas/r8a774a1-hihope-rzg2m-ex.dts |4 + .../boot/dts/renesas/r8a774a1-hihope-rzg2m.dts | 11 + arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 13 +- .../boot/dts/renesas/r8a774b1-hihope-rzg2n-ex.dts | 15 + .../boot/dts/renesas/r8a774b1-hihope-rzg2n.dts | 41 + arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 2250 arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 20 +- arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi |2 +- arch/arm64/boot/dts/renesas/r8a7795.dtsi | 34 + arch/arm64/boot/dts/
[GIT PULL] clk: renesas: Updates for v5.5
Hi Mike, Stephen,
The following changes since commit 54ecb8f7028c5eb3d740bb82b0f1d90f2df63c5c:
Linux 5.4-rc1 (2019-09-30 10:35:40 -0700)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git
tags/clk-renesas-for-v5.5-tag1
for you to fetch changes up to 56278c8fcb71874d591907d654272d511ce3597c:
clk: renesas: r8a774b1: Add TMU clock (2019-10-07 14:29:53 +0200)
clk: renesas: Updates for v5.5
- Add support for the new RZ/G2N (r8a774b1) SoC,
- Remove R-Car Gen2 legacy DT clock support,
- Improve arithmetic divisions on R-Car Gen2 and Gen3,
- Improve R-Car Gen3 SD clock handling,
- Minor cleanups.
Note that the new Renesas RZ/G2N DT Binding Definitions are shared by
driver and DT source files, and thus included in 3 pull requests:
- "[GIT PULL] clk: renesas: Updates for v5.5] (for clk),
- "[GIT PULL 3/5] Renesas ARM64 DT updates for v5.5" (for arm-soc),
- "[GIT PULL 4/5] Renesas driver updates for v5.5" (for arm-soc).
If you prefer to merge this dependency explicitly, please pull tag
renesas-r8a774b1-dt-binding-defs-tag first.
Thanks for pulling!
Biju Das (5):
dt-bindings: power: Add r8a774b1 SYSC power domain definitions
dt-bindings: clk: Add r8a774b1 CPG Core Clock Definitions
dt-bindings: clock: renesas: cpg-mssr: Document r8a774b1 binding
clk: renesas: cpg-mssr: Add r8a774b1 support
clk: renesas: r8a774b1: Add TMU clock
Geert Uytterhoeven (6):
clk: renesas: Remove R-Car Gen2 legacy DT clock support
clk: renesas: rcar-gen2: Improve arithmetic divisions
clk: renesas: rcar-gen3: Improve arithmetic divisions
clk: renesas: rcar-gen3: Avoid double table iteration in SD .set_rate()
clk: renesas: rcar-gen3: Absorb cpg_sd_clock_calc_div()
clk: renesas: rcar-gen3: Loop to find best rate in
cpg_sd_clock_round_rate()
Markus Elfring (1):
clk: renesas: mstp: Delete unnecessary kfree() in cpg_mstp_clocks_init()
.../devicetree/bindings/clock/renesas,cpg-mssr.txt | 10 +-
drivers/clk/renesas/Kconfig| 25 +-
drivers/clk/renesas/Makefile | 2 +-
drivers/clk/renesas/clk-mstp.c | 4 +-
drivers/clk/renesas/clk-rcar-gen2.c| 457 -
drivers/clk/renesas/r8a774b1-cpg-mssr.c| 327 +++
drivers/clk/renesas/rcar-gen2-cpg.c| 6 +-
drivers/clk/renesas/rcar-gen3-cpg.c| 37 +-
drivers/clk/renesas/renesas-cpg-mssr.c | 6 +
drivers/clk/renesas/renesas-cpg-mssr.h | 1 +
include/dt-bindings/clock/r8a774b1-cpg-mssr.h | 57 +++
include/dt-bindings/power/r8a774b1-sysc.h | 26 ++
12 files changed, 449 insertions(+), 509 deletions(-)
delete mode 100644 drivers/clk/renesas/clk-rcar-gen2.c
create mode 100644 drivers/clk/renesas/r8a774b1-cpg-mssr.c
create mode 100644 include/dt-bindings/clock/r8a774b1-cpg-mssr.h
create mode 100644 include/dt-bindings/power/r8a774b1-sysc.h
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
[PULL 1/5] Renesas ARM DT updates for v5.5
The following changes since commit 54ecb8f7028c5eb3d740bb82b0f1d90f2df63c5c: Linux 5.4-rc1 (2019-09-30 10:35:40 -0700) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel.git tags/renesas-arm-dt-for-v5.5-tag1 for you to fetch changes up to 84cd9d3442b755b804618b265d39ab99df829ab2: ARM: dts: emev2: Add whitespace for GPIO nodes (2019-10-01 09:51:42 +0200) Renesas ARM DT updates for v5.5 - Whitespace cleanups. Geert Uytterhoeven (2): ARM: dts: gose: Replace spaces by TABs ARM: dts: lager: Replace spaces by TABs Magnus Damm (1): ARM: dts: emev2: Add whitespace for GPIO nodes arch/arm/boot/dts/emev2.dtsi| 4 ++ arch/arm/boot/dts/r8a7790-lager.dts | 8 +-- arch/arm/boot/dts/r8a7793-gose.dts | 110 ++-- 3 files changed, 63 insertions(+), 59 deletions(-)
[GIT PULL 0/5] Renesas SoC updates for v5.5
Hi arm-soc folks,
This is my first pull request for the inclusion of Renesas SoC updates
for v5.5.
It consists of 5 parts:
[GIT PULL 1/5] Renesas ARM DT updates for v5.5
- Whitespace cleanups.
[GIT PULL 2/5] Renesas ARM64 defconfig updates for v5.5
- Enable support for the new RZ/G2N (r8a774b1) SoC.
[GIT PULL 3/5] Renesas ARM64 DT updates for v5.5
- Support for the RZ/G2N (r8a774b1) SoC and the HiHope RZ/G2N board,
- CPU idle support for R-Car H3 and M3-W,
- LVDS and backlight support on the HiHope RZ/G2M and RZ/G2N boards,
with Advantech idk-1110wr LVDS panel,
- Minor fixes and improvements.
[GIT PULL 4/5] Renesas driver updates for v5.5
- Add support for the new RZ/G2N (r8a774b1) SoC,
- Fix System Controller power request conflicts on recent R-Car Gen3
and RZ/G2N SoC variants and revisions,
- Minor cleanups.
[GIT PULL 5/5] Renesas DT binding updates for v5.5
- RZ/G2M update for the Renesas Timer Unit bindings,
- Support for the new RZ/G2N (r8a774b1) SoC and the HiHope RZ/G2N
board.
Note that the new Renesas RZ/G2N DT Binding Definitions are shared by
driver and DT source files, and thus included in 3 pull requests:
- "[GIT PULL 3/5] Renesas ARM64 DT updates for v5.5" (for arm-soc),
- "[GIT PULL 4/5] Renesas driver updates for v5.5" (for arm-soc).
- "[GIT PULL] clk: renesas: Updates for v5.5] (for clk).
If you prefer to merge this dependency explicitly, please pull tag
renesas-r8a774b1-dt-binding-defs-tag first.
Thanks for pulling!
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
[PULL 2/5] Renesas ARM64 defconfig updates for v5.5
The following changes since commit 54ecb8f7028c5eb3d740bb82b0f1d90f2df63c5c: Linux 5.4-rc1 (2019-09-30 10:35:40 -0700) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel.git tags/renesas-arm64-defconfig-for-v5.5-tag1 for you to fetch changes up to d8b178741e5ba571fbcc187c9e3cf9c0eaebf328: arm64: defconfig: Enable R8A774B1 SoC (2019-10-01 09:51:58 +0200) Renesas ARM64 defconfig updates for v5.5 - Enable support for the new RZ/G2N (r8a774b1) SoC. Biju Das (1): arm64: defconfig: Enable R8A774B1 SoC arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+)
[GIT PULL] pinctrl: sh-pfc: Updates for v5.5
Hi Linus,
The following changes since commit 54ecb8f7028c5eb3d740bb82b0f1d90f2df63c5c:
Linux 5.4-rc1 (2019-09-30 10:35:40 -0700)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git
tags/sh-pfc-for-v5.5-tag1
for you to fetch changes up to f846d1e704f2d07a7f359f65eac2c8cac565db35:
pinctrl: sh-pfc: pfc-r8a77965: Fix typo in pinmux macro for SCL3 (2019-10-14
12:11:12 +0200)
pinctrl: sh-pfc: Updates for v5.5
- Add support for the new RZ/G2N (r8a774b1) SoC,
- Small fixes and cleanups.
Thanks for pulling!
Biju Das (2):
dt-bindings: pinctrl: sh-pfc: Document r8a774b1 PFC support
pinctrl: sh-pfc: r8a77965: Add R8A774B1 PFC support
Chris Brandt (1):
pinctrl: rza2: Fix gpio name typos
Colin Ian King (1):
pinctrl: rzn1: Make array reg_drive static, makes object smaller
Geert Uytterhoeven (2):
Revert "pinctrl: sh-pfc: r8a77990: Fix MOD_SEL1 bit30 when using SSI_SCK2
and SSI_WS2"
Revert "pinctrl: sh-pfc: r8a77990: Fix MOD_SEL1 bit31 when using SIM0_D"
Keiya Nobuta (5):
pinctrl: sh-pfc: Fix PINMUX_IPSR_PHYS() to set GPSR
pinctrl: sh-pfc: pfc-r8a7795: Fix typo in pinmux macro for SCL3
pinctrl: sh-pfc: pfc-r8a7795-es1: Fix typo in pinmux macro for SCL3
pinctrl: sh-pfc: pfc-r8a7796: Fix typo in pinmux macro for SCL3
pinctrl: sh-pfc: pfc-r8a77965: Fix typo in pinmux macro for SCL3
Takeshi Kihara (1):
pinctrl: sh-pfc: r8a77990: Rename AVB_AVTP_{MATCH,CAPTURE} pin functions
.../bindings/pinctrl/renesas,pfc-pinctrl.txt | 1 +
drivers/pinctrl/pinctrl-rza2.c | 4 +-
drivers/pinctrl/pinctrl-rzn1.c | 2 +-
drivers/pinctrl/sh-pfc/Kconfig | 4 +
drivers/pinctrl/sh-pfc/Makefile| 1 +
drivers/pinctrl/sh-pfc/core.c | 6 +
drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c | 2 +-
drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 2 +-
drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 2 +-
drivers/pinctrl/sh-pfc/pfc-r8a77965.c | 863 +++--
drivers/pinctrl/sh-pfc/pfc-r8a77990.c | 57 +-
drivers/pinctrl/sh-pfc/sh_pfc.h| 5 +-
12 files changed, 504 insertions(+), 445 deletions(-)
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
[PULL 5/5] Renesas DT binding updates for v5.5
The following changes since commit 54ecb8f7028c5eb3d740bb82b0f1d90f2df63c5c: Linux 5.4-rc1 (2019-09-30 10:35:40 -0700) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel.git tags/renesas-dt-bindings-for-v5.5-tag1 for you to fetch changes up to 4d3cae42544775c71521e8ed5adb64c1839036b9: dt-bindings: reset: rcar-rst: Document r8a774b1 reset module (2019-10-01 09:52:34 +0200) Renesas DT binding updates for v5.5 - RZ/G2M update for the Renesas Timer Unit bindings, - Support for the new RZ/G2N (r8a774b1) SoC and the HiHope RZ/G2N board. Biju Das (4): dt-bindings: arm: renesas: Document RZ/G2N SoC DT bindings dt-bindings: arm: renesas: Add HopeRun RZ/G2N boards dt-bindings: power: rcar-sysc: Document r8a774b1 sysc dt-bindings: reset: rcar-rst: Document r8a774b1 reset module Fabrizio Castro (1): dt-bindings: timer: renesas: tmu: Document r8a774a1 bindings Documentation/devicetree/bindings/arm/renesas.yaml | 12 .../devicetree/bindings/power/renesas,rcar-sysc.txt | 1 + Documentation/devicetree/bindings/reset/renesas,rst.txt | 1 + Documentation/devicetree/bindings/timer/renesas,tmu.txt | 1 + 4 files changed, 15 insertions(+)
[PULL 4/5] Renesas driver updates for v5.5
The following changes since commit 54ecb8f7028c5eb3d740bb82b0f1d90f2df63c5c: Linux 5.4-rc1 (2019-09-30 10:35:40 -0700) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel.git tags/renesas-drivers-for-v5.5-tag1 for you to fetch changes up to 6655c568ced0789479f00b9399603c5d6ee48640: soc: renesas: rcar-sysc: Add r8a774b1 support (2019-10-01 10:29:40 +0200) Renesas driver updates for v5.5 - Add support for the new RZ/G2N (r8a774b1) SoC, - Fix System Controller power request conflicts on recent R-Car Gen3 and RZ/G2N SoC variants and revisions, - Minor cleanups. Biju Das (6): dt-bindings: power: Add r8a774b1 SYSC power domain definitions dt-bindings: clk: Add r8a774b1 CPG Core Clock Definitions soc: renesas: Add Renesas R8A774B1 config option soc: renesas: Identify RZ/G2N soc: renesas: rcar-rst: Add support for RZ/G2N soc: renesas: rcar-sysc: Add r8a774b1 support Geert Uytterhoeven (9): soc: renesas: rcar-sysc: Prepare for fixing power request conflicts soc: renesas: r8a7795-sysc: Fix power request conflicts soc: renesas: r8a7796-sysc: Fix power request conflicts soc: renesas: r8a77965-sysc: Fix power request conflicts soc: renesas: r8a77970-sysc: Fix power request conflicts soc: renesas: r8a77980-sysc: Fix power request conflicts soc: renesas: r8a77990-sysc: Fix power request conflicts soc: renesas: r8a774c0-sysc: Fix power request conflicts soc: renesas: rcar-sysc: Remove unneeded inclusion of drivers/soc/renesas/Kconfig | 11 ++ drivers/soc/renesas/Makefile | 1 + drivers/soc/renesas/r8a7743-sysc.c| 1 - drivers/soc/renesas/r8a7745-sysc.c| 1 - drivers/soc/renesas/r8a77470-sysc.c | 1 - drivers/soc/renesas/r8a774a1-sysc.c | 1 - drivers/soc/renesas/r8a774b1-sysc.c | 37 + drivers/soc/renesas/r8a774c0-sysc.c | 4 +- drivers/soc/renesas/r8a7779-sysc.c| 1 - drivers/soc/renesas/r8a7790-sysc.c| 1 - drivers/soc/renesas/r8a7791-sysc.c| 1 - drivers/soc/renesas/r8a7792-sysc.c| 1 - drivers/soc/renesas/r8a7794-sysc.c| 1 - drivers/soc/renesas/r8a7795-sysc.c| 33 +--- drivers/soc/renesas/r8a7796-sysc.c| 23 ++- drivers/soc/renesas/r8a77965-sysc.c | 4 +- drivers/soc/renesas/r8a77970-sysc.c | 4 +- drivers/soc/renesas/r8a77980-sysc.c | 4 +- drivers/soc/renesas/r8a77990-sysc.c | 4 +- drivers/soc/renesas/r8a77995-sysc.c | 1 - drivers/soc/renesas/rcar-rst.c| 1 + drivers/soc/renesas/rcar-sysc.c | 19 + drivers/soc/renesas/rcar-sysc.h | 8 +++- drivers/soc/renesas/renesas-soc.c | 8 include/dt-bindings/clock/r8a774b1-cpg-mssr.h | 57 +++ include/dt-bindings/power/r8a774b1-sysc.h | 26 26 files changed, 229 insertions(+), 25 deletions(-) create mode 100644 drivers/soc/renesas/r8a774b1-sysc.c create mode 100644 include/dt-bindings/clock/r8a774b1-cpg-mssr.h create mode 100644 include/dt-bindings/power/r8a774b1-sysc.h
Re: [PATCH V3 2/3] PCI: rcar: Do not abort on too many inbound dma-ranges
Hi Andrew,
On Fri, Oct 18, 2019 at 12:07 PM Andrew Murray wrote:
> On Thu, Oct 17, 2019 at 12:33:24AM +0200, Marek Vasut wrote:
> > On 10/17/19 12:26 AM, Rob Herring wrote:
> > [...]
> > >>>> You can have multiple non-continuous DRAM banks for example. And an
> > >>>> entry for SRAM optionally. Each DRAM bank and/or the SRAM should have a
> > >>>> separate dma-ranges entry, right ?
> > >>>
> > >>> Not necessarily. We really only want to define the minimum we have to.
> > >>> The ideal system is no dma-ranges. Is each bank at a different
> > >>> relative position compared to the CPU's view of the system. That would
> > >>> seem doubtful for just DRAM banks. Perhaps DRAM and SRAM could change.
> > >>
> > >> Is that a question ? Anyway, yes, there is a bit of DRAM below the 32bit
> > >> boundary and some more above the 32bit boundary. These two banks don't
> > >> need to be continuous. And then you could add the SRAM into the mix.
> > >
> > > Continuous is irrelevant. My question was in more specific terms is
> > > (bank1 addr - bank0 addr) different for CPU's view (i.e phys addr) vs.
> > > PCI host view (i.e. bus addr)? If not, then that is 1 translation and
> > > 1 dma-ranges entry.
> >
> > I don't think it's different in that aspect. Except the bus has this
> > 32bit limitation, where it only sees subset of the DRAM.
> >
> > Why should the DMA ranges incorrectly cover also the DRAM which is not
> > present ?
>
> I think this is where there is a difference in understanding.
>
> If I understand correctly, the job of the dma-ranges property isn't to
> describe *what* ranges the PCI device can access - it's there to describe
> *how*, i.e. the mapping between PCI and CPU-visible memory.
>
> The dma-ranges property is a side-effect of how the busses are wired up
> between the CPU and PCI controller - and so it doesn't matter what is or
> isn't on those buses.
>
> It's the job of other parts of the system to ensure that PCI devices are
> told the correct addresses to write to, e.g. the enumerating software
> referring to a valid CPU visible address correctly translated for the view
> of the PCI device, ATS etc. And any IOMMU to enforce that.
Yep, that's what I thought, too.
> It sounds like there is a 1:1 mapping between CPU and PCI - in which case
> there isn't a reason for a dma-ranges.
There's still the 32-bit limitation: PCI devices can access low 32-bit addresses
only.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Re: drivers/pinctrl/sh-pfc/pfc-sh7734.c multiple define of TCLK1_B
Hi Ben,
On Thu, Oct 17, 2019 at 1:54 PM Ben Dooks wrote:
> drivers/pinctrl/sh-pfc/pfc-sh7734.c hsa TCLK1_B defined twice.
> Not sure how to fix, so reporting it here:
>
>1453 GPIO_FN(RD_WR), GPIO_FN(TCLK1_B),
>1454 GPIO_FN(EX_WAIT0), GPIO_FN(TCLK1_B),
Thanks, nice catch!
Looks like (a) someone accidentally jumped to the wrong row in the
datasheet when entering this, and (b) we need more runtime checks to
catch bugs like this.
Will fix...
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Re: [PATCH V3 2/3] PCI: rcar: Do not abort on too many inbound dma-ranges
Hi Marek,
On Thu, Oct 17, 2019 at 12:33 AM Marek Vasut wrote:
> On 10/17/19 12:26 AM, Rob Herring wrote:
> [...]
> >>>> You can have multiple non-continuous DRAM banks for example. And an
> >>>> entry for SRAM optionally. Each DRAM bank and/or the SRAM should have a
> >>>> separate dma-ranges entry, right ?
> >>>
> >>> Not necessarily. We really only want to define the minimum we have to.
> >>> The ideal system is no dma-ranges. Is each bank at a different
> >>> relative position compared to the CPU's view of the system. That would
> >>> seem doubtful for just DRAM banks. Perhaps DRAM and SRAM could change.
> >>
> >> Is that a question ? Anyway, yes, there is a bit of DRAM below the 32bit
> >> boundary and some more above the 32bit boundary. These two banks don't
> >> need to be continuous. And then you could add the SRAM into the mix.
> >
> > Continuous is irrelevant. My question was in more specific terms is
> > (bank1 addr - bank0 addr) different for CPU's view (i.e phys addr) vs.
> > PCI host view (i.e. bus addr)? If not, then that is 1 translation and
> > 1 dma-ranges entry.
>
> I don't think it's different in that aspect. Except the bus has this
> 32bit limitation, where it only sees subset of the DRAM.
>
> Why should the DMA ranges incorrectly cover also the DRAM which is not
> present ?
>
> >>> I suppose if your intent is to use inbound windows as a poor man's
> >>> IOMMU to prevent accesses to the holes, then yes you would list them
> >>> out. But I think that's wrong and difficult to maintain. You'd also
> >>> need to deal with reserved-memory regions too.
> >>
> >> What's the problem with that? The bootloader has all that information
> >> and can patch the DT correctly. In fact, in my specific case, I have
> >> platform which can be populated with differently sized DRAM, so the
> >> holes are also dynamically calculated ; there is no one DT then, the
> >> bootloader is responsible to generate the dma-ranges accordingly.
> >
> > The problems are it doesn't work:
> >
> > Your dma-mask and offset are not going to be correct.
> >
> > You are running out of inbound windows. Your patch does nothing to
> > solve that. The solution would be merging multiple dma-ranges entries
> > to a single inbound window. We'd have to do that both for dma-mask and
> > inbound windows. The former would also have to figure out which
> > entries apply to setting up dma-mask. I'm simply suggesting just do
> > that up front and avoid any pointless splits.
>
> But then the PCI device can trigger a transaction to non-existent DRAM
> and cause undefined behavior. Surely we do not want that ?
The PCI device will trigger transactions to memory only when instructed
to do so by Linux, right? Hence if Linux takes into account chosen/memory
and dma-ranges, there is no problem?
> > You are setting up random inbound windows. The bootloader can't assume
> > what order the OS parses dma-ranges, and the OS can't assume what
> > order the bootloader writes the entries.
>
> But the OS can assume the ranges are correct and cover only valid
> memory, right ? That is, memory into which the PCI controller can safely
> access.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
[PATCH] dt-bindings: arm: renesas: Add R-Car M3-N ULCB with Kingfisher
Document the use of the Kingfisher expansion board with the R-Car Starter Kit Pro equipped with an R-Car M3-N SoC. Signed-off-by: Geert Uytterhoeven --- make ARCH=arm dtbs_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/arm/renesas.yaml arch/arm64/boot/dts/renesas/r8a77965-m3nulcb-kf.dt.yaml: compatible: ['shimafuji,kingfisher', 'renesas,m3nulcb', 'renesas,r8a77965'] is not valid under any of the given schemas --- Documentation/devicetree/bindings/arm/renesas.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/arm/renesas.yaml index 99b290ca418a8a92..9436124c58090860 100644 --- a/Documentation/devicetree/bindings/arm/renesas.yaml +++ b/Documentation/devicetree/bindings/arm/renesas.yaml @@ -217,9 +217,11 @@ properties: - enum: - renesas,h3ulcb - renesas,m3ulcb + - renesas,m3nulcb - enum: - renesas,r8a7795 - renesas,r8a7796 + - renesas,r8a77965 - description: R-Car M3-N (R8A77965) items: -- 2.17.1
[PATCH] ARM: shmobile: rcar-gen2: Drop legacy DT clock support
As of commit 362b334b17943d84 ("ARM: dts: r8a7791: Convert to new
CPG/MSSR bindings"), all upstream R-Car Gen2 device tree source files
use the unified "Renesas Clock Pulse Generator / Module Standby and
Software Reset" DT bindings.
Hence remove backward compatibility with old R-Car Gen2 device trees
describing a hierarchical representation of the various CPG and MSTP
clocks.
Signed-off-by: Geert Uytterhoeven
---
To be queued in renesas-devel-for-v5.5.
The abovementioned commit was part of the v4.15 release.
The conversion was backported to v4.14.75-ltsi, and included in any
R-Car BSP based on v4.14 (rcar-3.6.0 and later).
---
arch/arm/mach-shmobile/setup-rcar-gen2.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm/mach-shmobile/setup-rcar-gen2.c
b/arch/arm/mach-shmobile/setup-rcar-gen2.c
index 9e4bc1865f84abae..2fd3aa6f32124df0 100644
--- a/arch/arm/mach-shmobile/setup-rcar-gen2.c
+++ b/arch/arm/mach-shmobile/setup-rcar-gen2.c
@@ -24,7 +24,6 @@
#include "rcar-gen2.h"
static const struct of_device_id cpg_matches[] __initconst = {
- { .compatible = "renesas,rcar-gen2-cpg-clocks", },
{ .compatible = "renesas,r8a7743-cpg-mssr", .data = "extal" },
{ .compatible = "renesas,r8a7744-cpg-mssr", .data = "extal" },
{ .compatible = "renesas,r8a7790-cpg-mssr", .data = "extal" },
[PATCH] clk: renesas: r8a77965: Remove superfluous semicolon
There is no need to terminate a function with a semicolon. Remove it.
Reported-by: Biju Das
Fixes: 7ce36da900c0a2ff ("clk: renesas: cpg-mssr: Add support for R-Car M3-N")
Signed-off-by: Geert Uytterhoeven
---
To be queued in clk-renesas-for-v5.5.
drivers/clk/renesas/r8a77965-cpg-mssr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/renesas/r8a77965-cpg-mssr.c
b/drivers/clk/renesas/r8a77965-cpg-mssr.c
index b4e8c5b7d515635d..b3af4da2ca74b15d 100644
--- a/drivers/clk/renesas/r8a77965-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77965-cpg-mssr.c
@@ -323,7 +323,7 @@ static int __init r8a77965_cpg_mssr_init(struct device *dev)
}
return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode);
-};
+}
const struct cpg_mssr_info r8a77965_cpg_mssr_info __initconst = {
/* Core Clocks */
--
2.17.1
[PATCH] dt-bindings: clock: renesas: rcar-usb2-clock-sel: Fix typo in example
The documented compatible value for R-Car H3 is
"renesas,r8a7795-rcar-usb2-clock-sel", not
"renesas,r8a77950-rcar-usb2-clock-sel".
Fixes: 311accb64570db45 ("clk: renesas: rcar-usb2-clock-sel: Add R-Car USB 2.0
clock selector PHY")
Signed-off-by: Geert Uytterhoeven
---
This binding has no DTS users in upstream, nor in the BSP?
---
.../devicetree/bindings/clock/renesas,rcar-usb2-clock-sel.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
a/Documentation/devicetree/bindings/clock/renesas,rcar-usb2-clock-sel.txt
b/Documentation/devicetree/bindings/clock/renesas,rcar-usb2-clock-sel.txt
index e96e085271c134f4..83f6c6a7c41c76ca 100644
--- a/Documentation/devicetree/bindings/clock/renesas,rcar-usb2-clock-sel.txt
+++ b/Documentation/devicetree/bindings/clock/renesas,rcar-usb2-clock-sel.txt
@@ -46,7 +46,7 @@ Required properties:
Example (R-Car H3):
usb2_clksel: clock-controller@e6590630 {
- compatible = "renesas,r8a77950-rcar-usb2-clock-sel",
+ compatible = "renesas,r8a7795-rcar-usb2-clock-sel",
"renesas,rcar-gen3-usb2-clock-sel";
reg = <0 0xe6590630 0 0x02>;
clocks = <&cpg CPG_MOD 703>, <&usb_extal>, <&usb_xtal>;
--
2.17.1
[PATCH] dt-bindings: clock: renesas: Remove R-Car Gen2 legacy DT bindings
As of commit 362b334b17943d84 ("ARM: dts: r8a7791: Convert to new
CPG/MSSR bindings"), all upstream R-Car Gen2 device tree source files
use the unified "Renesas Clock Pulse Generator / Module Standby and
Software Reset" DT bindings.
Hence remove the old R-Car Gen2 DT bindings describing a hierarchical
representation of the various CPG and MSTP clocks.
Signed-off-by: Geert Uytterhoeven
---
To be queued in clk-renesas-for-v5.5.
The abovementioned commit was part of the v4.15 release.
The conversion was backported to v4.14.75-ltsi, and included in any
R-Car BSP based on v4.14 (rcar-3.6.0 and later).
---
.../clock/renesas,rcar-gen2-cpg-clocks.txt| 60 ---
1 file changed, 60 deletions(-)
delete mode 100644
Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt
diff --git
a/Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt
b/Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt
deleted file mode 100644
index f8c05bb4116eae54..
--- a/Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt
+++ /dev/null
@@ -1,60 +0,0 @@
-* Renesas R-Car Gen2 Clock Pulse Generator (CPG)
-
-The CPG generates core clocks for the R-Car Gen2 SoCs. It includes three PLLs
-and several fixed ratio dividers.
-The CPG also provides a Clock Domain for SoC devices, in combination with the
-CPG Module Stop (MSTP) Clocks.
-
-Required Properties:
-
- - compatible: Must be one of
-- "renesas,r8a7790-cpg-clocks" for the r8a7790 CPG
-- "renesas,r8a7791-cpg-clocks" for the r8a7791 CPG
-- "renesas,r8a7792-cpg-clocks" for the r8a7792 CPG
-- "renesas,r8a7793-cpg-clocks" for the r8a7793 CPG
-- "renesas,r8a7794-cpg-clocks" for the r8a7794 CPG
-and "renesas,rcar-gen2-cpg-clocks" as a fallback.
-
- - reg: Base address and length of the memory resource used by the CPG
-
- - clocks: References to the parent clocks: first to the EXTAL clock, second
-to the USB_EXTAL clock
- - #clock-cells: Must be 1
- - clock-output-names: The names of the clocks. Supported clocks are "main",
-"pll0", "pll1", "pll3", "lb", "qspi", "sdh", "sd0", "sd1", "z", "rcan", and
-"adsp"
- - #power-domain-cells: Must be 0
-
-SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed
-through an MSTP clock should refer to the CPG device node in their
-"power-domains" property, as documented by the generic PM domain bindings in
-Documentation/devicetree/bindings/power/power_domain.txt.
-
-
-Examples
-
-
- - CPG device node:
-
- cpg_clocks: cpg_clocks@e615 {
- compatible = "renesas,r8a7790-cpg-clocks",
-"renesas,rcar-gen2-cpg-clocks";
- reg = <0 0xe615 0 0x1000>;
- clocks = <&extal_clk &usb_extal_clk>;
- #clock-cells = <1>;
- clock-output-names = "main", "pll0, "pll1", "pll3",
-"lb", "qspi", "sdh", "sd0", "sd1", "z",
-"rcan", "adsp";
- #power-domain-cells = <0>;
- };
-
-
- - CPG/MSTP Clock Domain member device node:
-
- thermal@e61f {
- compatible = "renesas,thermal-r8a7790", "renesas,rcar-thermal";
- reg = <0 0xe61f 0 0x14>, <0 0xe61f0100 0 0x38>;
- interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&mstp5_clks R8A7790_CLK_THERMAL>;
- power-domains = <&cpg_clocks>;
- };
--
2.17.1
[PATCH] soc: renesas: Add missing check for non-zero product register address
If the DTB for a device with an RZ/A2 SoC lacks a device node for the
BSID register, the ID validation code falls back to using a register at
address 0x0, which leads to undefined behavior (e.g. reading back a
random value).
This could be fixed by letting fam_rza2.reg point to the actual BSID
register. However, the hardcoded fallbacks were meant for backwards
compatibility with old DTBs only, not for new SoCs. Hence fix this by
validating renesas_family.reg before using it.
Fixes: 175f435f44b724e3 ("soc: renesas: identify RZ/A2")
Signed-off-by: Geert Uytterhoeven
---
drivers/soc/renesas/renesas-soc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/soc/renesas/renesas-soc.c
b/drivers/soc/renesas/renesas-soc.c
index 5dc2ae55f746a48a..85aaf85ce6b192d9 100644
--- a/drivers/soc/renesas/renesas-soc.c
+++ b/drivers/soc/renesas/renesas-soc.c
@@ -337,7 +337,7 @@ static int __init renesas_soc_init(void)
if (np) {
chipid = of_iomap(np, 0);
of_node_put(np);
- } else if (soc->id) {
+ } else if (soc->id && family->reg) {
chipid = ioremap(family->reg, 4);
}
if (chipid) {
--
2.17.1
Re: [PATCH/RFC 17/19] arm64: dts: renesas: Add support for Salvator-XS with R-Car M3-W+
Hi Eugeniu,
On Mon, Oct 14, 2019 at 7:57 PM Eugeniu Rosca wrote:
> On Mon, Oct 07, 2019 at 12:23:30PM +0200, Geert Uytterhoeven wrote:
> > Add initial support for the Renesas Salvator-X 2nd version development
> > board equipped with an R-Car M3-W+ SiP with 8 (2 x 4) GiB of RAM.
> >
> > The memory map is as follows:
> > - Bank0: 4GiB RAM : 0x4800 -> 0x000bfff
> > 0x00048000 -> 0x004
> > - Bank1: 4GiB RAM : 0x0006 -> 0x006
> >
> > Based on a patch in the BSP by Takeshi Kihara
> > .
> >
> > Signed-off-by: Geert Uytterhoeven
> > ---
> > arch/arm64/boot/dts/renesas/Makefile | 1 +
> > .../boot/dts/renesas/r8a77961-salvator-xs.dts | 31 +++
> > 2 files changed, 32 insertions(+)
> > create mode 100644 arch/arm64/boot/dts/renesas/r8a77961-salvator-xs.dts
>
> It is common practice in Renesas BSP to specify the SiP memory
> split by suffixing the DTB names with '-{2,4}x{2,4}g' [1].
>
> Has this ever been discussed on ML?
>
> Here in particular, it would allow M3-W+ 2x4GiB Salvator-XS and
> M3-W+ 2x2GiB (or any other DRAM split flavor of) Salvator-XS to
> coexist in harmony, if the latter pops up at any point.
With mainline U-Boot, the memory configuration is passed from ATF
through U-Boot to Linux, see e.g. "ARM: renesas: Configure DRAM size
from ATF DT fragment" [1], so there's no longer a need to maintain
multiple DTS files.
[1]
https://gitlab.denx.de/u-boot/u-boot/commit/175f5027345c7feaa41e8f4201778814bf72fe37
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Re: [PATCH/RFC 00/19] arm64: dts: renesas: Initial support for R-Car M3-W+
Hi Eugeniu,
On Mon, Oct 14, 2019 at 9:58 PM Eugeniu Rosca wrote:
> On Mon, Oct 07, 2019 at 12:23:13PM +0200, Geert Uytterhoeven wrote:
> > This RFC patch series adds support for the R-Car M3-W+ (R8A77961) SoC
> > and the Salvator-XS board with R-Car M3-W+. This SoC is a derivative of
> > R-Car M3-W (R8A77960), and also known as R-Car M3-W ES3.0.
> > As this is an RFC, I'm sending it to a limited audience.
> >
> > Based on experience with previous SoCs in the R-Car Gen3 family, the
> > following design decisions were made:
> > - Use different compatible values (r8a77961-based),
>
> Given that a potentially incomplete list of M3-W compatible strings
> counts 40 occurrences [1] and this series adds only 7 [2], current RFC
> looks like the first step in a multi-phase approach. Do you plan to add
> the missing r8a77961 compatibles in the next revision or do you expect
> other people to contribute those later?
This is indeed a multi-phase approach.
I plan to add more later, and welcome other people in our team to do so, too.
However, as we currently have limited (remote) access, we cannot
add/test all other devices.
So if you have hardware access, any help is welcome.
> > - Use different clock and SYSC DT binding definitions
> > (R8A77961-based), but the same numerical values, to allow sharing
> > drivers,
> > - Share the pin control driver,
> > - Share the clock driver,
> > - Share the system controller driver.
> >
> > While the DT ABI is stable (hence we cannot s/r8a7796/r8a77960/ in DTS),
> > kernel source code and kernel config symbols can be changed at any
> > time. As changing kernel config symbols impacts the user, they weren't
> > renamed yet.
> >
> > Questions:
> > - What's the board part number of Salvator-XS with R-Car M3-W+?
>
> I guess my board is an exception, since it got the SiP simply upgraded
> from SoC ES1.x to ES3.0 by resoldering. IOW the board carries the same
> serial number as M3-ES1.1 Salvator-XS.
Yes, AFAIK, all Salvator-X and Salvator-XS boards have the same PCB
(modulo minor revision updates), and support all of H3/M3-W/M3-N SiPs
(except for H3 ES1.x, which is not supported by the -XS variant).
So upgraded boards retain their original part number.
> > - Should the R8A77961 config symbols be dropped?
> > - CONFIG_ARCH_R8A77961
> > - CONFIG_CLK_R8A77961
> > - CONFIG_PINCTRL_PFC_R8A77961
> > - CONFIG_SYSC_R8A77961
> >
> > - If not, should the R8A7796 config symbols be renamed?
> > - CONFIG_ARCH_R8A7796 to CONFIG_ARCH_R8A77960?
> > - CONFIG_CLK_R8A7796 to CONFIG_CLK_R8A77960?
> > - CONFIG_PINCTRL_PFC_R8A7796 to CONFIG_PINCTRL_PFC_R8A77960?
> > - CONFIG_SYSC_R8A7796 to CONFIG_SYSC_R8A77960?
> > Due to dependencies on CONFIG_ARCH_R8A7796, this should be a single
> > commit.
>
> [2 cents] Both adding CONFIG_*_R8A77961 and renaming CONFIG_*_R8A7796 to
> CONFIG_*_R8A77960 make sense to me.
>
> > Related questions for old R-Car H3 ES1.x support:
> > - Should CONFIG_PINCTRL_PFC_R8A77950 be added, to allow compiling out
> > R-Car H3 ES1.x pin control support?
>
> [2 cents] Adding CONFIG_*_R8A77950 makes sense in spite of the fact that
> R8A77950 is not documented in R-Car HW man. In fact, it is quite clear
> why R8A77950 is _not_ documented while R8A77960 _is_ documented. The
> former is obsolete (the community is nice by not obliterating its
> support) while the latter is expected to hit the market.
>
> > If yes, should CONFIG_PINCTRL_PFC_R8A7795 be renamed to
> > CONFIG_PINCTRL_PFC_R8A77951?
>
> In a perfect/ideal world, I would say yes.
Thanks for your feedback!
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Re: [PATCH/RFC 03/19] dt-bindings: clock: renesas: cpg-mssr: Document r8a77961 support
Hi Eugeniu,
On Mon, Oct 14, 2019 at 8:46 PM Eugeniu Rosca wrote:
> On Mon, Oct 07, 2019 at 12:23:16PM +0200, Geert Uytterhoeven wrote:
> > Add DT binding documentation for the Clock Pulse Generator / Module
> > Standby and Software Reset block in the Renesas R-Car M3-W+ (R8A77961)
> > SoC.
> >
> > Signed-off-by: Geert Uytterhoeven
> > ---
> > .../devicetree/bindings/clock/renesas,cpg-mssr.txt | 9 +
> > 1 file changed, 5 insertions(+), 4 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
> > b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
> > index b5edebeb12b40638..b9b0927b7c780699 100644
> > --- a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
> > +++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
>
> [..]
>
> > @@ -42,10 +43,10 @@ Required Properties:
> >- clock-names: List of external parent clock names. Valid names are:
> >- "extal" (r7s9210, r8a7743, r8a7744, r8a7745, r8a77470, r8a774a1,
> >r8a774b1, r8a774c0, r8a7790, r8a7791, r8a7792, r8a7793,
> > - r8a7794, r8a7795, r8a7796, r8a77965, r8a77970, r8a77980,
> > - r8a77990, r8a77995)
> > - - "extalr" (r8a774a1, r8a774b1, r8a7795, r8a7796, r8a77965, r8a77970,
> > - r8a77980)
> > + r8a7794, r8a7795, r8a7796, r8a77961, r8a77965, r8a77970,
> > + r8a77980, r8a77990, r8a77995)
> > + - "extalr" (r8a774a1, r8a774b1, r8a7795, r8a7796, r8a77961, r8a77965,
> > + r8a77970, r8a77980)
> >- "usb_extal" (r8a7743, r8a7744, r8a7745, r8a77470, r8a7790, r8a7791,
> >r8a7793, r8a7794)
>
> Not easy to review, but 'git show --color-words' comes to the rescue :)
Exactly ;-)
$ git help wshow
'wshow' is aliased to 'show --color-words'
$ git help wlog
'wlog' is aliased to 'log --color-words'
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
renesas-drivers-2019-10-15-v5.4-rc3
I have pushed renesas-drivers-2019-10-15-v5.4-rc3 to
https://git.kernel.org/cgit/linux/kernel/git/geert/renesas-drivers.git
This tree is meant to ease development of platform support and drivers
for Renesas ARM SoCs. It is created by merging (a) the for-next branches
of various subsystem trees and (b) branches with driver code submitted
or planned for submission to maintainers into the master branch of my
renesas-devel.git tree.
Today's version is based on renesas-devel-2019-10-14-v5.4-rc3.
Included branches with driver code:
- clk-renesas
- sh-pfc
- topic/r8a77961-v1-rebased
- git://git.ragnatech.se/linux#for-renesas-drivers
Included fixes:
- Revert "serial: core: Use cons->index for preferred console registration"
- ARM: shmobile: defconfig: Update shmobile_defconfig
- [LOCAL] arm64: defconfig: Update renesas_defconfig
Included subsystem trees:
- git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm.git#linux-next
- git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git#clk-next
-
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl.git#for-next
- git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio.git#for-next
- git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git#for-next
- git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git#mtd/next
- git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next.git#master
- git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty.git#tty-next
- git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux.git#i2c/for-next
- git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git#for-next
- git://git.kernel.org/pub/scm/linux/kernel/git/mkl/linux-can-next.git#master
- git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb.git#usb-next
- git://git.freedesktop.org/git/drm/drm.git#drm-next
- git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu.git#next
- git://linuxtv.org/media_tree.git#master
- git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc.git#next
-
git://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm.git#for-next
- git://git.linaro.org/people/daniel.lezcano/linux.git#clockevents/next
- git://git.kernel.org/pub/scm/linux/kernel/git/balbi/usb.git#testing/next
- git://git.infradead.org/users/vkoul/slave-dma.git#next
-
git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging.git#staging-next
- git://git.armlinux.org.uk/~rmk/linux-arm.git#for-next
- git://git.kernel.org/pub/scm/linux/kernel/git/rzhang/linux.git#next
- git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regmap.git#for-next
- git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git#irq/core
- git://github.com/bzolnier/linux.git#fbdev-for-next
- git://git.kernel.org/pub/scm/linux/kernel/git/axboe/linux-block.git#for-next
-
git://git.kernel.org/pub/scm/linux/kernel/git/sre/linux-power-supply.git#for-next
- git://www.linux-watchdog.org/linux-watchdog-next.git#master
- git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git#for-next
- git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regulator.git#for-next
- git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux.git#for-next/core
- git://anongit.freedesktop.org/drm/drm-misc#for-linux-next
- git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git#next
- git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy.git#next
-
git://git.kernel.org/pub/scm/linux/kernel/git/evalenti/linux-soc-thermal.git#next
- git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd.git#for-mfd-next
- git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git#for-next
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Re: [PATCH 4/4] pinctrl: sh-pfc: pfc-r8a77965: Fix typo in pinmux macro for SCL3
On Tue, Oct 8, 2019 at 8:06 AM Keiya Nobuta wrote:
> SCL3 is assigned to GPSR2 bit7 referred by IP1_23_20 macro.
>
> Signed-off-by: Keiya Nobuta
Reviewed-by: Geert Uytterhoeven
i.e. will queue in sh-pfc-for-v5.5.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Re: [PATCH] pinctrl: sh-pfc: Fix PINMUX_IPSR_PHYS() to set to GPSR
On Tue, Oct 8, 2019 at 8:02 AM Keiya Nobuta wrote:
> This patch allows PINMUX_IPSR_PHYS() to set bits to GPSR.
> When assigning function to pin, GPSR should be set peripheral function.
> For example in using SCL3, GPSR2 bit7 (PWM1_A pin) should be set to
> peripheral function.
>
> Signed-off-by: Keiya Nobuta
Fixes: 50d1ba1764b3e00a ("pinctrl: sh-pfc: Add physical pin
multiplexing helper macros")
Reviewed-by: Geert Uytterhoeven
i.e. will queue in sh-pfc-for-v5.5.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Re: [PATCH 2/4] pinctrl: sh-pfc: pfc-r8a7795-es1: Fix typo in pinmux macro for SCL3
On Tue, Oct 8, 2019 at 8:06 AM Keiya Nobuta wrote:
> SCL3 is assigned to GPSR2 bit7 referred by IP1_23_20 macro.
>
> Signed-off-by: Keiya Nobuta
Reviewed-by: Geert Uytterhoeven
i.e. will queue in sh-pfc-for-v5.5.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Re: [PATCH 3/4] pinctrl: sh-pfc: pfc-r8a7796: Fix typo in pinmux macro for SCL3
On Tue, Oct 8, 2019 at 8:06 AM Keiya Nobuta wrote:
> SCL3 is assigned to GPSR2 bit7 referred by IP1_23_20 macro.
>
> Signed-off-by: Keiya Nobuta
Reviewed-by: Geert Uytterhoeven
i.e. will queue in sh-pfc-for-v5.5.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Re: [PATCH 1/4] pinctrl: sh-pfc: pfc-r8a7795: Fix typo in pinmux macro for SCL3
On Tue, Oct 8, 2019 at 8:06 AM Keiya Nobuta wrote:
> SCL3 is assigned to GPSR2 bit7 referred by IP1_23_20 macro.
>
> Signed-off-by: Keiya Nobuta
Reviewed-by: Geert Uytterhoeven
i.e. will queue in sh-pfc-for-v5.5.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Re: [PATCH v2 3/3] arm64: dts: renesas: r8a774b1: Add CAN and CAN FD support
On Thu, Oct 10, 2019 at 4:26 PM Fabrizio Castro
wrote:
> Add CAN and CAN FD support to the RZ/G2N SoC specific dtsi.
>
> Signed-off-by: Fabrizio Castro
Reviewed-by: Geert Uytterhoeven
i.e. will queue in renesas-devel for v5.5.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Re: Regarding CPU frequency reported by Salvator-X board
Hi Biju,
CC clk
On Mon, Oct 14, 2019 at 9:46 AM Biju Das wrote:
> I have further investigated this issue, please find my findings below
>
> The "cpg_z_clk_round_rate" function is called 2 times from
> "dev_pm_opp_set_rate" (1 is direct call and other through "clk_set_rate")
> function.
>
> For 5 frequency, after doing math operation(mult = div_u64(rate *
> 32ULL, prate);), it gets a factor 10--> 10.66 truncated to 10 and the
> frequency returned by the system is 468748125
>
> On the second " cpg_z_clk_round_rate ", the below function make the value to
> worse, it gets a value of 9., since it is integer division it is
> truncated to 9.
> mult = div_u64(rate * 32ULL, prate);
>
> Now the frequency 468748125, after doing math operation becomes 421874 KHz.
> This is the problem.
>
> So I think the div_64 is wrong here, Instead we could go with
> DIV64_U64_ROUND_CLOSEST.
>
> With "DIV64_U64_ROUND_CLOSEST" the factor is 10.66 which is rounded to 11.
>
> So for 50, after math operation, it becomes 515624
>
> Please share your opinion this issue.
I don't know what's the best way to solve this.
Rounding instead of truncating may lead to programming a too high clock
frequency, which might damage the hardware.
Please note that the current code no longer uses div_u64(), but div64_ul()
instead, which should have no impact on your findings.
> > -Original Message-
> > From: Biju Das
> > Sent: Thursday, September 19, 2019 11:49 AM
> > To: Geert Uytterhoeven ; Simon Horman
> > ; linux-renesas-soc@vger.kernel.org; Dien Pham
> > ; TAKESHI KIHARA
> > ; Niklas Söderlund
> >
> > Subject: Regarding CPU frequency reported by Salvator-X board
> >
> > Hi All,
> >
> > I started testing frequency mentioned in OPP table with M3-W1.1 Salvator-X
> > board (NOT salvator-XS) using user space governor
> >
> > The actual frequency reported for 0.5GHz(50 KHz) is too much deviated
> > from the target frequency [INFO] Target frequency: 50 KHz [INFO]
> > Actual frequency: 421874 KHz
> >
> > But if I change the extal value, as per the board schematic (16.MHz),
> > the
> > value is some what closer to target frequency.
> > &extal_clk {
> > - clock-frequency = <1666>;
> > + clock-frequency = <1600>;
> > };
> > [INFO] Target frequency: 50 KHz
> > [INFO] Actual frequency: 468748 KHz
> >
> > Q1) Have any one seen this issue? Please share your thoughts on this issue.
> >
> > Note:-
> > I am not seeing this issue on Salvator-XS board, where the extal_clk value=
> > 1664(16.64MHz).
> >
> > Please see the logs
> > with clock-frequency = <1666>;
> > ---
> > root@salvator-x:/cip-test-scripts# ./opp_t_001.sh [INFO] Testing cpufreq
> > for
> > policy:
> > [INFO] /sys/devices/system/cpu/cpufreq/policy0
> > [INFO]
> > [INFO] CPUs affected:
> > [INFO] 0 1
> > [INFO]
> > [INFO] Available frequencies:
> > [INFO] 50 100 150
> > [INFO]
> > [INFO] Target frequency: 50 KHz
> > [INFO] Actual frequency: 421874 KHz
> > [INFO]
> > [INFO] Target frequency: 100 KHz
> > [INFO] Actual frequency: 937499 KHz
> > [INFO]
> > [INFO] Target frequency: 150 KHz
> > [INFO] Actual frequency: 149 KHz
> > [INFO]
> > [INFO] Testing cpufreq for policy:
> > [INFO] /sys/devices/system/cpu/cpufreq/policy2
> > [INFO]
> > [INFO] CPUs affected:
> > [INFO] 2 3 4 5
> > [INFO]
> > [INFO] Available frequencies:
> > [INFO] 80 100 120
> > [INFO]
> > [INFO] Target frequency: 80 KHz
> > [INFO] Actual frequency: 74 KHz
> > [INFO]
> > [INFO] Target frequency: 100 KHz
> > [INFO] Actual frequency: 974999 KHz
> > [INFO]
> > [INFO] Target frequency: 120 KHz
> > [INFO] Actual frequency: 119 KHz
> >
> > With clock-frequency = <1600>
> > --
> > root@salvator-x:/cip-test-scripts# ./opp_t_001.sh [INFO] Testing cpufreq
> > for
> > policy:
> > [INFO] /sys/devices/system/cpu/cpufreq/policy0
> > [INFO]
> > [INFO] CPUs affected:
> > [INFO] 0 1
> > [INFO]
> > [INFO] Available frequencies:
> > [INFO] 50 100 150
> > [INFO]
> > [INFO] Target frequency: 50 KHz
> > [INFO] Actual frequency: 468748 KHz
>
Re: [PATCH] arm64: dts: renesas: add iommus into R-Car Gen3 sdhi/mmc nodes
On Mon, Oct 7, 2019 at 10:40 AM Yoshihiro Shimoda
wrote:
> This patch adds iommus properties into R-Car Gen3 SoCs'
> sdhi/mmc nodes.
>
> Signed-off-by: Yoshihiro Shimoda
Reviewed-by: Geert Uytterhoeven
i.e. will queue in renesas-devel for v5.5.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Re: [PATCH v3 9/9] arm64: dts: renesas: Add support for Advantech idk-1110wr LVDS panel
On Wed, Oct 2, 2019 at 5:21 PM Biju Das wrote:
> This patch adds support for Advantech idk-1110wr LVDS panel.
> The HiHope RZ/G2[MN] is advertised as compatible with panel
> idk-1110wr from Advantech, however the panel isn't sold alongside
> the board.
>
> Signed-off-by: Biju Das
> Signed-off-by: Fabrizio Castro
> Reviewed-by: Laurent Pinchart
Thanks, queued in renesas-devel for v5.5.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Re: [PATCH v2] dt-bindings: irqchip: renesas: intc-irqpin: convert bindings to json-schema
Hi Rob, Kaneko-san,
On Fri, Oct 11, 2019 at 12:07 AM Rob Herring wrote:
> On Fri, Sep 27, 2019 at 04:59:37AM +0900, Yoshihiro Kaneko wrote:
> > Convert R-/SH-Mobile IRQPin Controller bindings documentation to
> > json-schema.
> >
> > Signed-off-by: Yoshihiro Kaneko
> > --- /dev/null
> > +++
> > b/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.yaml
> > @@ -0,0 +1,102 @@
> > +# SPDX-License-Identifier: GPL-2.0
> > +%YAML 1.2
> > +---
> > +$id:
> > http://devicetree.org/schemas/interrupt-controller/renesas,intc-irqpin.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: DT bindings for the R-/SH-Mobile irqpin controller
> > +
> > +maintainers:
> > + - Geert Uytterhoeven
Looks like I received many maintainerships recently ;-)
> > +
> > +properties:
> > + compatible:
> > +items:
> > + - enum:
> > + - renesas,intc-irqpin-r8a7740 # R-Mobile A1
> > + - renesas,intc-irqpin-r8a7778 # R-Car M1A
> > + - renesas,intc-irqpin-r8a7779 # R-Car H1
> > + - renesas,intc-irqpin-sh73a0 # SH-Mobile AG5
> > + - const: renesas,intc-irqpin
> > +
> > + reg:
> > +# Base address and length of each register bank used by the external
> > +# IRQ pins driven by the interrupt controller hardware module. The base
> > +# addresses, length and number of required register banks varies with
> > +# soctype.
> > +minItems: 1
minItems: 5
> > +maxItems: 6
>
> Every entry is the same thing?
No they're not.
First entry is the Interrupt control register.
Second entry is the Interrupt priority register.
Third entry is the Interrupt source register.
Fourth entry is the Interrupt mask register.
Fifth entry is the Interrupt mask clear register.
Sixth entry is the optional Interrupt control register for ICR0 with IRLM bit.
The fact that SH/R-Mobile SoCs have 4 instances of this block, with
interleaved registers, and different register widths, doesn't help much,
and I understand that was the reason for the individual register
descriptions.
This is a very old binding, which tried to describe everything in DT,
using a generic compatible value. Of course this lead to a mess when
having different register layouts, optional registers, and a
sense-bitfield-width property...
The modern way would be to describe all differences in the driver, based
on SoC-specific compatible values.
Given this is for rather old SoCs, I see no point in upgrading the bindings.
> > +irqpin1: interrupt-controller@e694 {
> > +compatible = "renesas,intc-irqpin-r8a7740",
> > + "renesas,intc-irqpin";
> > +#interrupt-cells = <2>;
> > +interrupt-controller;
> > +reg = <0xe694 4>,
> > + <0xe6900014 4>,
> > + <0xe6900024 1>,
> > + <0xe6900044 1>,
> > + <0xe6900064 1>;
>
> Really only 1 byte?
Yep. Some registers are 8-bit on some SoCs...
> > +interrupts = > + GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
> > + GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
> > + GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
> > + GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
> > + GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
> > + GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
> > + GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
>
> <> each interrupt specifier.
>
> Above you said there is only 1 interrupt...
Which is wrong. But the description was correct.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Re: [PATCH v3 1/2] arm64: dts: renesas: r8a774a1: Remove audio port node
Hi Biju,
On Thu, Oct 10, 2019 at 3:04 PM Biju Das wrote:
> > Subject: Re: [PATCH v3 1/2] arm64: dts: renesas: r8a774a1: Remove audio
> > port node
> > On Tue, Oct 8, 2019 at 3:43 PM Biju Das wrote:
> > > > Subject: Re: [PATCH v3 1/2] arm64: dts: renesas: r8a774a1: Remove
> > > > audio port node On Fri, Oct 4, 2019 at 4:53 PM Biju Das
> > > > wrote:
> > > > > This patch removes audio port node from SoC device tree.
> > > >
> > > > Standard review comment: "Why?"
> >
> > Bcause it fixes a dtb warning?
> >
> >Warning (unit_address_vs_reg): /soc/sound@ec50/ports/port@0:
> > node has
> >a unit name, but no reg property
>
> I also noticed this warning.
>
> We will get this warning, if we apply the patch "[v3,2/2] arm64: dts:
> renesas: r8a774b1: Add Sound and Audio DMAC
> device nodes" first and then this one.
>
> If it is other way around, then there won't be any warning. That is the
> reason I didn't mention it in the commit message.
I even see the warning with current renesas-devel ("make dtbs W=1"),
which does not have "[v3,2/2] arm64: dts: renesas: r8a774b1: Add Sound
and Audio DMAC device nodes" yet.
So I'll apply this patch with the warning message in the commit log, unless
I'm missing something?
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Re: [PATCH v3 1/2] arm64: dts: renesas: r8a774a1: Remove audio port node
Hi Biju,
On Tue, Oct 8, 2019 at 3:43 PM Biju Das wrote:
> > Subject: Re: [PATCH v3 1/2] arm64: dts: renesas: r8a774a1: Remove audio
> > port node
> > On Fri, Oct 4, 2019 at 4:53 PM Biju Das wrote:
> > > This patch removes audio port node from SoC device tree.
> >
> > Standard review comment: "Why?"
Bcause it fixes a dtb warning?
Warning (unit_address_vs_reg): /soc/sound@ec50/ports/port@0: node has
a unit name, but no reg property
> >
> > > Fixes: e2f04248fcd4 ("arm64: dts: renesas: r8a774a1: Add audio
> > > support")
> > > Signed-off-by: Biju Das
> > > ---
> > > V1-->V2
> > > * New patch.
> > > V2-->V3
> > > * Fixed the commit message. Thanks to Fabrizio.
> > >
> > > This patch depend upon
> > > https://patchwork.kernel.org/project/linux-renesas-soc/list/?series=18
> > > 2581
> >
> > Why the dependency?
> > This looks like a fix for r8a774a1, too?
>
> Sorry, the above dependency is for the second patch.
> "[v3,2/2] arm64: dts: renesas: r8a774b1: Add Sound and Audio DMAC device
> nodes"
OK.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Re: [PATCH net-next 2/3] dt-bindings: can: rcar_canfd: document r8a774b1 support
Hi Fabrizio,
On Thu, Oct 10, 2019 at 2:37 PM Fabrizio Castro
wrote:
> Document the support for rcar_canfd on R8A774B1 SoC devices.
>
> Signed-off-by: Fabrizio Castro
Thanks for your patch!
> --- a/Documentation/devicetree/bindings/net/can/rcar_canfd.txt
> +++ b/Documentation/devicetree/bindings/net/can/rcar_canfd.txt
> @@ -5,6 +5,7 @@ Required properties:
> - compatible: Must contain one or more of the following:
>- "renesas,rcar-gen3-canfd" for R-Car Gen3 and RZ/G2 compatible
> controllers.
>- "renesas,r8a774a1-canfd" for R8A774A1 (RZ/G2M) compatible controller.
> + - "renesas,r8a774b1-canfd" for R8A774B1 (RZ/G2N) compatible controller.
>- "renesas,r8a774c0-canfd" for R8A774C0 (RZ/G2E) compatible controller.
>- "renesas,r8a7795-canfd" for R8A7795 (R-Car H3) compatible controller.
>- "renesas,r8a7796-canfd" for R8A7796 (R-Car M3-W) compatible controller.
The above looks good, but I think you forgot to add R8A774B1 to the
paragraph talking about the CAN FD clock below.
With that fixed:
Reviewed-by: Geert Uytterhoeven
While at it, the example in the bindings says the CANFD clock should be
configured to 40 MHz, which matches what is used in the various DTS files.
However, the Hardware User's Manual states it should be 80 MHz, except
for R-Car D3.
Is that correct?
Thanks!
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Re: [PATCH net-next 1/3] dt-bindings: can: rcar_can: Add r8a774b1 support
On Thu, Oct 10, 2019 at 2:37 PM Fabrizio Castro
wrote:
> Document RZ/G2N (r8a774b1) SoC specific bindings.
>
> Signed-off-by: Fabrizio Castro
Reviewed-by: Geert Uytterhoeven
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Re: [PATCH] arm64: dts: renesas: r8a774b1-hihope-rzg2n: Enable HS400 mode
On Mon, Sep 30, 2019 at 12:03 PM Biju Das wrote:
> This patch enables HS400 mode on HiHope RZ/G2N board.
>
> Signed-off-by: Biju Das
Reviewed-by: Geert Uytterhoeven
i.e. will queue in renesas-devel for v5.5.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Re: [PATCH v3 8/9] arm64: dts: renesas: hihope-rzg2-ex: Add LVDS support
On Wed, Oct 2, 2019 at 5:21 PM Biju Das wrote:
> This patch adds LVDS support for RZ/G2[MN] boards.
>
> Signed-off-by: Biju Das
> Reviewed-by: Laurent Pinchart
Reviewed-by: Geert Uytterhoeven
i.e. will queue in renesas-devel for v5.5.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Re: [PATCH 7/7] arm64: dts: renesas: hihope-rzg2-ex: Let the board specific DT decide about pciec1
On Fri, Oct 4, 2019 at 10:36 AM Fabrizio Castro
wrote:
> The plan for the HiHope RZ/G2N board is to enable pciec0 by default,
> and use pciec1 physical interface for SATA (as SATA and PCIE1 share
> the same physical interface), therefore move pciec1 enabling away
> from hihope-rzg2-ex.
>
> Signed-off-by: Fabrizio Castro
Reviewed-by: Geert Uytterhoeven
i.e. will queue in renesas-devel for v5.5.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Re: [PATCH v3 7/9] arm64: dts: renesas: hihope-rzg2-ex: Enable backlight
On Wed, Oct 2, 2019 at 5:21 PM Biju Das wrote:
> This patch enables backlight support.
>
> Signed-off-by: Biju Das
> Reviewed-by: Laurent Pinchart
Reviewed-by: Geert Uytterhoeven
i.e. will queue in renesas-devel for v5.5.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Re: [PATCH v3 1/9] arm64: dts: renesas: hihope-common: Move du clk properties out of common dtsi
On Wed, Oct 2, 2019 at 5:20 PM Biju Das wrote:
> RZ/G2N board is pin compatible with RZ/G2M board. However on the SoC
> side RZ/G2N uses DU3 where as RZ/G2M uses DU2 for the DPAD. In order to
> reuse the common dtsi for both the boards, it is required to move du clock
> properties from common dtsi to board specific dts.
>
> Signed-off-by: Biju Das
> Reviewed-by: Laurent Pinchart
Reviewed-by: Geert Uytterhoeven
i.e. will queue in renesas-devel for v5.5.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Re: [PATCH v3 2/2] arm64: dts: renesas: r8a774b1: Add Sound and Audio DMAC device nodes
On Fri, Oct 4, 2019 at 4:53 PM Biju Das wrote:
> Based on a similar patch of the R8A7796 device tree
> by Kuninori Morimoto .
>
> Signed-off-by: Biju Das
Reviewed-by: Geert Uytterhoeven
i.e. will queue in renesas-devel for v5.5.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Re: [PATCH 6/7] arm64: dts: renesas: r8a774b1: Add PCIe device nodes
On Fri, Oct 4, 2019 at 10:36 AM Fabrizio Castro
wrote:
> This patch adds PCIe{0,1} device nodes for R8A774B1 SoC.
>
> Signed-off-by: Fabrizio Castro
Reviewed-by: Geert Uytterhoeven
i.e. will queue in renesas-devel for v5.5.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Re: [PATCH 5/7] arm64: dts: renesas: r8a774b1: Add all MSIOF nodes
On Fri, Oct 4, 2019 at 10:36 AM Fabrizio Castro
wrote:
> Add the device nodes for all MSIOF SPI controllers on the RZ/G2N
> SoC (a.k.a. r8a774b1).
>
> Signed-off-by: Fabrizio Castro
Reviewed-by: Geert Uytterhoeven
i.e. will queue in renesas-devel for v5.5.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Re: [PATCH 4/7] arm64: dts: renesas: r8a774b1: Add RWDT node
On Fri, Oct 4, 2019 at 10:36 AM Fabrizio Castro
wrote:
> Populate the device tree node for the Watchdog Timer (RWDT)
> controller on the Renesas RZ/G2N (r8a774b1) SoC.
>
> Signed-off-by: Fabrizio Castro
Reviewed-by: Geert Uytterhoeven
i.e. will queue in renesas-devel for v5.5.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Re: [PATCH v3 6/9] arm64: dts: renesas: r8a774b1: Add PWM device nodes
On Wed, Oct 2, 2019 at 5:21 PM Biju Das wrote:
> This patch adds PWM device nodes to r8a774b1 SoC DT.
>
> Signed-off-by: Biju Das
> Reviewed-by: Laurent Pinchart
Reviewed-by: Geert Uytterhoeven
i.e. will queue in renesas-devel for v5.5.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Re: [PATCH v3 5/9] arm64: dts: renesas: r8a774b1: Add FDP1 device nodes
On Wed, Oct 2, 2019 at 5:21 PM Biju Das wrote:
> The r8a774b1 has a single FDP1 instance.
>
> Signed-off-by: Biju Das
> Reviewed-by: Laurent Pinchart
Reviewed-by: Geert Uytterhoeven
i.e. will queue in renesas-devel for v5.5.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Re: [PATCH v3 4/9] arm64: dts: renesas: r8a774b1-hihope-rzg2n: Add display clock properties
On Wed, Oct 2, 2019 at 5:20 PM Biju Das wrote:
> Add display clock properties for the HiHope RZ/G2N board.
>
> Signed-off-by: Biju Das
> Reviewed-by: Laurent Pinchart
Reviewed-by: Geert Uytterhoeven
i.e. will queue in renesas-devel for v5.5.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Re: [PATCH v3 3/9] arm64: dts: renesas: r8a774b1: Add HDMI encoder instance
On Wed, Oct 2, 2019 at 5:20 PM Biju Das wrote:
> Add the HDMI encoder to the R8A774B1 DT in disabled state.
>
> Signed-off-by: Biju Das
> Reviewed-by: Laurent Pinchart
Reviewed-by: Geert Uytterhoeven
i.e. will queue in renesas-devel for v5.5.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Re: [PATCH v3 2/9] arm64: dts: renesas: r8a774b1: Add DU device to DT
On Wed, Oct 2, 2019 at 5:20 PM Biju Das wrote:
> Add the DU device to r8a774b1 SoC DT.
>
> Signed-off-by: Biju Das
> Reviewed-by: Laurent Pinchart
Reviewed-by: Geert Uytterhoeven
i.e. will queue in renesas-devel for v5.5.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Re: [PATCH 7/7] arm64: dts: renesas: r8a774b1: Connect Ethernet-AVB to IPMMU-DS0
On Tue, Sep 24, 2019 at 10:23 AM Biju Das wrote:
> Add IPMMU-DS0 to the Ethernet-AVB device node.
>
> Based on work by Magnus Damm for the r8a7795.
>
> Signed-off-by: Biju Das
Reviewed-by: Geert Uytterhoeven
i.e. will queue in renesas-devel for v5.5.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Re: [PATCH 6/7] arm64: dts: renesas: r8a774b1: Tie SYS-DMAC to IPMMU-DS0/1
On Tue, Sep 24, 2019 at 10:23 AM Biju Das wrote:
> Hook up r8a774b1 DMAC nodes to the IPMMUs. In particular SYS-DMAC0
> gets tied to IPMMU-DS0, and SYS-DMAC1 and SYS-DMAC2 get tied to IPMMU-DS1.
>
> Based on work for the r8a7796 by Magnus Damm.
>
> Signed-off-by: Biju Das
Reviewed-by: Geert Uytterhoeven
i.e. will queue in renesas-devel for v5.5.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Re: [PATCH 5/7] arm64: dts: renesas: r8a774b1: Add VSP instances
On Tue, Sep 24, 2019 at 10:23 AM Biju Das wrote:
> The r8a774b1 has 4 VSP instances.
>
> Based on the work done for r8a77965 SoC.
>
> Signed-off-by: Biju Das
Reviewed-by: Geert Uytterhoeven
i.e. will queue in renesas-devel for v5.5.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Re: [PATCH 4/7] arm64: dts: renesas: r8a774b1: Add FCPF and FCPV instances
On Tue, Sep 24, 2019 at 10:23 AM Biju Das wrote:
> Add FCPF and FCPV instances to the r8a774b1 dtsi.
>
> Based on the work done for r8a77965 SoC.
>
> Signed-off-by: Biju Das
Reviewed-by: Geert Uytterhoeven
i.e. will queue in renesas-devel for v5.5.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Re: [PATCH 3/7] arm64: dts: renesas: r8a774b1: Add IPMMU device nodes
On Tue, Sep 24, 2019 at 10:23 AM Biju Das wrote:
> Add RZ/G2N (R8A774B1) IPMMU nodes.
>
> Signed-off-by: Biju Das
Reviewed-by: Geert Uytterhoeven
i.e. will queue in renesas-devel for v5.5.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Re: [PATCH 2/7] arm64: dts: renesas: r8a774b1: Add I2C and IIC-DVFS support
On Tue, Sep 24, 2019 at 10:23 AM Biju Das wrote:
> Add the I2C[0-6] and IIC Bus Interface for DVFS (IIC for DVFS)
> devices nodes to the r8a774b1 device tree.
>
> Signed-off-by: Biju Das
Reviewed-by: Geert Uytterhoeven
i.e. will queue in renesas-devel for v5.5.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Re: [PATCH 1/7] arm64: dts: renesas: r8a774b1: Add SDHI support
On Tue, Sep 24, 2019 at 10:23 AM Biju Das wrote:
> Add SDHI support for the r8a774b1 SoC.
>
> Signed-off-by: Biju Das
Reviewed-by: Geert Uytterhoeven
i.e. will queue in renesas-devel for v5.5.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Re: [PATCH 4/4] arm64: dts: renesas: r8a774b1: Add TMU device nodes
On Mon, Sep 23, 2019 at 4:57 PM Biju Das wrote:
> This patch adds TMU[01234] device tree nodes to the
> r8a774b1 SoC specific DT.
>
> Signed-off-by: Biju Das
Reviewed-by: Geert Uytterhoeven
i.e. will queue in renesas-devel for v5.5.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Re: [PATCH 3/4] arm64: dts: renesas: r8a774b1: Add CMT device nodes
On Mon, Sep 23, 2019 at 4:57 PM Biju Das wrote:
> This patch adds the CMT[0123] device tree nodes to the
> r8a774b1 SoC specific DT.
>
> Signed-off-by: Biju Das
Reviewed-by: Geert Uytterhoeven
i.e. will queue in renesas-devel for v5.5.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Re: [PATCH 2/4] arm64: dts: renesas: r8a774b1: Add RZ/G2N thermal support
On Mon, Sep 23, 2019 at 4:57 PM Biju Das wrote:
> Add thermal support for R8A774B1 (RZ/G2N) SoC.
>
> Based on the work done for r8a77965 SoC.
>
> Signed-off-by: Biju Das
Reviewed-by: Geert Uytterhoeven
i.e. will queue in renesas-devel for v5.5.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Re: [PATCH 1/4] arm64: dts: renesas: r8a774b1: Add OPPs table for cpu devices
On Mon, Sep 23, 2019 at 4:57 PM Biju Das wrote:
> This patch adds OPPs table for CA57{0,1} cpu devices.
>
> Signed-off-by: Biju Das
Reviewed-by: Geert Uytterhoeven
i.e. will queue in renesas-devel for v5.5.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Re: [PATCH v2 5/5] arm64: dts: renesas: Add HiHope RZ/G2N sub board support
On Mon, Sep 30, 2019 at 10:19 AM Biju Das wrote:
> The HiHope RZ/G2N sub board sits below the HiHope RZ/G2N main board.
>
> Signed-off-by: Biju Das
Reviewed-by: Geert Uytterhoeven
i.e. will queue in renesas-devel for v5.5.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Re: [PATCH v2 4/5] arm64: dts: renesas: r8a774b1: Add Ethernet AVB node
On Mon, Sep 30, 2019 at 10:19 AM Biju Das wrote:
> This patch adds the SoC specific part of the Ethernet AVB
> device tree node.
>
> Signed-off-by: Biju Das
Reviewed-by: Geert Uytterhoeven
i.e. will queue in renesas-devel for v5.5.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Re: [PATCH v2 3/5] arm64: dts: renesas: r8a774b1: Add GPIO device nodes
On Mon, Sep 30, 2019 at 10:19 AM Biju Das wrote:
> Add GPIO device nodes to the DT of the r8a774b1 SoC.
>
> Signed-off-by: Biju Das
Reviewed-by: Geert Uytterhoeven
i.e. will queue in renesas-devel for v5.5.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Re: [PATCH v2 2/5] arm64: dts: renesas: r8a774b1: Add SCIF and HSCIF nodes
On Mon, Sep 30, 2019 at 10:19 AM Biju Das wrote:
> Add the device nodes for RZ/G2N SCIF and HSCIF serial ports,
> including clocks, power domains and DMAs.
>
> Signed-off-by: Biju Das
Reviewed-by: Geert Uytterhoeven
i.e. will queue in renesas-devel for v5.5.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Re: [PATCH v2 1/5] arm64: dts: renesas: r8a774b1: Add SYS-DMAC device nodes
On Mon, Sep 30, 2019 at 10:19 AM Biju Das wrote:
> Add sys-dmac[0-2] device nodes for RZ/G2N (R8A774B1) SoC.
>
> Signed-off-by: Biju Das
Reviewed-by: Geert Uytterhoeven
i.e. will queue in renesas-devel for v5.5.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Re: [PATCH v3] PCI: rcar: Fix missing MACCTLR register setting in rcar_pcie_hw_init()
Hi Shimoda-san,
On Wed, Oct 9, 2019 at 1:05 PM Yoshihiro Shimoda
wrote:
> According to the R-Car Gen2/3 manual, the bit 0 of MACCTLR register
> should be written to 0 before enabling PCIETCTLR.CFINIT because
> the bit 0 is set to 1 on reset. To avoid unexpected behaviors from
> this incorrect setting, this patch fixes it.
>
> Fixes: c25da4778803 ("PCI: rcar: Add Renesas R-Car PCIe driver")
> Cc: # v3.16+
> Signed-off-by: Yoshihiro Shimoda
> Reviewed-by: Sergei Shtylyov
> Reviewed-by: Geert Uytterhoeven
> ---
> Changes from v2:
> - Change the subject.
> - Fix commit log again.
> - Add the register setting into the initialization, instead of speedup.
> - Change commit hash/target version on Fixes and Cc stable tags.
> - Add Geert-san's Reviewed-by.
> https://patchwork.kernel.org/patch/11180429/
Thanks for the update!
> --- a/drivers/pci/controller/pcie-rcar.c
> +++ b/drivers/pci/controller/pcie-rcar.c
> @@ -93,6 +93,7 @@
> #define LINK_SPEED_2_5GTS (1 << 16)
> #define LINK_SPEED_5_0GTS (2 << 16)
> #define MACCTLR0x011058
> +#define MACCTLR_RESERVED BIT(0)
> #define SPEED_CHANGE BIT(24)
> #define SCRAMBLE_DISABLE BIT(27)
> #define PMSR 0x01105c
> @@ -615,6 +616,8 @@ static int rcar_pcie_hw_init(struct rcar_pcie *pcie)
> if (IS_ENABLED(CONFIG_PCI_MSI))
> rcar_pci_write_reg(pcie, 0x801f, PCIEMSITXR);
>
> + rcar_rmw32(pcie, MACCTLR, MACCTLR_RESERVED, 0);
> +
> /* Finish initialization - establish a PCI Express link */
> rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR);
I guess the same should be added to rcar_pcie_resume_noirq(),
as s2ram on R-Car Gen3 powers down the SoC?
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Re: [PATCH v2] PCI: rcar: Fix writing the MACCTLR register value
Hi Shimoda-san,
On Wed, Oct 9, 2019 at 6:03 AM Yoshihiro Shimoda
wrote:
> According to the R-Car Gen2/3 manual, the bit 0 of MACCTLR register
> should be written to 0 because the register is set to 1 on reset.
> To avoid unexpected behaviors from this incorrect setting, this
> patch fixes it.
>
> Fixes: b3327f7fae66 ("PCI: rcar: Try increasing PCIe link speed to 5 GT/s at
> boot")
> Cc: # v4.9+
> Signed-off-by: Yoshihiro Shimoda
> Reviewed-by: Sergei Shtylyov
Thanks for your patch!
This patch fixes the issue where the register is written, so
Reviewed-by: Geert Uytterhoeven
However, according to the R-Car H1, Gen2, and Gen3 Hardware User's
Manuals, this reserved bit should be cleared on initialization.
Are we sure that is guaranteed to happen? If the checks at the top of
rcar_pcie_force_speedup() trigger, the register is never written to,
and the bit may still be set?
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
