rnel/git/lee/mfd.git#for-mfd-next
- git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git#for-next
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with
lay: rcar-du: Add a VSP channel
index to the vsps DT property") says a backwards-compatibility mode can be
implemented, but I fail to see how this can work, as rcar_du_vsps_init()
will just return an error, which is propagated.
What am I missing?
Thanks!
Gr{oetje,eeting}s,
is called fdp1-0.
> DEF_MOD("scif5",202,R8A77965_CLK_S3D4),
> DEF_MOD("scif4",203,R8A77965_CLK_S3D4),
> DEF_MOD("scif3",204,R8A77965_CLK_S3D4),
Reviewed-by: Geert Uytterhoe
__clk_get_name(parent), 0,
> + base + 0x74, shift, 4, 0, table,
CPG_SD0CKCR instead of hardcoded 0x74?
> + _lock);
> +}
> +
> const struct cpg_mssr_info r8a7
RCAR_GP_PIN(1, 1),
> +};
> +static const unsigned int du_clk_in_1_mux[] = {
> + DU_DOTCLKIN1_MARK
> +};
Missing du_clk_in_0 (GP0_16)?
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@l
GROUP(i2c2_a),
> + SH_PFC_PIN_GROUP(i2c3),
> + SH_PFC_PIN_GROUP(i2c5),
Please move the above two lines down, to preserve sort order.
> SH_PFC_PIN_GROUP(i2c2_b),
> SH_PFC_PIN_GROUP(i2c6_a),
> SH_PFC_PIN_GROUP(i2c6_b),
Gr{oetje,eeting}s,
_clkenb_a_pins[] = {
> + RCAR_GP_PIN(0, 1),
> +};
> +
> +static const unsigned int vin5_clkenb_a_mux[] = {
> + VI5_CLKENB_A_MARK,
> +};
"A" groups without "B" groups? Usually we drop the "_A" suffix in that case.
They're actually named like tha
On Tue, Aug 28, 2018 at 6:37 AM Nguyen An Hoan wrote:
> From: Hoan Nguyen An
>
> Add Audio SSI pin support for r8a77965
>
> Signed-off-by: Hoan Nguyen An
Reviewed-by: Geert Uytterhoeven
i.e. will queue in sh-pfc-for-v4.20.
Gr{oetje,eeting}s,
G
Hi Hoan,
On Tue, Aug 28, 2018 at 6:37 AM Nguyen An Hoan wrote:
> From: Hoan Nguyen An
>
> Add Audio clock pin support for r8a77965
>
> Signed-off-by: Hoan Nguyen An
Thanks for the update!
Reviewed-by: Geert Uytterhoeven
i.e. will queue in sh-pfc-for-v4.20.
Gr
Hi Chris,
On Tue, Aug 28, 2018 at 12:13 AM Chris Brandt wrote:
> On Monday, August 27, 2018 1, Geert Uytterhoeven wrote:
> > Given the differences, and the limited amount of RAM on RZ/A2, I think you
> > would be better off with a separate renesas-cpg-stbcr driver, and an
> &
Hi Chris,
On Mon, Aug 27, 2018 at 6:59 PM Chris Brandt wrote:
> On Monday, August 27, 2018 1, Geert Uytterhoeven wrote:
> > Given the differences, and the limited amount of RAM on RZ/A2, I think you
> > would be better off with a separate renesas-cpg-stbcr driver, and an
> &
"ostm0", 306, R7S9210_CLK_P1C),
4. Your module clocks can use e.g. "36" instead of "306" (also in the DTS),
matching the datasheet.
> --- /dev/null
> +++ b/include/dt-bindings/clock/r7s9210-cpg-mssr.h
5. Almost all of this can stay the same, modulo so
Hi Hoan,
On Fri, Aug 17, 2018 at 5:03 AM Nguyen An Hoan wrote:
> From: Hoan Nguyen An
Thanks for your patch!
Reviewed-by: Geert Uytterhoeven
But I cannot apply it without your Signed-off-by.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Li
Hi Hoan,
On Fri, Aug 17, 2018 at 5:03 AM Nguyen An Hoan wrote:
> From: Hoan Nguyen An
Reviewed-by: Geert Uytterhoeven
But I cannot apply it without your Signed-off-by.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 --
> Will fix this and send v2.
No need for that, I can fix it up while applying.
> > > Signed-off-by: Biju Das
> > > Reviewed-by: Fabrizio Castro
Reviewed-by: Geert Uytterhoeven
i.e. will queue in sh-pfc-for-v4.2.0.
Gr{oetje,eeting}s,
Geer
On Mon, Aug 13, 2018 at 3:58 PM Biju Das wrote:
> Document PFC support for the R8A774A1 SoC.
>
> Signed-off-by: Biju Das
> Reviewed-by: Fabrizio Castro
Reviewed-by: Geert Uytterhoeven
i.e. will queue in sh-pfc-for-v4.2.0.
Gr{oetje,eeting}s,
Geer
o
> break anything.
For Salvator-X(S):
1. If you set SW5 and SW6 to their center positions, you can access I2C3 on
EXIO Connector D.
2. I2C5 is available on test points CP45/46.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyon
ored for the sake of staying in sync with the aforementioned commits.
>
> Signed-off-by: Eugeniu Rosca
Thanks for your patch, but please see commit 7628fa811b8af571 ("pinctrl:
sh-pfc: r8a77965: Add HSCIF pins, groups, and functions") in v4.19-rc1.
Gr{oetje,eeting}s,
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
t;GP_5_20", "GP_5_22";
>
> I am curious to know why only some of the pins used above appear here.
GP5_23 has an external 100K pull-up, GP5_{17,20,22} don't.
GP6_1[123] have external 1K + 2K pull-upps.
>
> > + bias-pull-up;
> > + };
> > +
Hi Sergei,
On Thu, Aug 23, 2018 at 10:56 AM Sergei Shtylyov
wrote:
> On 8/23/2018 11:52 AM, Geert Uytterhoeven wrote:
> >>> According to R-Car Gen3 HW manual rev1.00, R-Car M3-N has two CAN
> >>> interfaces, similar to H3, M3-W and other SoCs from the same family.
>
/* placeholder */
> > + status = "disabled";
> > + };
>
> This is probably more detail than is needed for a placeholder, but it
> looks correct so I think this is fine.
Indeed. Adding the "compatible" properties means
Hi Uli,
(with Khiem's address fixed (hopefully))
On Thu, Aug 23, 2018 at 10:22 AM Geert Uytterhoeven
wrote:
> On Fri, Aug 17, 2018 at 3:19 PM Ulrich Hecht wrote:
> > This series adds CPU idle support for H3 and M3-W. It's a straight
> > up-port from the BSP.
>
> T
ion that all M3ULCB boards have an ES1.0
> SoC?
Alternatively, is this something that can be handled in the kernel using
soc_device_match()?
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In persona
r backport
repository.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
On Tue, Jul 31, 2018 at 6:08 PM Geert Uytterhoeven
wrote:
> SH-Mobile AG5 and R-Car H1 SoCs are based on the Cortex-A9 MPCore, which
> includes a global timer.
>
> Enable the ARM global timer on these SoCs, which will be used for:
> - the scheduler clock, improving scheduler accu
rnel/git/lee/mfd.git#for-mfd-next
- git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git#for-next
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with tech
,65}*/salvator-x, there's also an MFD device (BD9571WMC PMIC)
on an i2c bus, inheriting NULL DMA masks from its parent, but it doesn't
have any subnodes in DT, and the warning isn't triggered neither.
Anyone with a clue?
Thanks!
Gr{oetje,eeting}s,
Geert
--
Geer
Hi Wolfram, Simon,
On Mon, Jul 30, 2018 at 9:34 AM Wolfram Sang
wrote:
> Add the nodes to enable SATA. Note that MD12 (SW12-7) must be switched
> off for that to work.
>
> Signed-off-by: Wolfram Sang
> Reviewed-by: Geert Uytterhoeven
> ---
>
> Changes since v1:
>
y take patches for upstream.
I do not maintain any source tree at elinux.org (which tree? AFAIK
there's no git repo
at elinux.org?).
Thanks for your understanding!
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m6
IP9_31_28
> + IP9_27_24
> + IP9_23_20
> + IP9_19_16
> + IP9_15_12
> + IP9_11_8
> + IP9_7_4
> + IP9_3_0 }
Should't that be IP10_...?
Also not present in the upstream version.
Gr{oetje,eeting}s,
Hi Chris,
On Wed, Aug 8, 2018 at 12:39 PM Chris Brandt wrote:
> On Wednesday, August 08, 2018, Geert Uytterhoeven wrote:
> > BTW, I guess earlycon also works on RZ/A2 with current tty-next or
> > latest renesas-drivers?
>
> I was using your RFC patches on top of the curren
On Mon, Aug 6, 2018 at 4:08 PM Geert Uytterhoeven
wrote:
> This RFC patch series was sparked by noticing that commit 2d4dd0da45401c7a
> ("serial: sh-sci: Allow for compressed SCIF address") broke earlycon
> support on most Renesas ARM SoCs using SCIF ports, and by the frag
Hi Chris,
On Wed, Aug 8, 2018 at 2:16 AM Chris Brandt wrote:
> On Tuesday, August 07, 2018, Geert Uytterhoeven wrote:
> > > I see that you added this:
> > >
> > > OF_EARLYCON_DECLARE(scif, "renesas,scif-r7s9210",
> > rza2_early_console_setup);
> &
Hi Chris,
On Tue, Aug 7, 2018 at 9:24 PM Chris Brandt wrote:
> On Monday, August 06, 2018 1, Geert Uytterhoeven wrote:
> > > I had a simple patch to add support for CONFIG_DEBUG_LL for RZ/A2
> > > because earlycon never worked because of RZ/A2's different register
> &
ank you, this merges cleanly into today's linux-next.
Let's see how that works out in two weeks ;-)
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myse
ff-by: Biju Das
> ---
> V1-->V2
> * Added gpio-reserved-ranges support for handling
> unused gpios.
> V2-->V3
> * Incorporated Geert's review comment.
Reviewed-by: Geert Uytterhoeven
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven --
The inconsistency started when suddenly SK was spelled out in full, with
"Premier" or "Pro" added to differentiate, and the need arose for a shorter
nickname, which became "ULCB"
> > and if we had such compatible driver/soc, it needs to match to all
On Tue, Aug 7, 2018 at 10:03 AM Biju Das wrote:
> Update the DT bindings documentation with the optional gpio-reserved-ranges
> properties.
>
> Signed-off-by: Biju Das
> Reviewed-by: Fabrizio Castro
Reviewed-by: Geert Uytterhoeven
Gr{oetje,eeting}s,
G
Hi Marek,
On Sat, Aug 4, 2018 at 6:38 PM Marek Vasut wrote:
> Add DA9063 PMIC node to the I2C bus.
>
> Signed-off-by: Marek Vasut
> Cc: Geert Uytterhoeven
> Cc: Kuninori Morimoto
> Cc: Simon Horman
> Cc: Wolfram Sang
> Cc: linux-renesas-soc@vger.kernel.org
> -
rently no driver seems to check for this.
I was mistaken in my earlier report about msm_pinmux_request
(this is pinmux_ops.request(), not gpio_chip.request()).
> Signed-off-by: Biju Das
> Reviewed-by: Fabrizio Castro
Reviewed-by: Geert Uytterhoeven
Gr{oetje,eeting}s,
s to move the assignment to chip->of_node from of_gpiochip_add()
> to gpiochip_add_data_with_key().
>
> Signed-off-by: Biju Das
Reviewed-by: Geert Uytterhoeven
Tested-by: Geert Uytterhoeven
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyo
ORESOURCE_MEM, 0);
> if (!res)
> return -EINVAL;
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when
seems to be fine.
> We only need the GPIO resume on specific boards. This is a seperate
> task. D'accord?
Thanks for testing!
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations wi
AN operation, or were you just fixing the
build failure?
In case of the latter, please just add minimal placeholders, like were present
for other device nodes in early versions of r8a77965.dtsi.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond
>
> > So more information is needed to convince me ;-)
>
> Here they are :)
With "platform", it doesn't do the full cycle.
Please try without that step, or do "echo none > /sys/power/pm_test".
Thanks!
Gr{oetje,eeting}s,
Geert
--
Geer
On Mon, Aug 6, 2018 at 1:13 PM Geert Uytterhoeven wrote:
> On Mon, Aug 6, 2018 at 12:38 PM Laurent Pinchart
> wrote:
> > On Sunday, 5 August 2018 02:11:02 EEST Eugeniu Rosca wrote:
> > > In the context of M3N-ULCB (RTP0RC77965SKBX010SA00) board bring-up, it's
> > >
Hi Laurent,
On Mon, Aug 6, 2018 at 4:40 PM Laurent Pinchart
wrote:
> On Monday, 6 August 2018 17:34:34 EEST Geert Uytterhoeven wrote:
> > On Mon, Aug 6, 2018 at 4:16 PM Laurent Pinchart wrote:
> > > On Monday, 6 August 2018 17:07:54 EEST Geert Uytterhoeven wrote:
> >
Hi Laurent,
On Mon, Aug 6, 2018 at 4:37 PM Laurent Pinchart
wrote:
> On Monday, 6 August 2018 17:07:51 EEST Geert Uytterhoeven wrote:
> > This RFC patch series was sparked by noticing that commit 2d4dd0da45401c7a
>
> Where can that commit be found ?
tty-next
> > (&
DECLARE() line that also filled in
the correct regtype.
BTW, it would have been very valuable to know that earlycon didn't work, as that
would have helped in avoiding the earlycon breakage on other parts.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lo
Hi Laurent,
On Mon, Aug 6, 2018 at 4:16 PM Laurent Pinchart
wrote:
> On Monday, 6 August 2018 17:07:54 EEST Geert Uytterhoeven wrote:
> > This reverts commit dfc80387aefb78161f83732804c6d01c89c24595.
> >
> > Deriving the proper regshift value from the register bloc
the compatible value instead.
This requires adding an entry for RZ/A2 serial ports, which use an
atypical regshift value.
On non-DT systems the regshift value is still derived from the register
block size, as before.
Signed-off-by: Geert Uytterhoeven
---
- Sato-san: I assume this fixes SCI on H8/300
2d4dd0da45401c7a ("serial: sh-sci: Allow for compressed
SCIF address") alternative,
3. Add an OF_EARLYCON_DECLARE() for RZ/A2, to fix earlycon on RZ/A2.
What do you think?
Thanks for your comments!
P.S. Apparently SCIx_SH4_SCIF_REGTYPE and SCIx_SH2_SCIF_FIFODATA_REGTYPE
This reverts commit dfc80387aefb78161f83732804c6d01c89c24595.
Deriving the proper regshift value from the register block size is
fragile, as it may have been rounded up.
Furthermore we will need plat_sci_port.regshift again.
Signed-off-by: Geert Uytterhoeven
---
arch/sh/kernel/cpu/sh3/setup
From: Yoshinori Sato
The first sh-sci port and earlycon use the same sci_port.
Hence after the initialization of the first port, earlycon may die.
Fis this by assigning a separate sci_port for earlycon.
Signed-off-by: Yoshinori Sato
[geert: Rebased, reworded]
Signed-off-by: Geert Uytterhoeven
entry for RZ/A2 SoCs that do need regshift 0.
Signed-off-by: Geert Uytterhoeven
Fixes: 2d4dd0da45401c7a ("serial: sh-sci: Allow for compressed SCIF address")
---
Tested on R-Car Gen2 and Gen3.
This depends on the previous patch. Else the kernel hangs when
initializing SCIF0 (why??).
--
ram aka a full PSCI system suspend?
I guess not, as it is supposed to fail without PCA9654 suspend/resume support...
So more information is needed to convince me ;-)
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.or
boW-G23S)
> > @@ -105,7 +105,7 @@ Boards:
> >- Lager (RTP0RC7790SEB00010S)
> > compatible = "renesas,lager", "renesas,r8a7790"
> >- M3ULCB (R-Car Starter Kit Pro, RTP0RC7796SKBX0010SA09 (M3 ES1.0))
> > -compatible = "renesas,m3ulcb",
d.
>
> The plan is to set "of_node" variable in driver. So that
> gpiochip_init_valid_mask() sets gpio_chip->need_valid_mask to true.
> What is your opinion on this?
Sounds fine to me.
You said on IRC that it currently crashes when "gpio-reserved-ranges" is used.
IMHO that'
On Mon, Jul 2, 2018 at 9:01 PM Rob Landley wrote:
> On 07/02/2018 04:50 AM, Geert Uytterhoeven wrote:
> > On Sun, Jul 1, 2018 at 7:27 PM Rob Landley wrote:
> >> On 06/29/2018 09:25 AM, Geert Uytterhoeven wrote:
> >>> The RX FIFO timer may be armed whe
Hi Biju,
On Thu, Aug 2, 2018 at 4:17 PM Biju Das wrote:
> Describe GPIO blocks in the R8A77470 device tree.
>
> Signed-off-by: Biju Das
> Reviewed-by: Fabrizio Castro
Thanks for your patch!
Reviewed-by: Geert Uytterhoeven
> --- a/arch/arm/boot/dts/r8a77470.dtsi
> +++ b
t;
> Signed-off-by: Biju Das
> Reviewed-by: Fabrizio Castro
> ---
> V1-->V2
> * Added OSC predividers, rename rint to .r
Thanks for the update!
Reviewed-by: Geert Uytterhoeven
I.e. will queue in clk-renesas-for-v4.20.
Gr{oetje,eeting}s,
Geert
--
Geer
Castro
> Reviewed-by: Geert Uytterhoeven
> ---
> V1--> V2
> * Removed internal clock POST2.
Thanks for the update!
Will queue in clk-renesas-for-v4.20.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge..
On Thu, Aug 2, 2018 at 4:17 PM Biju Das wrote:
> Update the DT bindings documentation with the optional gpio-reserved-ranges
> properties.
>
> Signed-off-by: Biju Das
> Reviewed-by: Fabrizio Castro
Reviewed-by: Geert Uytterhoeven
Gr{oetje,eeting}s,
for (offset = 0; offset < p->gpio_chip.ngpio; offset++) {
> mask = BIT(offset);
> + if (p->gpio_chip.valid_mask && (mask & p->bank_info.gpiomsk))
> + continue;
> +
Just do "if (!gpiochip_line_is_valid(chip, offset)) co
Hi Marek,
On Thu, Aug 2, 2018 at 3:56 PM Marek Vasut wrote:
> On 08/01/2018 02:32 PM, Geert Uytterhoeven wrote:
> > On Mon, Jul 30, 2018 at 1:18 PM Marek Vasut wrote:
> >> Add DA9063 PMIC node to the I2C bus.
> >>
> >> Signed-off-by: Marek Vasut
> >
- */
> > +static const unsigned int avb_col_pins[] = {
> > + RCAR_GP_PIN(5, 18),
> > +};
>
> I feel that I am missing something painfully obvious, but this does not
> seem to match page 4-36 of R01UH0695EJ0100 Rev.1.00 (Oct 13 2017).
Please ch
t; [wsa: rebased to upstream base]
> > Reviewed-by: Geert Uytterhoeven
> > Signed-off-by: Wolfram Sang
> > ---
> >
> > Changes since v1:
> > * sorted it according to address (Thanks, Geert!)
> > * added Geert's tag
> >
> > arch/a
;;
According to my schematics, the interrupt is connected to GP3_31?
> + interrupt-controller;
> +
> + wdt {
> + compatible = "dlg,da9063-watchdog";
> + };
> + };
> };
Gr{oetje,eeting}s,
Hi Marek,
On Mon, Jul 30, 2018 at 1:17 PM Marek Vasut wrote:
> Add DA9210 DVFS node to the I2C bus and link it to CPU0 for DVFS.
>
> Signed-off-by: Marek Vasut
Thanks for your patch!
Oneline-summary prefix should be "ARM: dts: gose:".
Reviewed-by: Geert Uytterhoeven
192,1, 192,1, },
> + { 2,192,1, 128,1, },
> + { 0, /* Prohibited setting */ },
> + { 2,192,1, 192,1, },
> +};
Please add the new OSC predividers. You're gonna need t
On Mon, Jul 30, 2018 at 9:54 AM Biju Das wrote:
> Signed-off-by: Biju Das
> Reviewed-by: Chris Paterson
Reviewed-by: Geert Uytterhoeven
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In pe
define R8A774A1_CLK_HDMI 40
> +#define R8A774A1_CLK_CSI0 41
> +#define R8A774A1_CLK_CP42
> +#define R8A774A1_CLK_POST2 43
POST2 is an internal clock, which doesn't need to be referred to from DT.
So please drop it from the bindings.
&
On Mon, Jul 30, 2018 at 9:54 AM Biju Das wrote:
> Add support for RZ/G2M (R8A774A1) SoC power areas to the R-Car SYSC
> driver.
>
> Signed-off-by: Biju Das
> Reviewed-by: Chris Paterson
Reviewed-by: Geert Uytterhoeven
Gr{oetje,eeting}s,
Geert
--
Gee
On Mon, Jul 30, 2018 at 9:54 AM Biju Das wrote:
> This patch adds power domain indices for RZ/G2M.
>
> Signed-off-by: Biju Das
> Reviewed-by: Chris Paterson
Reviewed-by: Geert Uytterhoeven
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's l
: single-core Cortex-A9 MPCore r4p1 (global timer not
documented),
- r8a7740: single-core Cortex-A9 r2p4,
- r8a7778: single-core Cortex-A9 r2p2-00rel0.
This has been tested on KZM-A9-GT (SH-Mobile AG5) and Marzen (R-Car H1).
Thanks for your comments!
Geert Uytterhoeven (4):
ARM: dts
to shmobile_init_delay() from
the corresponding machine vectors.
Note that when using an old DTB lacking the global timer, the kernel
will still work. However, loops-per-jiffies will no longer be preset,
and the delay loop will need to be calibrated during boot.
Signed-off-by: Geert Uytterhoeven
Add a device node for the global timer, which is part of the Cortex-A9
MPCore.
The global timer can serve as an accurate (3 ns) clock source for
scheduling and delay loops.
Signed-off-by: Geert Uytterhoeven
---
arch/arm/boot/dts/sh73a0.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff
The "TWD" clock is actually the Cortex-A9 MPCore "PERIPHCLK" clock,
which not only clocks the private timers and watchdogs (TWD), but also
the interrupt controller and global timer.
Hence rename it from "twd" to "periph".
Signed-off-by: Geert Uytterhoeven
Add a device node for the global timer, which is part of the Cortex-A9
MPCore.
The global timer can serve as an accurate (4 ns) clock source for
scheduling and delay loops.
Signed-off-by: Geert Uytterhoeven
---
arch/arm/boot/dts/r8a7779.dtsi | 8
1 file changed, 8 insertions(+)
diff
Presumable unused since commit c99cd90d98a98aa1 ("ARM: shmobile:
r8a7779: Remove legacy SoC code").
Signed-off-by: Geert Uytterhoeven
---
arch/arm/mach-shmobile/setup-r8a7779.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c
b/arch/arm/mac
t;
> are available in the git repository at:
>
> https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas-backport.git
> backport/v4.14.57/snapshot-to-v4.18-rc6+fixes-flattened
Thank you!
I subjected this to the same testing I do for each renesas-drivers release.
I have detected n
Hi Laurent,
On Wed, Jul 11, 2018 at 11:16 PM Laurent Pinchart
wrote:
> On Thursday, 5 July 2018 13:55:00 EEST Geert Uytterhoeven wrote:
> > On Thu, Jun 14, 2018 at 1:36 PM Simon Horman wrote:
> > > This series is comprised of backports to v4.14 of the following
>
/kernel/git/lee/mfd.git#for-mfd-next
- git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git#for-next
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations
for any signals that are muxed together (have the same interrupt
> number) simply register one handler.
>
> Signed-off-by: Chris Brandt
> Reviewed-by: Geert Uytterhoeven
> ---
> v2:
> * Removed - 1 from loop
> * Added Reviewed-by
> --- a/drivers/tty/serial/sh-sci.c
> +++ b/drive
t; + "sata0_devslp_b",
> +};
> +
Moving the above hunk to its correct destination while applying...
> static const char * const hscif0_groups[] = {
> "hscif0_data",
> "hscif0_clk",
Gr{oetje,eeting}s,
Geer
On Mon, Jul 30, 2018 at 8:22 PM Sergei Shtylyov
wrote:
> The CAN clock node should precede the "cpus" node in the R8A779{7|8}0
> device trees, according to the alphanumeric node sorting rule...
>
> Signed-off-by: Sergei Shtylyov
Reviewed-by: Geert Uytterhoev
Hi Shimoda-san,
On Tue, Jul 31, 2018 at 8:14 AM Yoshihiro Shimoda
wrote:
> > From: Geert Uytterhoeven, Sent: Tuesday, July 31, 2018 12:34 AM
> > On Mon, Jul 30, 2018 at 1:55 PM Yoshihiro Shimoda
> > wrote:
> > > This patch adds PWM device nodes and enables PWM3 and PW
mments and/or patch
description.
> Signed-off-by: Yoshihiro Shimoda
Reviewed-by: Geert Uytterhoeven
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself
On Mon, Jul 30, 2018 at 1:49 PM Yoshihiro Shimoda
wrote:
> From: Takeshi Kihara
>
> This patch adds PWM{0,1,2,3,4,5,6} pins, groups and functions to
> the R8A77990 SoC.
>
> Signed-off-by: Takeshi Kihara
> Signed-off-by: Yoshihiro Shimoda
Reviewed-by: Geert Uytterhoeven
On Mon, Jul 30, 2018 at 1:51 PM Yoshihiro Shimoda
wrote:
> This patch adds bindings for R-Car E3. No driver update is needed.
>
> Signed-off-by: Yoshihiro Shimoda
Reviewed-by: Geert Uytterhoeven
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots
470-iwg23s-sbc.dts
> @@ -46,6 +49,11 @@
> };
>
> {
> + avb_pins: avb {
> + groups = "avb_mdio", "avb_gmii_tx_rx";
avb_crs is wired, but deemed unused, right?
In that case:
Reviewed-by: Geert Uytterhoeven
> + fun
Hi Biju,
On Fri, Jul 27, 2018 at 11:29 AM Biju Das wrote:
>
> + sergie
>
> > -Original Message-
> > From: Biju Das [mailto:biju@bp.renesas.com]
> > Sent: 27 July 2018 10:22
> > To: Laurent Pinchart ; Geert
> > Uytterhoeven ; Linus Walleij
>
OBE_REGTYPE
Reviewed-by: Geert Uytterhoeven
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I
Hi Chris,
On Mon, Jul 30, 2018 at 2:33 PM Chris Brandt wrote:
> On Monday, July 30, 2018, Geert Uytterhoeven wrote:
> > > if (sci_port->irqs[0] < 0)
> > > return -ENXIO;
> > >
> > > - if (sci_port->irqs[1] < 0) {
On Fri, Jul 27, 2018 at 11:57 AM Biju Das wrote:
> Specify EtherAVB PHY IRQ in the board specific device tree, now that we
> have GPIO support.
>
> Signed-off-by: Biju Das
> Reviewed-by: Fabrizio Castro
Reviewed-by: Geert Uytterhoeven
Gr{oetje,eeting}s,
to 27..29!
A simple way to work around this is to set ngpios to the highest bit number
in use + 1. But you still need a mechanism to avoid accessing the unused
bits in the gap between 16 and 27.
>
> if (*npins == 0 || *npins > RCAR_MAX_GPIO_PER_BANK) {
> dev_warn(>
not review the actual values.
Acked-by: Geert Uytterhoeven
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to j
ymore.
> So, this patch removes the rcar_dmac_sync_tcr().
>
> Fixes: 73a47bd0da66 ("dmaengine: rcar-dmac: use TCRB instead of TCR for
> residue")
> Signed-off-by: Yoshihiro Shimoda
> Tested-by: Hiroyuki Yokoyama
Makes sense, so
Reviewed-by: Geert Uytterhoeven
Gr{oetje,ee
;irqs) - 1; i++)
Shouldn't the "- 1" be dropped?
> + sci_port->irqs[i] = sci_port->irqs[0];
>
> sci_port->params = sci_probe_regmap(p);
> if (unlikely(sci_port->params == NULL))
With the above fixed:
Reviewed-by: Geert Uytterhoeven
501 - 600 of 5331 matches
Mail list logo
