DTB with no problems, so the HW is fine.
However, I can't seem to boot an upstream kernel (Linus master or
soc-for-v4.17 branch) on it. I just get total silence on the UART
after u-boot.
Any tips or ideas for me to try?
Many thanks,
Gilad
--
Gilad Ben-Yossef
Chief Coffee Drinker
"If you
On Thu, May 10, 2018 at 11:19 AM, Magnus Damm <magnus.d...@gmail.com> wrote:
> Hi Gilad,
>
> Thanks for your email.
>
> On Thu, May 10, 2018 at 5:12 PM, Gilad Ben-Yossef <gi...@benyossef.com> wrote:
>> Hi there,
>>
>> I am trying to add support fo
On Mon, May 14, 2018 at 5:29 PM, Geert Uytterhoeven
<ge...@linux-m68k.org> wrote:
> Hi Gilad,
>
> On Thu, May 10, 2018 at 10:12 AM, Gilad Ben-Yossef <gi...@benyossef.com>
> wrote:
>> I am trying to add support for the CryptoCell security IP in the
>> R-
On Tue, May 15, 2018 at 5:47 PM, Geert Uytterhoeven
<ge...@linux-m68k.org> wrote:
> Hi Gilad,
>
> On Tue, May 15, 2018 at 2:29 PM, Gilad Ben-Yossef <gi...@benyossef.com> wrote:
>> This patch adds the clock used by the CryptoCell 630p instance in the SoC.
>>
>&
On Wed, May 16, 2018 at 10:43 AM, Simon Horman <ho...@verge.net.au> wrote:
> On Tue, May 15, 2018 at 04:50:44PM +0200, Geert Uytterhoeven wrote:
>> Hi Gilad,
>>
>> On Tue, May 15, 2018 at 2:29 PM, Gilad Ben-Yossef <gi...@benyossef.com>
>> wrote:
&g
Herbert,
On Tue, May 15, 2018 at 3:29 PM, Gilad Ben-Yossef <gi...@benyossef.com> wrote:
> We were using the content of the signature register as a sanity
> check for the hardware functioning but it turns out not all
> implementers use the same values so the check is giving f
On Thu, May 17, 2018 at 12:04 PM, Simon Horman <ho...@verge.net.au> wrote:
> On Thu, May 17, 2018 at 11:01:57AM +0300, Gilad Ben-Yossef wrote:
>> On Wed, May 16, 2018 at 10:43 AM, Simon Horman <ho...@verge.net.au> wrote:
>> > On Tue, May 15, 2018 at 04:50:44PM +
On Thu, May 17, 2018 at 1:16 PM, Geert Uytterhoeven
<ge...@linux-m68k.org> wrote:
> Hi Gilad,
>
> On Thu, May 17, 2018 at 10:01 AM, Gilad Ben-Yossef <gi...@benyossef.com>
> wrote:
>> On Wed, May 16, 2018 at 10:43 AM, Simon Horman <ho...@verge.net.au> wrote:
&g
On Thu, May 17, 2018 at 4:35 PM, Geert Uytterhoeven
<ge...@linux-m68k.org> wrote:
> Hi Gilad,
>
> On Thu, May 17, 2018 at 3:09 PM, Gilad Ben-Yossef <gi...@benyossef.com> wrote:
>> On Thu, May 17, 2018 at 1:16 PM, Geert Uytterhoeven
>> <ge...@linux-m68k.org> w
We were using the content of the signature register as a sanity
check for the hardware functioning but it turns out not all
implementers use the same values so the check is giving false
negative on certain SoCs and so we drop it.
Signed-off-by: Gilad Ben-Yossef <gi...@benyossef.com>
---
d
This patch adds the clock used by the CryptoCell 630p instance in the SoC.
Signed-off-by: Gilad Ben-Yossef <gi...@benyossef.com>
---
drivers/clk/renesas/r8a7795-cpg-mssr.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c
b/drivers/clk/renesas/r
Add bindings for CryptoCell instance in the SoC.
Signed-off-by: Gilad Ben-Yossef <gi...@benyossef.com>
---
arch/arm64/boot/dts/renesas/r8a7795.dtsi | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
b/arch/arm64/boot/dts/renesas/r8a779
The following patch set enables CryptoCell present in the Renesas
R-Car SoC.
Gilad Ben-Yossef (3):
crypto: ccree: drop signature register check
clk: renesas: r8a7795: Add ccree clock
arm64: dts: renesas: r8a7795: add ccree binding
arch/arm64/boot/dts/renesas/r8a7795.dtsi | 8
abort).
>
I was trying to do as you suggested but I didn't quite get what is the
dev_id (2nd) parameter to devm_clk_get parameter is supposed to be.
I see what of_clk_get() is doing, so can replicate that but it seems
an over kill.
Any ideas?
Thanks,
Gilad
--
Gilad Ben-Yossef
Chief Coffee Drink
The cache parameter register configuration was being too verbose.
Use dev_dbg() to only provide the information if needed.
Signed-off-by: Gilad Ben-Yossef <gi...@benyossef.com>
---
drivers/crypto/ccree/cc_driver.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/d
Use managed clock handling, differentiate between no clock (possibly OK)
and clock init failure (never OK) and correctly handle clock detection
being deferred.
Suggested-by: Geert Uytterhoeven <ge...@linux-m68k.org>
Signed-off-by: Gilad Ben-Yossef <gi...@benyossef.com>
---
drivers/
This patch adds the clock used by the CryptoCell 630p instance in the SoC.
Signed-off-by: Gilad Ben-Yossef <gi...@benyossef.com>
---
This patch depends upon the "clk: renesas: r8a7795: Add CR clock" patch
from Geert Uytterhoeven.
drivers/clk/renesas/r8a7795-cpg-mssr.c | 1 +
1
fields as indicated by Geert Uytterhoeven.
- Better clock enabling as suggested by Geert Uytterhoeven.
Note! the last two patches in the set depend on the
"clk: renesas: r8a7795: Add CR clock" patch from Geert Uytterhoeven.
Gilad Ben-Yossef (5):
crypto: ccree: correct host regs offse
Add bindings for CryptoCell instance in the SoC.
Signed-off-by: Gilad Ben-Yossef <gi...@benyossef.com>
---
arch/arm64/boot/dts/renesas/r8a7795.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
b/arch/arm64/boot/dts/renesas/r8a779
On Tue, May 22, 2018 at 10:48 AM, Geert Uytterhoeven
<ge...@linux-m68k.org> wrote:
> Hi Gilad,
>
> On Mon, May 21, 2018 at 3:43 PM, Gilad Ben-Yossef <gi...@benyossef.com> wrote:
>> On Thu, May 17, 2018 at 1:16 PM, Geert Uytterhoeven
>> <ge...@linux-m68k.org>
;)
Cc: sta...@vger.kernel.org
Signed-off-by: Gilad Ben-Yossef <gi...@benyossef.com>
---
drivers/crypto/ccree/cc_debugfs.c | 7 +--
drivers/crypto/ccree/cc_driver.c| 8 ++--
drivers/crypto/ccree/cc_driver.h| 2 ++
drivers/crypto/ccree/cc_host_regs.h | 6 --
4 files changed, 17
heory, at least. :-)
We've just in the middle of an office move here, but I hope things
will settle down during the ween and I'll be able to replicate your
test and see if I can advise better, but certainly using 4k encryption
section size is key, otherwise the overhead just kills everything.
Than
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