Hi Fabrizio,
Thank you for the patch.
On Thursday, 13 December 2018 22:23:27 EET Fabrizio Castro wrote:
> Add support for the RZ/G2E (R8A774C0) SoC to the R-Car DU driver.
>
> Signed-off-by: Fabrizio Castro
Reviewed-by: Laurent Pinchart
and applied to my tree.
> ---
> drive
Hi Fabrizio,
Thank you for the patch.
On Thursday, 13 December 2018 22:20:54 EET Fabrizio Castro wrote:
> The RZ/G2E (r8a774c0) supports two LVDS channels. Extend the binding to
> support them.
>
> Signed-off-by: Fabrizio Castro
Reviewed-by: Laurent Pinchart
and applie
iver in a similar fashion to what
s/what/what is/
> done for R-Car E3.
>
> Signed-off-by: Fabrizio Castro
Reviewed-by: Laurent Pinchart
and applied to my tree with the above fix.
> ---
> drivers/gpu/drm/rcar-du/rcar_lvds.c | 1 +
> 1 file changed, 1 insertion(+)
>
>
Hi Fabrizio,
Thank you for the patch.
On Thursday, 13 December 2018 22:20:24 EET Fabrizio Castro wrote:
> Document RZ/G1 and RZ/G2 support.
>
> Signed-off-by: Fabrizio Castro
Reviewed-by: Laurent Pinchart
And applied to my tree.
> ---
> Documentation/devicetree/bindings/med
Hi Fabrizio,
Thank you for the patch.
On Thursday, 13 December 2018 22:20:33 EET Fabrizio Castro wrote:
> Document RZ/G2 support.
>
> Signed-off-by: Fabrizio Castro
Reviewed-by: Laurent Pinchart
And applied to my tree.
> ---
> Documentation/devicetree/bindings/media/rene
ume cycle and that the chip
> is powered down during this cycle, so the configuration could get lost.
>
> Signed-off-by: Marek Vasut
> Cc: Alexey Firago
> Cc: Laurent Pinchart
> Cc: Michael Turquette
> Cc: Stephen Boyd
> Cc: linux-renesas-soc@vger.kernel.org
Reviewe
(SEL_PWM2_2)
> FM(SEL_PWM2_1)
FM(SEL_PWM2
> _3) +#define
> MOD_SEL0_18_17FM(SEL_PWM3_0) FM(SEL_PWM3_2)
> FM(SEL_PWM3_1)
FM(SEL_PWM3
> _3) #define MOD_SEL0_15 FM(SEL_IRQ_0_0) FM(SEL_IRQ_0_1)
> #define MOD_SEL0_14 FM(SEL_IRQ_1_0) FM(SEL_IRQ_1_1)
> #define MOD_SEL0_13 FM(SEL_IRQ_2_0) FM(SEL_IRQ_2_1)
--
Regards,
Laurent Pinchart
-
> -- diff --git a/drivers/media/i2c/adv748x/adv748x.h
> b/drivers/media/i2c/adv748x/adv748x.h index 0ee3b8d5c795..63a17c31c169
> 100644
> --- a/drivers/media/i2c/adv748x/adv748x.h
> +++ b/drivers/media/i2c/adv748x/adv748x.h
> @@ -220,6 +220,7 @@ struct adv748x_state {
> #define ADV748X_IO_10_CSI4_ENBIT(7)
> #define ADV748X_IO_10_CSI1_ENBIT(6)
> #define ADV748X_IO_10_PIX_OUT_EN BIT(5)
> +#define ADV748X_IO_10_CSI4_IN_SEL_AFE0x08
>
> #define ADV748X_IO_CHIP_REV_ID_1 0xdf
> #define ADV748X_IO_CHIP_REV_ID_2 0xe0
--
Regards,
Laurent Pinchart
t; struct v4l2_fract aspect_ratio;
>
> + struct adv748x_csi2 *tx;
> +
> struct {
> u8 edid[512];
> u32 present;
> @@ -148,6 +150,8 @@ struct adv748x_afe {
> struct v4l2_subdev sd;
> struct v4l2_mbus_framefmt format;
>
> + struct adv748x_csi2 *tx;
> +
> bool streaming;
> v4l2_std_id curr_norm;
> unsigned int input;
This may call for defining a common structure to store the common fields of
adv748x_hdmi and adv748x_afe. Out of scope for this patch, but please keep it
in mind.
Reviewed-by: Laurent Pinchart
--
Regards,
Laurent Pinchart
ndex b482c7fe6957..387002d6da65
> 100644
> --- a/drivers/media/i2c/adv748x/adv748x.h
> +++ b/drivers/media/i2c/adv748x/adv748x.h
> @@ -85,6 +85,7 @@ struct adv748x_csi2 {
> struct v4l2_ctrl_handler ctrl_hdl;
> struct v4l2_ctrl *pixel_rate;
> struct v4l2_sub
}
> >
> > if (enable)
> > flags = MEDIA_LNK_FL_ENABLED;
> >
> >return media_create_pad_link(&src->entity, src_pad,
> > &tx->sd.entity, ADV748X_CSI2_SINK,
> > flags);
dant ? (CSI-4Lane, RGB888 configuration?)
> >
> > The CSI-2 data lane configuration has been break out from this table
> > by Niklas' patches. I've tried also moving the format configuration
> > out of this, but I haven't sent that change. The HDMI vi
Hi Marek,
On Thursday, 13 December 2018 04:09:19 EET Marek Vasut wrote:
> On 12/12/2018 09:43 AM, Laurent Pinchart wrote:
> > On Wednesday, 12 December 2018 03:41:30 EET Marek Vasut wrote:
> >> Add simple suspend/resume handlers to the driver to restore the chip
> >>
ume cycle and that the chip
> is powered down during this cycle, so the configuration could get lost.
>
> Signed-off-by: Marek Vasut
> Cc: Alexey Firago
> Cc: Laurent Pinchart
> Cc: Michael Turquette
> Cc: Stephen Boyd
> Cc: linux-renesas-soc@vger.kernel.o
Hi Niklas,
On Tuesday, 11 December 2018 04:01:15 EET Niklas Söderlund wrote:
> On 2018-12-10 22:16:52 +0200, Laurent Pinchart wrote:
> > On Monday, 10 December 2018 16:53:55 EET Jacopo Mondi wrote:
> >> The PHTW selection algorithm implemented in rcsi2_phtw_write_mbps()
>
Hi Kieran,
Thank you for the patch.
On Friday, 7 December 2018 18:31:34 EET Kieran Bingham wrote:
> In the partition sizing the term 'prevents' is inappropriately
> pluralized. Simplify to 'prevent'.
>
> Signed-off-by: Kieran Bingham
Reviewed-by: Laurent P
{ .mbps = 700, .reg = 0x12 },
> + { .mbps = 750, .reg = 0x32 },
> + { .mbps = 800, .reg = 0x52 },
> + { .mbps = 850, .reg = 0x72 },
> + { .mbps = 900, .reg = 0x14 },
> + { .mbps = 950, .reg = 0x34 },
> + { .mbps = 1000, .reg = 0x54 },
> + { .mbps = 1050, .reg = 0x74 },
> { .mbps = 1125, .reg = 0x16 },
> { /* sentinel */ },
> };
--
Regards,
Laurent Pinchart
Hi Geert,
On Monday, 10 December 2018 14:30:22 EET Geert Uytterhoeven wrote:
> On Tue, Dec 4, 2018 at 6:36 PM Geert Uytterhoeven wrote:
> > On Sun, Nov 25, 2018 at 3:40 PM Laurent Pinchart wrote:
> >> Add the backlight device for the LVDS1 output, in preparation for
o_queue_late = 1;
> break;
> + case OPT_RESET_CONTROLS:
> + do_reset_controls = 1;
> + break;
> case OPT_REQUEUE_LAST:
> do_requeue_last = 1;
> break;
> @@ -2560,7 +2609,10 @@ int main(int argc, char *argv[])
> video_set_control(&dev, ctrl_name, ctrl_value);
>
> if (do_list_controls)
> - video_list_controls(&dev);
> + video_list_controls(&dev, false);
> +
> + if (do_reset_controls)
> + video_list_controls(&dev, true);
>
> if (do_enum_formats) {
> printf("- Available formats:\n");
--
Regards,
Laurent Pinchart
A typo in the adv7180 DT node prevents successful probing of the VIN.
Fix it.
Fixes: 6a0942c20f5c ("arm64: dts: renesas: draak: Describe CVBS input")
Signed-off-by: Laurent Pinchart
---
arch/arm64/boot/dts/renesas/r8a77995-draak.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletio
I on rcar_pwm_resume()
> pwm: rcar: remove legacy APIs
> pwm: rcar: add workaround to output "pseudo" low level
>
> drivers/pwm/pwm-rcar.c | 108 ++----
> 1 file changed, 62 insertions(+), 46 deletions(-)
For the whole seri
lations are similar, the main difference is the last line, and I
think yours read better.
From 22f7149916f590d3dbcc673dacc738441c741900 Mon Sep 17 00:00:00 2001
From: Laurent Pinchart
Date: Sun, 25 Nov 2018 16:02:39 +0200
Subject: [PATCH] pwm: rcar: Optimize rcar_pwm_get_clock_division()
Get rid of the loop over all possible d
fixed levels in the DU channels themselves through the DOFLR
group register. Use this to turn the DPAD on or off by driving fixed
signals at the output of any DU channel not routed to a DPAD output.
This doesn't affect the DU output signals going to other outputs.
Signed-off-by: Laurent Pin
Hi Kieran,
On Friday, 7 December 2018 14:34:58 EET Kieran Bingham wrote:
> On 25/11/2018 14:40, Laurent Pinchart wrote:
> > The rcar_du_crtc outputs field stores a bitmask of the outputs driven by
> > the CRTC. This changes based on the configuration requested by
> > users
Hi Kieran,
On Friday, 7 December 2018 14:50:47 EET Kieran Bingham wrote:
> On 25/11/2018 14:40, Laurent Pinchart wrote:
> > DU channels are routed to DPAD outputs in an SoC-dependent way. The
> > routing can be fixed (e.g. DU3 to DPAD0 on H3) or configurable (e.g. DU0
> > or
n. For this reason we currently hardcode the
> > clock source to the LVDS PLL clock if available, and allow flicker-free
> > selection of the external DOTCLKIN clock or CPG-generated clock
> > otherwise. A more dynamic clock selection process can be implemented
> > later if the
Hi Marek,
On Wednesday, 5 December 2018 14:29:22 EET Marek Vasut wrote:
> On 12/05/2018 06:21 AM, Laurent Pinchart wrote:
> > On Wednesday, 5 December 2018 01:48:01 EET Marek Vasut wrote:
> >> On 12/04/2018 09:52 PM, Stephen Boyd wrote:
> >>> Quoting Ma
Hi Marek,
On Wednesday, 5 December 2018 03:10:18 EET Marek Vasut wrote:
> On 12/03/2018 11:48 PM, Laurent Pinchart wrote:
> > On Tuesday, 4 December 2018 00:24:32 EET Marek Vasut wrote:
> >> On 12/03/2018 10:48 PM, Laurent Pinchart wrote:
> >>> On Monday, 3 De
int ret;
> >> +
> >> + regcache_cache_only(vc5->regmap, false);
> >> + ret = regcache_sync(vc5->regmap);
> >> + if (ret != 0) {
> >> + dev_err(dev, "Failed to restore register map: %d\n",
> >> ret);
> >> + return ret;
> >> + }
> >
> > Simplify to
> >
> > if (ret)
> >
> > dev_err()
> >
> > retun ret;
> >
> >> +
> >> + return 0;
> >> +}
> >> +#endif
> >> +
> >>
> >> static const struct vc5_chip_info idt_5p49v5923_info = {
> >>
> >> .model = IDT_VC5_5P49V5923,
> >> .clk_fod_cnt = 2,
--
Regards,
Laurent Pinchart
Hi Geert,
On Tuesday, 4 December 2018 21:45:10 EET Geert Uytterhoeven wrote:
> On Tue, Dec 4, 2018 at 7:51 PM Laurent Pinchart wrote:
> > On Tuesday, 4 December 2018 20:42:53 EET Geert Uytterhoeven wrote:
> > > On Tue, Dec 4, 2018 at 7:12 PM Laurent Pinchart wrote:
> > &g
Hi Geert,
On Tuesday, 4 December 2018 20:42:53 EET Geert Uytterhoeven wrote:
> On Tue, Dec 4, 2018 at 7:12 PM Laurent Pinchart wrote:
> > On Tuesday, 4 December 2018 19:30:25 EET Geert Uytterhoeven wrote:
> >> On Tue, Dec 4, 2018 at 5:36 PM Laurent Pinchart wrote:
> >&g
Hi Geert,
On Tuesday, 4 December 2018 19:30:25 EET Geert Uytterhoeven wrote:
> On Tue, Dec 4, 2018 at 5:36 PM Laurent Pinchart wrote:
> > Implement a .mode_valid() handler in the R-Car glue layer to reject
> > modes with an unsupported clock frequency.
> >
> > Sign
Hi Simon,
Could you please consider taking this patch in your tree ? It's independent
from the rest of the series.
On Sunday, 25 November 2018 16:40:30 EET Laurent Pinchart wrote:
> Add the backlight device for the LVDS1 output, in preparation for panel
> support.
>
> Signe
Implement a .mode_valid() handler in the R-Car glue layer to reject
modes with an unsupported clock frequency.
Signed-off-by: Laurent Pinchart
---
drivers/gpu/drm/rcar-du/rcar_dw_hdmi.c | 15 +++
1 file changed, 15 insertions(+)
Changes since v1:
- Add a comment to explain where
Hi Marek,
On Tuesday, 4 December 2018 00:24:32 EET Marek Vasut wrote:
> On 12/03/2018 10:48 PM, Laurent Pinchart wrote:
> > On Monday, 3 December 2018 17:12:41 EET Geert Uytterhoeven wrote:
> >> As of commit 6d2ca85279becdff ("dt-bindings: display: renesas: Deprecate
>
-off-by: Geert Uytterhoeven
> ---
> Compile-tested only.
I can't test the patch either but it looks fine to me.
Reviewed-by: Laurent Pinchart
I assume you will send this directly to Simon, so I don't plan to take the
patch in my tree.
> ---
> arch/arm64/boot/dts/renesas/r8
the patch either but it looks fine to me.
Reviewed-by: Laurent Pinchart
I assume you will send this directly to Simon, so I don't plan to take the
patch in my tree.
> ---
> arch/arm/boot/dts/r8a7790-stout.dts | 15 ---
> 1 file changed, 12 insertions(+), 3 deletions
an be set to fallback on.
>
> Signed-off-by: Niklas Söderlund
Reviewed-by: Laurent Pinchart
> ---
> * Changes since v3
> - Add paragraph to describe the accepted values for the source endpoint
> data-lane property. Thanks Jacopo for pointing this out and sorry for
> m
the patch, but this should be good
enough :-)
The result is nicer to read, thanks.
Reviewed-by: Laurent Pinchart
and taken in my tree.
> ---
> .../drm/rcar-du/rcar_du_of_lvds_r8a7790.dts | 93 +--
> .../drm/rcar-du/rcar_du_of_lvds_r8a7791.dts | 53 +--
&
fine with 4.15 kernel.
>
> Now as part of RZ/G1N vsp upstreaming, I rebased to latest branch from
> renesas-dev , and executed the same test case
>
> Only test cases in vsp test suite is working. the vspd test case is broken.
Could you please post the tests output and log ?
> So I am wondering how do we expose the r-car gen2 SoC feature "VSPD" to
> the end user?
Isn't the VSPD already exposed to the user as a V4L2 device on Gen2 ?
--
Regards,
Laurent Pinchart
ck/r8a7796-cpg-mssr.h | 2 +-
> include/dt-bindings/clock/r8a77995-cpg-mssr.h | 5 +++--
> 10 files changed, 18 insertions(+), 15 deletions(-)
--
Regards,
Laurent Pinchart
ssr: Add R8A77995 support")
> Signed-off-by: Geert Uytterhoeven
Reviewed-by: Laurent Pinchart
The patch has no effect on the DU operation as the rcar-du driver hardcodes a
different clock source for the dot clock. However, after hacking the driver to
hardcode usage of this clock, operati
hi Kihara
> Fixes: 3570a2af473789c5 ("clk: renesas: cpg-mssr: Add support for R-Car E3")
> Signed-off-by: Geert Uytterhoeven
Reviewed-by: Laurent Pinchart
> ---
> drivers/clk/renesas/r8a77990-cpg-mssr.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
&
ng calls in console_lock(), console_trylock() and
console_unlock() (kernel/printk/printk.c).
--
Regards,
Laurent Pinchart
95.048144] [drm] Initialized rcar-du 1.0.0 20130110 for
> feb0.display on minor 0
> [ 95.055907] [drm] Device feb0.display probed
> ...
>
> On 2018/11/26 17:21, Simon Horman wrote:
> > On Fri, Nov 23, 2018 at 01:48:08PM +0200, Laurent Pinchart wrote:
> >> Gro
DPAD1 source in a new dpad1_source
field which will move to a state structure with dpad0_source.
Signed-off-by: Laurent Pinchart
---
drivers/gpu/drm/rcar-du/rcar_du_crtc.c| 42 +++
drivers/gpu/drm/rcar-du/rcar_du_crtc.h| 7 ++--
drivers/gpu/drm/rcar-du/rcar_du_drv.h
the Draak board DT, in
order to test the series. Only patch 4/5 should be upstreamed at this time as
5/5 should be rewritten using DT overlays. It can be merged separately from
the rest of the series as code and DT are not dependent.
Laurent Pinchart (5):
drm: rcar-du: Replace EXT_CTRL_REGS
Signed-off-by: Laurent Pinchart
---
arch/arm64/boot/dts/renesas/r8a77995-draak.dts | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
index cd067319e6f3..140519e39f06 100644
--- a/arch
to fixed levels in the DU channels themselves through the DOFLR
group register. Use this to turn the DPAD on or off by driving fixed
signals at the output of any DU channel not routed to a DPAD output.
This doesn't affect the DU output signals going to other outputs.
Signed-off-by: Laurent Pin
The RCAR_DU_FEATURE_EXT_CTRL_REGS feature flag is missing for H1 only,
which is a first generation device, not a second generation device as
reported in the device information table. Fix the H1 generation and use
generation checks to replace the feature flag.
Signed-off-by: Laurent Pinchart
Add the backlight device for the LVDS1 output, in preparation for panel
support.
Signed-off-by: Laurent Pinchart
---
.../arm64/boot/dts/renesas/r8a77995-draak.dts | 20 +++
1 file changed, 20 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
b/arch
Hi Kieran,
On Friday, 23 November 2018 17:30:43 EET Kieran Bingham wrote:
> On 23/11/2018 14:47, Laurent Pinchart wrote:
> > On Friday, 23 November 2018 16:43:28 EET Kieran Bingham wrote:
> >> On 23/11/2018 14:34, Laurent Pinchart wrote:
> >>> Implement a .mode_val
Hi Kieran,
On Friday, 23 November 2018 16:43:28 EET Kieran Bingham wrote:
> On 23/11/2018 14:34, Laurent Pinchart wrote:
> > Implement a .mode_valid() handler in the R-Car glue layer to reject
> > modes with an unsupported clock frequency.
> >
> > Sign
registers, and they might be improved, since you're rewriting
> this sequence anyhow.
>
> I had a patch pending, before I realized you could change this in your
> next v4. In case you want to have a look:
> https://paste.debian.net/1052965/
I would prefer fixes to be made on top of this patch, to separate the
refactoring from the functional changes as much as possible.
> > +
> > + /* ADI Required Write */
> > + adv748x_write_check(state, page, 0xc1, 0x3b, &ret);
> > +
> > + return ret;
> > +}
> >
> > int adv748x_tx_power(struct adv748x_csi2 *tx, bool on)
> > {
> > - struct adv748x_state *state = tx->state;
> > - const struct adv748x_reg_value *reglist;
> > int val;
> >
> > if (!is_tx_enabled(tx))
> > @@ -321,14 +329,7 @@ int adv748x_tx_power(struct adv748x_csi2 *tx, bool
> > on)
> > WARN_ONCE((on && val & ADV748X_CSI_FS_AS_LS_UNKNOWN),
> > "Enabling with unknown bit set");
> >
> > - if (on)
> > - reglist = is_txa(tx) ? adv748x_power_up_txa_4lane :
> > - adv748x_power_up_txb_1lane;
> > - else
> > - reglist = is_txa(tx) ? adv748x_power_down_txa_4lane :
> > - adv748x_power_down_txb_1lane;
> > -
> > - return adv748x_write_regs(state, reglist);
> > + return on ? adv748x_power_up_tx(tx) : adv748x_power_down_tx(tx);
> > }
> >
> > /* --
--
Regards,
Laurent Pinchart
Implement a .mode_valid() handler in the R-Car glue layer to reject
modes with an unsupported clock frequency.
Signed-off-by: Laurent Pinchart
---
drivers/gpu/drm/rcar-du/rcar_dw_hdmi.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/rcar-du/rcar_dw_hdmi.c
b
Hi Fabrizio,
On Thursday, 22 November 2018 17:59:32 EET Fabrizio Castro wrote:
> On 15 October 2018 23:25 Laurent Pinchart wrote:
> > On Friday, 21 September 2018 21:08:30 EEST Fabrizio Castro wrote:
> >> From: Biju Das
> >>
> >> Add support for the R8A7
Hi Fabrizio,
On Thursday, 22 November 2018 18:03:44 EET Fabrizio Castro wrote:
> On 17 October 2018 07:52 Laurent Pinchart wrote:
> > On Tuesday, 16 October 2018 19:58:59 EEST Fabrizio Castro wrote:
> > > Add RZ/G1C (a.k.a. r8a77470) support to the R-Car DU driver.
> &
5a9 ("drm: rcar-du: Cache DSYSR value to ensure known initial
value")
Reported-by: Hoan Nguyen An
Signed-off-by: Laurent Pinchart
---
drivers/gpu/drm/rcar-du/rcar_du_group.c | 21 ++---
1 file changed, 18 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/r
Hello Hoan,
On Tuesday, 23 October 2018 04:01:19 EET Hoan wrote:
> On 2018/10/22 20:23, Laurent Pinchart wrote:
> > On Monday, 22 October 2018 09:30:54 EEST Nguyen An Hoan wrote:
> >> From: Hoan Nguyen An
> >>
> >> From previous commit 0521ccb "
y down the road.
> }
>
> ret = drm_encoder_init(rcdu->ddev, encoder, &encoder_funcs,
--
Regards,
Laurent Pinchart
M3-N, V3M and V3H. Fix it.
Fixes: de2bc45c84f7 ("media: vsp1: Update LIF buffer thresholds")
Reported-by: Colin Ian King
Signed-off-by: Laurent Pinchart
---
drivers/media/platform/vsp1/vsp1_lif.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/media/platfor
The hardware requires the HDSR and VDSR registers to be set to 1 or
higher. This translates to a minimum combined horizontal sync and back
porch of 20 pixels and a minimum vertical back porch of 3 lines. Reject
modes that fail those requirements.
Signed-off-by: Laurent Pinchart
---
Changes since
Hi Kieran,
On Thursday, 20 September 2018 14:22:38 EET Laurent Pinchart wrote:
> On Wednesday, 19 September 2018 18:56:59 EEST Kieran Bingham wrote:
> > If the alpha property is not added to a plane, a default value will be
> > used, which can result in a non-visible layer
The hardware requires the HDSR and VDSR registers to be set to 1 or
higher. This translates to a minimum combined horizontal sync and back
porch of 20 pixels and a minimum vertical back porch of 3 lines. Reject
modes that fail those requirements.
Signed-off-by: Laurent Pinchart
---
drivers/gpu
,
> > took your configuration, enabled CONFIG_COMMON_CLK_VC5, and my
> > Salvator-XS H3 boots fine.
>
> I'm deeply sorry, it was my fault.
> I'm using ES1.x board, but I used XS dtb
I've done worse mistakes, and many times, so I can't blame you :-) I'm glad it
works now.
--
Regards,
Laurent Pinchart
upport for vblank timestamp query.
>
> ** stop here **
I'm afraid I can't reproduce this. I checked out renesas-drivers-2018-10-09-
v4.19-rc7, applied the fix I've submitted, took your configuration, enabled
CONFIG_COMMON_CLK_VC5, and my Salvator-XS H3 boots fine.
--
Regards,
Laurent Pinchart
a
> >
> > Signed-off-by: Takeshi Kihara
> > Signed-off-by: Jacopo Mondi
> > Reviewed-by: Laurent Pinchart
>
> Thanks,
>
> This looks fine to me but I will wait to see if there are other reviews
> before applying.
>
> Reviewed-by: Simon Horman
I think you can go ahead and apply it.
--
Regards,
Laurent Pinchart
Hi Morimoto-san,
On Tuesday, 6 November 2018 16:30:35 EET Laurent Pinchart wrote:
> On Thursday, 18 October 2018 05:12:14 EET Kuninori Morimoto wrote:
> > Hi Vladimir, Laurent
> >
> > I'm testing ULCB board, and I noticed that HDMI doen't work on it.
> >
&g
avoids a WARN_ON() at runtime.
Fixes: 1b30dbde8596 ("drm: rcar-du: Add support for external pixel clock")
Reported-by: Kuninori Morimoto
Signed-off-by: Laurent Pinchart
---
drivers/gpu/drm/rcar-du/rcar_du_crtc.c | 14 +-
1 file changed, 9 insertions(+), 5 deletions(-)
di
[]
irq_exit+0x12c/0x138
[1.879100] ---[ end trace ec07bda5b9bd7ef1 ]---
I'm now investigating it.
--
Regards,
Laurent Pinchart
-> v2:
> - Limit the PHTW table to 1125 MBps, according to Laurent's comment
Based on the assumption that the values haven't changed between v1 and v2,
Reviewed-by: Laurent Pinchart
> ---
> drivers/media/platform/rcar-vin/rcar-csi2.c | 62 --
>
ver fails to probe.
>
> Fixes: ec70407ae7d7 ("arm64: dts: renesas: r8a77990: Add VIN and CSI-2
> device nodes") Signed-off-by: Koji Matsuoka
> Signed-off-by: Takeshi Kihara
> Signed-off-by: Jacopo Mondi
Reviewed-by: Laurent Pinchart
> ---
> arch/arm64/boot/dts
0x76 },
> + { .mbps = 1349, .reg = 0x18 },
> + { .mbps = 1399, .reg = 0x38 },
> + { .mbps = 1449, .reg = 0x58 },
> + { .mbps = 1500, .reg = 0x78 },
> { /* sentinel */ },
> };
In the latest datasheet version I can find, the frequencies go up to 1125 MHz
only. I've verified values up to that point, but not beyond it.
--
Regards,
Laurent Pinchart
LD_NUM(2) | FLD_FLD_EN4 |
> FLD_FLD_EN3 | FLD_FLD_EN2 | FLD_FLD_EN);
> rcsi2_write(priv, VCDT_REG, vcdt);
> - rcsi2_write(priv, VCDT2_REG, vcdt2);
> + if (vcdt2)
I would write this as
if (priv->info->num_channels > 2)
in
nverting the tables into functions and
> using parameters the power up/down functions for TXA and TXB power
> up/down can be merged and used for both transmitters.
>
> Signed-off-by: Niklas Söderlund
Reviewed-by: Laurent Pinchart
The code looks so much better now :-)
> ---
>
return -EINVAL;
> + }
> +
> + state->txb.num_lanes = num_lanes;
> + adv_dbg(state, "TXB: using %u lanes\n", state->txb.num_lanes);
> + }
Should we set the number of lanes to 4 and 1 respecti
s to be reused when initializing the
> hardware reducing code duplicating as well aligning with the
> documentation.
>
> Signed-off-by: Niklas Söderlund
Reviewed-by: Laurent Pinchart
>
> ---
> * Changes since v2
> - Bring in the undocumented registers in the power on se
be set to fallback on.
>
> Signed-off-by: Niklas Söderlund
Reviewed-by: Laurent Pinchart
>
> ---
> * Changes since v2
> - Update paragraph according to Laurents comments.
> ---
> Documentation/devicetree/bindings/media/i2c/adv748x.txt | 4 +++-
> 1 file changed, 3 in
Hi Niklas,
On Friday, 2 November 2018 12:38:34 EET Niklas Söderlund wrote:
> On 2018-10-05 01:36:11 +0300, Laurent Pinchart wrote:
> > On Thursday, 4 October 2018 23:41:35 EEST Niklas Söderlund wrote:
> > > From: Niklas Söderlund
> > >
> > > Reorder the
Hi Jacopo,
On Tuesday, 30 October 2018 12:14:31 EET jacopo mondi wrote:
> On Mon, Sep 10, 2018 at 05:12:30PM +0300, Laurent Pinchart wrote:
> > On Wednesday, 5 September 2018 18:29:43 EEST Jacopo Mondi wrote:
> >> From: Koji Matsuoka
> >>
> >> Add device nod
t;>> On Mon, Oct 1, 2018 at 6:12 PM Noralf Trønnes wrote:
> >>>> Den 01.10.2018 13.56, skrev Laurent Pinchart:
> >>>>> On Monday, 1 October 2018 09:52:20 EEST Daniel Vetter wrote:
> >>>>>> On Fri, Sep 28, 2018 at 06:30:35PM +0300, Laurent P
start ? DSYSR_DEN : DSYSR_DRES);
> + rcar_du_group_write(rgrp, DSYSR,
> + (rcar_du_group_read(rgrp, DSYSR) & ~(DSYSR_DRES |
> DSYSR_DEN)) |
> + (start ? DSYSR_DEN : DSYSR_DRES));
> }
>
> void rcar_du_group_start_stop(struct rcar_du_group *rgrp, bool start)
--
Regards,
Laurent Pinchart
nd ec50.sound: probed
> [2.045763] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
> [2.052441] [drm] No driver support for vblank timestamp query.
> /* here kernel stop */
I will have a look.
--
Regards,
Laurent Pinchart
The M3-N (r8a77965) includes one LVDS encoder. Extend the binding to
support it.
Signed-off-by: Laurent Pinchart
---
.../devicetree/bindings/display/bridge/renesas,lvds.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/display/bridge/renesas
Hello,
This small patch series adds support for the M3-N internal LVDS encoder in the
DT bindings, the LVDS encoder driver and the M3-N .dtsi.
Please see individual patches for details.
The series is based on a merge of Simon's devel branch and the DRM -next
branch.
Laurent Pinchart (2):
Add support for the R-Car M3-N (R8A77965) SoC to the LVDS encoder
driver. The encoder appears identical to the M3-W version, we can thus
simply point to the generic Gen3 data.
Signed-off-by: Laurent Pinchart
---
drivers/gpu/drm/rcar-du/rcar_lvds.c | 1 +
1 file changed, 1 insertion(+)
diff
The M3-N (r8a77965) platform has oneLVDS encoder connected to the DU.
Add the corresponding DT node and wire it up.
Signed-off-by: Laurent Pinchart
---
arch/arm64/boot/dts/renesas/r8a77965.dtsi | 27 +++
1 file changed, 27 insertions(+)
diff --git a/arch/arm64/boot/dts
The drm_vblank_init() takes the total number of CRTCs as an argument,
but the rcar-du driver passes a bitmask of the CRTC indices. Fix it.
Fixes: 4bf8e1962f91 ("drm: Renesas R-Car Display Unit DRM driver")
Reported-by: Tomi Valkeinen
Signed-off-by: Laurent Pinchart
---
drivers/gpu/d
Hello,
On Wednesday, 17 October 2018 20:48:01 EEST Laurent Pinchart wrote:
> The LVDS0 encoder on Koelsh and Porter, and the LVDS1 encoder on Lager,
> are enabled in DT but have no device connected to their output. This
> result in spurious messages being printed to the kernel lo
by disabling the encoders.
Fixes: 15a1ff30d8f9 ("ARM: dts: r8a7790: Convert to new LVDS DT bindings")
Fixes: e5c3f4707f39 ("ARM: dts: r8a7791: Convert to new LVDS DT bindings")
Reported-by: Simon Horman
Signed-off-by: Laurent Pinchart
---
arch/arm/boot/dts/r8a7790-lager.dt
Hi Fabrizio,
Thank you for the patch.
On Tuesday, 16 October 2018 19:58:59 EEST Fabrizio Castro wrote:
> Add RZ/G1C (a.k.a. r8a77470) support to the R-Car DU driver.
>
> Signed-off-by: Fabrizio Castro
> Reviewed-by: Laurent Pinchart
>
> ---
> v1
Geert Uytterhoeven has long taken over and I'm not involved anymore with
the Renesas pinctrl driver. Remove myself from the maintainers list.
Signed-off-by: Laurent Pinchart
---
MAINTAINERS | 1 -
1 file changed, 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 69373eb
7;ret' instead to propagate the error code.
>
> Fixes: 47a52d024e89 ("media: drm: rcar-du: Add support for CRC computation")
> Signed-off-by: Christophe JAILLET
Reviewed-by: Laurent Pinchart
and applied to my tree.
> ---
> drivers/gpu/drm/rcar-du/rcar_du_crtc.
> >> not have lane remapping, the clock-lanes property is redundant.
> >
> > Uhm ... Niklas?
>
> The MAX9286 documentation contains information on lane remapping and
> support for any number (1-4) of enabled data-lanes. I have not tested if
> this works in practice but the registers are there and documented :-)
That's my understanding too. Clock lane remapping doesn't seem to be supported
though. We could thus omit the clock-lanes property.
--
Regards,
Laurent Pinchart
.routes = {
/*
-* R8A7743 has one RGB output and one LVDS output
+* R8A774[34] has one RGB output and one LVDS output
*/
[RCAR_DU_OUTPUT_DPAD0] = {
.possible_crtcs = BIT(1) | BIT(0),
W
/*
> + * R8A77470 has two RGB outputs, one LVDS output, and
> + * one analog video output (unsupported)
I'd write this "and one (currently unsupported) analog video output" to match
the other device entries. With this fixed,
Hi Fabrizio,
Thank you for the patch.
On Friday, 21 September 2018 21:08:28 EEST Fabrizio Castro wrote:
> From: Biju Das
>
> Document the RZ/G1N (R8A7744) SoC in the R-Car DU bindings.
>
> Signed-off-by: Biju Das
> Reviewed-by: Fabrizio Castro
Reviewed-by: Laurent Pinch
Hi Fabrizio,
Thank you for the patch.
On Friday, 21 September 2018 21:08:27 EEST Fabrizio Castro wrote:
> Document the RZ/G1C (r8a77470) SoC in R-Car DU bindings.
>
> Signed-off-by: Fabrizio Castro
> Reviewed-by: Biju Das
Reviewed-by: Laurent Pinchart
and take
Hi Jacopo,
On Friday, 5 October 2018 11:49:45 EEST jacopo mondi wrote:
> On Fri, Oct 05, 2018 at 01:00:47AM +0300, Laurent Pinchart wrote:
> > On Friday, 5 October 2018 00:42:17 EEST Laurent Pinchart wrote:
> >> On Thursday, 4 October 2018 23:41:34 EEST Niklas Söderlund wrote:
0x40}, /* ADI Required Write */
> {ADV748X_PAGE_TXB, 0xda, 0x01}, /* i2c_mipi_pll_en - 1'b1 */
> -
> {ADV748X_PAGE_WAIT, 0x00, 0x02},/* delay 2 */
> {ADV748X_PAGE_TXB, 0x00, 0x21 },/* Power-up CSI-TX */
> {ADV748X_PAGE_WAIT, 0x00, 0x01},/* delay 1 */
--
Regards,
Laurent Pinchart
201 - 300 of 2657 matches
Mail list logo
