Add a special enable method for the second CA7 of the R9A06G032
as well as the default value for the "cpu-release-addr" property.
Signed-off-by: Michel Pollet <michel.pol...@bp.renesas.com>
---
arch/arm/boot/dts/r9a06g032.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git
The Renesas R9A06G032 second CA7 is parked in a ROM pen at boot time, it
requires a special enable method to get it started.
Signed-off-by: Michel Pollet <michel.pol...@bp.renesas.com>
---
arch/arm/mach-shmobile/Makefile| 1 +
arch/arm/mach-shmobile/smp-r9a06g032.
Add a special enable method for second CA7 of the R9A06G032
Signed-off-by: Michel Pollet <michel.pol...@bp.renesas.com>
Reviewed-by: Rob Herring <r...@kernel.org>
---
Documentation/devicetree/bindings/arm/cpus.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentatio
patch v7
v2:
+ Added suggestions from Florian Fainelli
+ Use __pa_symbol()
+ Simplified logic in prepare_cpu()
+ Reordered the patches
+ Rebased on RZN1 Base patch v5
Michel Pollet (3):
dt-bindings: cpu: Add Renesas R9A06G032 SMP enable method.
arm: shmobile: Add the R9A06G032 SMP
This provides a clock driver for the Renesas R09A06G032.
This uses a structure derived from both the RCAR gen2 driver as well as
the renesas-cpg-mssr driver.
Signed-off-by: Michel Pollet <michel.pol...@bp.renesas.com>
---
drivers/clk/renesas/Kconfig| 6 +
drivers/clk/r
This adds a base device tree file for the RZN1-DB board, with only the
basic support allowing the system to boot to a prompt. Only one UART is
used, with only a single CPU running.
Signed-off-by: Michel Pollet <michel.pol...@bp.renesas.com>
---
arch/arm/boot/dts/Makefile
This adds the Renesas R9A06G032 bare bone support.
This currently only handles generic parts (gic, architected timer)
and a UART.
Signed-off-by: Michel Pollet <michel.pol...@bp.renesas.com>
---
arch/arm/boot/dts/r9a06g032.dtsi | 86
1 file chang
The Renesas R9A06G032 SYSCTRL node description.
Signed-off-by: Michel Pollet <michel.pol...@bp.renesas.com>
---
.../bindings/clock/renesas,r9a06g032-sysctrl.txt | 32 ++
1 file changed, 32 insertions(+)
create mode 100644
Documentation/devicetree/bindings/clock/r
This adds the constants necessary to use the renesas,r9a06g032-sysctrl node.
Signed-off-by: Michel Pollet <michel.pol...@bp.renesas.com>
Reviewed-by: Rob Herring <r...@kernel.org>
---
include/dt-bindings/clock/r9a06g032-sysctrl.h | 187 ++
1 file changed, 18
every warnings from the DTC compiler on W=12 mode.
+ Split the device-tree patches from the code.
Michel Pollet (5):
dt-bindings: Add the r9a06g032-sysctrl.h file
dt-bindings: clock: renesas,r9a06g032-sysctrl: documentation
ARM: dts: Renesas R9A06G032 base device tree file
ARM: dts: Re
This adds the Renesas RZ/N1D (Part #R9A06G032) SoC bare
bone support.
This currently only handles generic parts (gic, architected timer)
and a UART.
For simplicity sake, this also relies on the bootloader to set the
pinctrl and clocks.
Signed-off-by: Michel Pollet <michel.pol...@bp.renesas.
This adds a base device tree file for the RZN1-DB board, with only the
basic support allowing the system to boot to a prompt. Only one UART is
used, with only a single CPU running.
Signed-off-by: Michel Pollet <michel.pol...@bp.renesas.com>
---
arch/arm/boot/dts/Makefile
This provides a clock driver for the Renesas RZ/N1 parts (#R09A06G0xx).
This uses a structure derived from both the RCAR gen2 driver as well as
the renesas-cpg-mssr driver.
Signed-off-by: Michel Pollet <michel.pol...@bp.renesas.com>
---
drivers/clk/renesas/Kconfig | 6 +
drive
The Renesas RZ/N1 Family (Part #R9A06G0xx) requires a driver
to provide the SoC clock infrastructure for Linux.
This documents the driver bindings.
Signed-off-by: Michel Pollet <michel.pol...@bp.renesas.com>
---
.../bindings/clock/renesas,rzn1-clocks.txt | 44 +++
This adds the constants necessary to use the renesas,rzn1-clocks driver.
Signed-off-by: Michel Pollet <michel.pol...@bp.renesas.com>
---
include/dt-bindings/clock/rzn1-clocks.h | 187
1 file changed, 187 insertions(+)
create mode 100644 include/dt-bindings
This documents the RZ/N1 bindings for the RZN1D-DB board.
Signed-off-by: Michel Pollet <michel.pol...@bp.renesas.com>
Reviewed-by: Rob Herring <r...@kernel.org>
---
Documentation/devicetree/bindings/arm/shmobile.txt | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
elly.
+ Fixed every warnings from the DTC compiler on W=12 mode.
+ Split the device-tree patches from the code.
Michel Pollet (6):
dt-bindings: arm: Document the RZN1D-DB board
dt-bindings: Add the rzn1-clocks.h file
dt-bindings: clock: renesas,rzn1-clocks: document RZ/N1 clock driver
ARM
Add a special enable method for the second CA7 of the Renesas RZ/N1D
(R9A06G032), as well as the default value for the "cpu-release-addr"
property.
Signed-off-by: Michel Pollet <michel.pol...@bp.renesas.com>
---
arch/arm/boot/dts/r9a06g032.dtsi | 2 ++
1 file changed, 2 insertion
Add a special enable method for second CA8 of the Renesas RZ/N1D
(R9A06G032).
Signed-off-by: Michel Pollet <michel.pol...@bp.renesas.com>
Reviewed-by: Rob Herring <r...@kernel.org>
---
Documentation/devicetree/bindings/arm/cpus.txt | 1 +
1 file changed, 1 insertion(+)
The Renesas RZ/N1D second CA7 is parked in a ROM pen at boot time, it
requires a special enable method to get it started.
Signed-off-by: Michel Pollet <michel.pol...@bp.renesas.com>
---
arch/arm/mach-shmobile/Makefile| 1 +
arch/arm/mach-shmobile/smp-r9a06g032.
()
+ Simplified logic in prepare_cpu()
+ Reordered the patches
+ Rebased on RZN1 Base patch v5
*** BLURB HERE ***
Michel Pollet (3):
dt-bindings: cpu: Add Renesas RZ/N1D SMP enable method.
arm: shmobile: Add the RZ/N1D SMP enabler driver
ARM: dts: Renesas RZ/N1D SMP enable method
part'
distinction.
+ Removed the sysctrl.h file entirelly.
+ Fixed every warnings from the DTC compiler on W=12 mode.
+ Split the device-tree patches from the code.
Michel Pollet (6):
arm: shmobile: Add the RZ/N1D (R9A06G032) to the shmobile Kconfig
dt-bindings: reset: renesas,rzn1-re
This adds the Renesas RZ/N1D (Part #R9A06G032) SoC bare
bone support.
This currently only handles generic parts (gic, architected timer)
and a UART.
For simplicity sake, this also relies on the bootloader to set the
pinctrl and clocks.
Signed-off-by: Michel Pollet <michel.pol...@bp.renesas.
The Renesas RZ/N1 Family (Part #R9A06G0xx) requires a driver
as part of the sysctrl MFD to handle rebooting the CA7 cores.
This documents the driver bindings.
Signed-off-by: Michel Pollet <michel.pol...@bp.renesas.com>
---
.../devicetree/bindings/power/renesas,rzn1-reboot.txt
This adds a base device tree file for the RZN1-DB board, with only the
basic support allowing the system to boot to a prompt. Only one UART is
used, with only a single CPU running.
Signed-off-by: Michel Pollet <michel.pol...@bp.renesas.com>
---
arch/arm/boot/dts/Makefile
Add the RZ/N1D SoC to the reset of the Renesas SoC Collection.
Signed-off-by: Michel Pollet <michel.pol...@bp.renesas.com>
---
arch/arm/mach-shmobile/Kconfig | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 9
The Renesas RZ/N1 Family (Part #R9A06G0xx) needs a small driver
to reboot the Cortex-A7 cores. This driver is a sub driver of
the sysctrl MFD.
Signed-off-by: Michel Pollet <michel.pol...@bp.renesas.com>
---
drivers/power/reset/Kconfig | 7 +++
drivers/power/reset/Makefile
This documents the RZ/N1 bindings for the RZN1D-DB board.
Signed-off-by: Michel Pollet <michel.pol...@bp.renesas.com>
---
Documentation/devicetree/bindings/arm/shmobile.txt | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/arm/shmobi
Hi Florian,
On 16 April 2018 22:46, Florian Fainelli:
> Hi Michel,
>
> On 04/16/2018 02:34 AM, Michel Pollet wrote:
> > The Renesas RZ/N1D second CA7 is parked in a ROM pen at boot time, it
> > requires a special enable method to get it started at boot time.
> >
>
Hi Rob,
On 13 April 2018 19:06, Rob Herring:
> On Tue, Apr 10, 2018 at 09:30:03AM +0100, Michel Pollet wrote:
> > The Renesas RZ/N1 Family (Part #R9A06G0xx) has a multi-function system
> > controller. This documents the node used to encapsulate it's sub
> > drivers.
> >
Please ignore this one... it's rebase junk
Michel
>
> This enables starting the second CA7 core. Also handles the case the
> bootloader has had to change the second CPU parking address to allow
> booting in NONSEC/HYP.
>
> Signed-off-by: Michel Pollet <michel.
This enables starting the second CA7 core. Also handles the case the
bootloader has had to change the second CPU parking address to allow
booting in NONSEC/HYP.
Signed-off-by: Michel Pollet <michel.pol...@bp.renesas.com>
---
arch/arm/mach-shmobile/Makefile | 1 +
arch/arm/mach-sh
Add a special enable method for second CA8 of the Renesas RZ/N1D
(R9A06G032).
Signed-off-by: Michel Pollet <michel.pol...@bp.renesas.com>
---
Documentation/devicetree/bindings/arm/cpus.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/arm/cpus.
Add a special enable method for the second CA7 of the Renesas RZ/N1D
(R9A06G032), as well as the default value for the "cpu-release-addr"
property.
Signed-off-by: Michel Pollet <michel.pol...@bp.renesas.com>
---
arch/arm/boot/dts/r9a06g032.dtsi | 2 ++
1 file changed, 2 insertion
The Renesas RZ/N1D second CA7 is parked in a ROM pen at boot time, it
requires a special enable method to get it started at boot time.
Signed-off-by: Michel Pollet <michel.pol...@bp.renesas.com>
---
arch/arm/mach-shmobile/Makefile| 1 +
arch/arm/mach-shmobile/smp-r9a06g032.
, or is it sufficiently
clear?
Michel Pollet (3):
dt-bindings: cpu: Add Renesas RZ/N1D SMP enable method.
ARM: dts: Renesas RZ/N1D SMP enable method
arm: shmobile: Add the RZ/N1D SMP enabler driver.
Documentation/devicetree/bindings/arm/cpus.txt | 1 +
arch/arm/boot/dts/r9a06g032.dtsi
Hi Geert,
On 10 April 2018 11:08, Geert wrote:
>
> Hi Michel,
>
> On Tue, Apr 10, 2018 at 11:56 AM, Michel Pollet
> <michel.pol...@bp.renesas.com> wrote:
> > In the current SDK for the RZ/N1, we made a clock architecture that is
> entirely device-tree based.
&g
Hi guys,
In the current SDK for the RZ/N1, we made a clock architecture that is entirely
device-tree based.
The clock hierarchy is quite complex and was machine generated from design
documents, and
some exceptions and grouping were added to the 'main' family rzn1.dtsi...
Apart from a few
The Renesas RZ/N1 Family (Part #R9A06G0xx) needs a small driver
to reboot the Cortex-A7 cores. This driver is a sub driver of
the sysctrl MFD.
Signed-off-by: Michel Pollet <michel.pol...@bp.renesas.com>
---
drivers/power/reset/Kconfig | 7 +++
drivers/power/reset/Makefile
Add the RZ/N1D SoC to the reset of the Renesas SoC Collection.
Signed-off-by: Michel Pollet <michel.pol...@bp.renesas.com>
---
arch/arm/mach-shmobile/Kconfig | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 2
The Renesas RZ/N1 Family (Part #R9A06G0xx) has a multi-function
system controller. This documents the node used to encapsulate
it's sub drivers.
Signed-off-by: Michel Pollet <michel.pol...@bp.renesas.com>
---
.../bindings/mfd/renesas,rzn1-sysctrl.txt | 23 ++
The Renesas RZ/N1 Family (Part #R9A06G0xx) requires a driver
as part of the sysctrl MFD to handle rebooting the CA7 cores.
This documents the driver bindings.
Signed-off-by: Michel Pollet <michel.pol...@bp.renesas.com>
---
.../bindings/power/renesas,rzn1-reboot.txt
This adds a base device tree file for the RZN1-DB board, with only the
basic support allowing the system to boot to a prompt. Only one UART is
used, with only a single CPU running.
Signed-off-by: Michel Pollet <michel.pol...@bp.renesas.com>
---
arch/arm/boot/dts/Makefile
This adds the Renesas RZ/N1D (Part #R9A06G032) SoC bare
bone support.
This currently only handles generic parts (gic, architected timer)
and a UART.
For simplicity sake, this also relies on the bootloader to set the
pinctrl and clocks.
Signed-off-by: Michel Pollet <michel.pol...@bp.renesas.
This documents the RZ/N1 bindings for the RZN1D-DB board.
Signed-off-by: Michel Pollet <michel.pol...@bp.renesas.com>
---
Documentation/devicetree/bindings/arm/shmobile.txt | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/arm/shmobi
Add the RZ/N1 Family (Part #R9A06G0xx) ARCH config to the rest of
the Renesas SoC collection.
Signed-off-by: Michel Pollet <michel.pol...@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+rene...@glider.be>
---
arch/arm/mach-shmobile/Kconfig | 5 +
1 file changed, 5 inserti
bile conventions
+ Adapted the compatible= strings to reflect 'family' vs 'part'
distinction.
+ Removed the sysctrl.h file entirelly.
+ Fixed every warnings from the DTC compiler on W=12 mode.
+ Split the device-tree patches from the code.
Michel Pollet (8):
arm: shmobile: Add the RZ/N1
Hi Rob,
On 09 April 2018 21:10, Rob Herring wrote:
> On Thu, Mar 29, 2018 at 08:46:58AM +0100, Michel Pollet wrote:
> > The Renesas RZ/N1 Family (Part #R9A06G0xx) requires a driver as part
> > of the sysctrl MFD to handle rebooting the CA7 cores.
> > This document
On 29 March 2018 08:47, I messed up:
[snip]
>
> The Renesas RZ/N1 Family (Part #R9A06G0xx) needs a small driver to reboot
> the Cortex-A7 cores. This driver is a sub driver of the sysctrl MFD.
>
> Signed-off-by: Michel Pollet <michel.pol...@bp.renesas.com>
> ---
>
Add the RZ/N1 Family (Part #R9A06G0xx) ARCH config to the rest of
the Renesas SoC collection.
Signed-off-by: Michel Pollet <michel.pol...@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+rene...@glider.be>
---
arch/arm/mach-shmobile/Kconfig | 5 +
1 file changed, 5 inserti
This adds the Renesas RZ/N1 Family (Part #R9A06G0xx) SoC
bare bone support.
This currently only handles generic parts (gic, architected timer)
and a UART.
For simplicity sake, this also relies on the bootloader to set the
pinctrl and clocks.
Signed-off-by: Michel Pollet <michel.
This adds a base device tree file for the RZN1-DB board, with only the
basic support allowing the system to boot to a prompt. Only one UART is
used, with only a single CPU running.
Signed-off-by: Michel Pollet <michel.pol...@bp.renesas.com>
---
arch/arm/boot/dts/r9a06g032-rzn1d400-db.dt
This adds the newly added board to the Renesas built target
Signed-off-by: Michel Pollet <michel.pol...@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+rene...@glider.be>
---
arch/arm/boot/dts/Makefile | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/Mak
the compatible= strings to reflect 'family' vs 'part'
distinction.
+ Removed the sysctrl.h file entirelly.
+ Fixed every warnings from the DTC compiler on W=12 mode.
+ Split the device-tree patches from the code.
Michel Pollet (8):
DT: mfd: renesas,rzn1-sysctrl: document RZ/N1 sysctrl node
The Renesas RZ/N1 Family (Part #R9A06G0xx) has a multi-function
system controller. This documents the node used to encapsulate
it's sub drivers.
Signed-off-by: Michel Pollet <michel.pol...@bp.renesas.com>
---
.../devicetree/bindings/mfd/renesas,rzn1-sysctrl.txt | 19 +++
The Renesas RZ/N1 Family (Part #R9A06G0xx) needs a small driver
to reboot the Cortex-A7 cores. This driver is a sub driver of
the sysctrl MFD.
Signed-off-by: Michel Pollet <michel.pol...@bp.renesas.com>
---
drivers/power/reset/Kconfig | 7 +++
drivers/power/reset/Makefile
This documents the RZ/N1 bindings for both the RZ/N1 and the RZN1D-DB
board.
Signed-off-by: Michel Pollet <michel.pol...@bp.renesas.com>
---
Documentation/devicetree/bindings/arm/shmobile.txt | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/Documentation/devi
The Renesas RZ/N1 Family (Part #R9A06G0xx) requires a driver
as part of the sysctrl MFD to handle rebooting the CA7 cores.
This documents the driver bindings.
Signed-off-by: Michel Pollet <michel.pol...@bp.renesas.com>
---
.../bindings/power/renesas,rzn1-reboot.txt
' vs 'part'
>distinction.
> + Removed the sysctrl.h file entirelly.
> + Fixed every warnings from the DTC compiler on W=12 mode.
> + Split the device-tree patches from the code.
>
> Michel Pollet (8):
> DT: mfd: renesas,rzn1-sysctrl: document RZ/N1 sysctrl node
> DT: reset:
Hi Geert,
Thanks for your review!
On 22 March 2018 12:37, Geert said:
> Hi Michel,
>
> On Thu, Mar 22, 2018 at 12:44 PM, Michel Pollet
> <michel.pol...@bp.renesas.com> wrote:
> > This documents the RZ/N1 bindings for both the RZ/N1 and the
> > RZN1D400-DB board.
conventions
+ Adapted the compatible= strings to reflect 'family' vs 'part'
distinction.
+ Removed the sysctrl.h file entirelly.
+ Fixed every warnings from the DTC compiler on W=12 mode.
+ Split the device-tree patches from the code.
Michel Pollet (8):
DT: mfd: renesas,rzn1-sysctrl
The Renesas RZ/N1 Family (Part #R9A06G0xx) has a multi-function
system controller. This documents the node used to encapsulate
it's sub drivers.
Signed-off-by: Michel Pollet <michel.pol...@bp.renesas.com>
---
.../bindings/mfd/renesas,rzn1-sysctrl.txt | 22 ++
This documents the RZ/N1 bindings for both the RZ/N1 and the RZN1D400-DB
board.
Signed-off-by: Michel Pollet <michel.pol...@bp.renesas.com>
---
Documentation/devicetree/bindings/arm/shmobile.txt | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/Documentation/devi
The Renesas RZ/N1 Family (Part #R9A06G0xx) requires a driver
as part of the sysctrl MFD to handle rebooting the CA7 cores.
This documents the driver bindings.
Signed-off-by: Michel Pollet <michel.pol...@bp.renesas.com>
---
.../bindings/power/renesas,rzn1-reboot.txt
Add the RZ/N1 Family (Part #R9A06G0xx) ARCH config to the rest of
the Renesas SoC collection.
Signed-off-by: Michel Pollet <michel.pol...@bp.renesas.com>
---
arch/arm/mach-shmobile/Kconfig | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/ar
The Renesas RZ/N1 Family (Part #R9A06G0xx) needs a small driver
to reboot the Cortex-A7 cores. This driver is a sub driver of
the sysctrl MFD.
Signed-off-by: Michel Pollet <michel.pol...@bp.renesas.com>
---
drivers/power/reset/Kconfig | 7 +++
drivers/power/reset/Makefile
This adds the Renesas RZ/N1 Family (Part #R9A06G0xx) SoC
bare bone support.
This currently only handles generic parts (gic, architected timer)
and a UART.
For simplicity sake, this also relies on the bootloader to set the
pinctrl and clocks.
Signed-off-by: Michel Pollet <michel.
This adds the newly added board to the Renesas built target
Signed-off-by: Michel Pollet <michel.pol...@bp.renesas.com>
---
arch/arm/boot/dts/Makefile | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 3b4cc1b..0f01ada
This adds a base device tree file for the RZN1-DB board, with only the
basic support allowing the system to boot to a prompt. Only one UART is
used, with only a single CPU running.
Signed-off-by: Michel Pollet <michel.pol...@bp.renesas.com>
---
arch/arm/boot/dts/r9a06g032-rzn1d400-db.dt
This adds the Renesas RZ/N1 CPU and bare bone support.
This currently only handles generic parts (gic, architected timer)
and a UART.
This also relies on the bootloader to set the pinctrl and clocks.
Signed-off-by: Michel Pollet <michel.pol...@bp.renesas.com>
---
Documentation/devi
Only enables the uart0 for now, and also relies on the bootloader
for setting up the clocks and pinctrl.
Signed-off-by: Michel Pollet <michel.pol...@bp.renesas.com>
---
Documentation/devicetree/bindings/arm/shmobile.txt | 2 ++
arch/arm/boot/dts/rzn1d400-db.dts
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