Re: [PATCH] clk: renesas: r8a7795: Correct lvds clock parent

Hi Geert, Thank you for the patch. On Friday 10 Jun 2016 09:44:33 Geert Uytterhoeven wrote: > According to the latest information, the parent clock of the LVDS module > clock is the S0D4 clock, not the S2D1 clock. > > Note that this change has no influence on actual operation, as the > rcar-du L

[PATCH] clk: renesas: r8a7795: Correct lvds clock parent

According to the latest information, the parent clock of the LVDS module clock is the S0D4 clock, not the S2D1 clock. Note that this change has no influence on actual operation, as the rcar-du LVDS encoder driver doesn't use the parent clock's rate. Signed-off-by: Geert Uytterhoeven --- Will que