Re: [PATCH 2/3] arm64: renesas: r8a7796: Add all SCIF nodes

[Simon Horman]

On Thu, Sep 15, 2016 at 08:33:38PM +0200, Geert Uytterhoeven wrote:
> On Wed, Sep 14, 2016 at 6:46 PM, Ulrich Hecht
>  wrote:
> > Add the device nodes for all R-Car H3 SCIF serial ports, incl. clocks
> > and clock domain.
> >
> > Signed-off-by: Ulrich Hecht 
> 
> Reviewed-by: Geert Uytterhoeven 

Unfortunately this does not apply to my tree.

Ulrich, please consider rebasing the latest renesas/next branch
(currently renesas-next-20160908-v4.8-rc1 tag) and reposting.

I'd be happy to see this patch reposted without the rest of the series
if that would be most expedient for you.

Re: [PATCH 2/3] arm64: renesas: r8a7796: Add all SCIF nodes

[Geert Uytterhoeven]

On Wed, Sep 14, 2016 at 6:46 PM, Ulrich Hecht
 wrote:
> Add the device nodes for all R-Car H3 SCIF serial ports, incl. clocks
> and clock domain.
>
> Signed-off-by: Ulrich Hecht 

Reviewed-by: Geert Uytterhoeven 

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

[PATCH 2/3] arm64: renesas: r8a7796: Add all SCIF nodes

[Ulrich Hecht]

Add the device nodes for all R-Car H3 SCIF serial ports, incl. clocks
and clock domain.

Signed-off-by: Ulrich Hecht 
---
 arch/arm64/boot/dts/renesas/r8a7796.dtsi | 65 
 1 file changed, 65 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi 
b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
index 7c4d11c..e59ded4 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
@@ -347,6 +347,32 @@
status = "disabled";
};
 
+   scif0: serial@e6e6 {
+   compatible = "renesas,scif-r8a7796",
+"renesas,rcar-gen3-scif", "renesas,scif";
+   reg = <0 0xe6e6 0 64>;
+   interrupts = ;
+   clocks = < CPG_MOD 207>,
+< CPG_CORE R8A7796_CLK_S3D1>,
+<_clk>;
+   clock-names = "fck", "brg_int", "scif_clk";
+   power-domains = < R8A7796_PD_ALWAYS_ON>;
+   status = "disabled";
+   };
+
+   scif1: serial@e6e68000 {
+   compatible = "renesas,scif-r8a7796",
+"renesas,rcar-gen3-scif", "renesas,scif";
+   reg = <0 0xe6e68000 0 64>;
+   interrupts = ;
+   clocks = < CPG_MOD 206>,
+< CPG_CORE R8A7796_CLK_S3D1>,
+<_clk>;
+   clock-names = "fck", "brg_int", "scif_clk";
+   power-domains = < R8A7796_PD_ALWAYS_ON>;
+   status = "disabled";
+   };
+
scif2: serial@e6e88000 {
compatible = "renesas,scif-r8a7796",
 "renesas,rcar-gen3-scif", "renesas,scif";
@@ -360,6 +386,45 @@
status = "disabled";
};
 
+   scif3: serial@e6c5 {
+   compatible = "renesas,scif-r8a7796",
+"renesas,rcar-gen3-scif", "renesas,scif";
+   reg = <0 0xe6c5 0 64>;
+   interrupts = ;
+   clocks = < CPG_MOD 204>,
+< CPG_CORE R8A7796_CLK_S3D1>,
+<_clk>;
+   clock-names = "fck", "brg_int", "scif_clk";
+   power-domains = < R8A7796_PD_ALWAYS_ON>;
+   status = "disabled";
+   };
+
+   scif4: serial@e6c4 {
+   compatible = "renesas,scif-r8a7796",
+"renesas,rcar-gen3-scif", "renesas,scif";
+   reg = <0 0xe6c4 0 64>;
+   interrupts = ;
+   clocks = < CPG_MOD 203>,
+< CPG_CORE R8A7796_CLK_S3D1>,
+<_clk>;
+   clock-names = "fck", "brg_int", "scif_clk";
+   power-domains = < R8A7796_PD_ALWAYS_ON>;
+   status = "disabled";
+   };
+
+   scif5: serial@e6f3 {
+   compatible = "renesas,scif-r8a7796",
+"renesas,rcar-gen3-scif", "renesas,scif";
+   reg = <0 0xe6f3 0 64>;
+   interrupts = ;
+   clocks = < CPG_MOD 202>,
+< CPG_CORE R8A7796_CLK_S3D1>,
+<_clk>;
+   clock-names = "fck", "brg_int", "scif_clk";
+   power-domains = < R8A7796_PD_ALWAYS_ON>;
+   status = "disabled";
+   };
+
dmac0: dma-controller@e670 {
compatible = "renesas,dmac-r8a7796",
 "renesas,rcar-dmac";
-- 
2.9.3