Hi Niklas,
On Fri, Jan 20, 2017 at 11:03 PM, Niklas Söderlund
wrote:
> Nice patch! It took me a while to understand why you didn't need to read
> the register before writing to it in cpg_mssr_deassert() :-)
Yeah, deassertion and assertion are asymmetrical.
Note
On 01/20, Geert Uytterhoeven wrote:
> Add optional support for the Reset Control feature of the Renesas Clock
> Pulse Generator / Module Standby and Software Reset module on R-Car
> Gen2, R-Car Gen3, and RZ/G1 SoCs.
>
> This allows to reset SoC devices using the Reset Controller API.
>
>
Hi Philipp,
On Fri, Jan 20, 2017 at 4:57 PM, Philipp Zabel wrote:
> On Fri, 2017-01-20 at 15:08 +0100, Geert Uytterhoeven wrote:
>> Add optional support for the Reset Control feature of the Renesas Clock
>> Pulse Generator / Module Standby and Software Reset module on
Hi Geert,
On Fri, 2017-01-20 at 15:08 +0100, Geert Uytterhoeven wrote:
> Add optional support for the Reset Control feature of the Renesas Clock
> Pulse Generator / Module Standby and Software Reset module on R-Car
> Gen2, R-Car Gen3, and RZ/G1 SoCs.
Is there a reason to make this optional?
>
Add optional support for the Reset Control feature of the Renesas Clock
Pulse Generator / Module Standby and Software Reset module on R-Car
Gen2, R-Car Gen3, and RZ/G1 SoCs.
This allows to reset SoC devices using the Reset Controller API.
Signed-off-by: Geert Uytterhoeven