subject:"\[PATCH v10 28\/30\] rcar\-vin\: enable support for r8a7795"

Re: [PATCH v10 28/30] rcar-vin: enable support for r8a7795

2018-02-13 Thread Laurent Pinchart

Hi Niklas,

Thank you for the patch.

On Monday, 29 January 2018 18:34:33 EET Niklas Söderlund wrote:
> Add the SoC specific information for Renesas r8a7795 ES1.x and ES2.0.
> 
> Signed-off-by: Niklas Söderlund 

Reviewed-by: Laurent Pinchart 

> ---
>  drivers/media/platform/rcar-vin/Kconfig |   2 +-
>  drivers/media/platform/rcar-vin/rcar-core.c | 120 +
>  2 files changed, 121 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/media/platform/rcar-vin/Kconfig
> b/drivers/media/platform/rcar-vin/Kconfig index
> af4c98b44d2e22cb..8fa7ee468c63afb9 100644
> --- a/drivers/media/platform/rcar-vin/Kconfig
> +++ b/drivers/media/platform/rcar-vin/Kconfig
> @@ -6,7 +6,7 @@ config VIDEO_RCAR_VIN
>   select V4L2_FWNODE
>   ---help---
> Support for Renesas R-Car Video Input (VIN) driver.
> -   Supports R-Car Gen2 SoCs.
> +   Supports R-Car Gen2 and Gen3 SoCs.
> 
> To compile this driver as a module, choose M here: the
> module will be called rcar-vin.
> diff --git a/drivers/media/platform/rcar-vin/rcar-core.c
> b/drivers/media/platform/rcar-vin/rcar-core.c index
> 7ceff0de40078580..43d2fa83875817f0 100644
> --- a/drivers/media/platform/rcar-vin/rcar-core.c
> +++ b/drivers/media/platform/rcar-vin/rcar-core.c
> @@ -21,6 +21,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
> 
>  #include 
>  #include 
> @@ -815,6 +816,104 @@ static const struct rvin_info rcar_info_gen2 = {
>   .max_height = 2048,
>  };
> 
> +static const struct rvin_group_route rcar_info_r8a7795_routes[] = {
> + { .vin = 0, .csi = RVIN_CSI40, .chan = 0, .mask = BIT(0) | BIT(3) },
> + { .vin = 0, .csi = RVIN_CSI20, .chan = 0, .mask = BIT(1) | BIT(4) },
> + { .vin = 0, .csi = RVIN_CSI40, .chan = 1, .mask = BIT(2) },
> + { .vin = 1, .csi = RVIN_CSI20, .chan = 0, .mask = BIT(0) },
> + { .vin = 1, .csi = RVIN_CSI40, .chan = 1, .mask = BIT(1) | BIT(3) },
> + { .vin = 1, .csi = RVIN_CSI40, .chan = 0, .mask = BIT(2) },
> + { .vin = 1, .csi = RVIN_CSI20, .chan = 1, .mask = BIT(4) },
> + { .vin = 2, .csi = RVIN_CSI20, .chan = 1, .mask = BIT(0) },
> + { .vin = 2, .csi = RVIN_CSI40, .chan = 0, .mask = BIT(1) },
> + { .vin = 2, .csi = RVIN_CSI20, .chan = 0, .mask = BIT(2) },
> + { .vin = 2, .csi = RVIN_CSI40, .chan = 2, .mask = BIT(3) },
> + { .vin = 2, .csi = RVIN_CSI20, .chan = 2, .mask = BIT(4) },
> + { .vin = 3, .csi = RVIN_CSI40, .chan = 1, .mask = BIT(0) },
> + { .vin = 3, .csi = RVIN_CSI20, .chan = 1, .mask = BIT(1) | BIT(2) },
> + { .vin = 3, .csi = RVIN_CSI40, .chan = 3, .mask = BIT(3) },
> + { .vin = 3, .csi = RVIN_CSI20, .chan = 3, .mask = BIT(4) },
> + { .vin = 4, .csi = RVIN_CSI41, .chan = 0, .mask = BIT(0) | BIT(3) },
> + { .vin = 4, .csi = RVIN_CSI20, .chan = 0, .mask = BIT(1) | BIT(4) },
> + { .vin = 4, .csi = RVIN_CSI41, .chan = 1, .mask = BIT(2) },
> + { .vin = 5, .csi = RVIN_CSI20, .chan = 0, .mask = BIT(0) },
> + { .vin = 5, .csi = RVIN_CSI41, .chan = 1, .mask = BIT(1) | BIT(3) },
> + { .vin = 5, .csi = RVIN_CSI41, .chan = 0, .mask = BIT(2) },
> + { .vin = 5, .csi = RVIN_CSI20, .chan = 1, .mask = BIT(4) },
> + { .vin = 6, .csi = RVIN_CSI20, .chan = 1, .mask = BIT(0) },
> + { .vin = 6, .csi = RVIN_CSI41, .chan = 0, .mask = BIT(1) },
> + { .vin = 6, .csi = RVIN_CSI20, .chan = 0, .mask = BIT(2) },
> + { .vin = 6, .csi = RVIN_CSI41, .chan = 2, .mask = BIT(3) },
> + { .vin = 6, .csi = RVIN_CSI20, .chan = 2, .mask = BIT(4) },
> + { .vin = 7, .csi = RVIN_CSI41, .chan = 1, .mask = BIT(0) },
> + { .vin = 7, .csi = RVIN_CSI20, .chan = 1, .mask = BIT(1) | BIT(2) },
> + { .vin = 7, .csi = RVIN_CSI41, .chan = 3, .mask = BIT(3) },
> + { .vin = 7, .csi = RVIN_CSI20, .chan = 3, .mask = BIT(4) },
> + { /* Sentinel */ }
> +};
> +
> +static const struct rvin_info rcar_info_r8a7795 = {
> + .model = RCAR_GEN3,
> + .use_mc = true,
> + .max_width = 4096,
> + .max_height = 4096,
> + .routes = rcar_info_r8a7795_routes,
> +};
> +
> +static const struct rvin_group_route rcar_info_r8a7795es1_routes[] = {
> + { .vin = 0, .csi = RVIN_CSI40, .chan = 0, .mask = BIT(0) | BIT(3) },
> + { .vin = 0, .csi = RVIN_CSI20, .chan = 0, .mask = BIT(1) | BIT(4) },
> + { .vin = 0, .csi = RVIN_CSI21, .chan = 0, .mask = BIT(2) | BIT(5) },
> + { .vin = 1, .csi = RVIN_CSI20, .chan = 0, .mask = BIT(0) },
> + { .vin = 1, .csi = RVIN_CSI21, .chan = 0, .mask = BIT(1) },
> + { .vin = 1, .csi = RVIN_CSI40, .chan = 0, .mask = BIT(2) },
> + { .vin = 1, .csi = RVIN_CSI40, .chan = 1, .mask = BIT(3) },
> + { .vin = 1, .csi = RVIN_CSI20, .chan = 1, .mask = BIT(4) },
> + { .vin = 1, .csi = RVIN_CSI21, .chan = 1, .mask = BIT(5) },
> + { .vin = 2, .csi = RVIN_CSI21, .chan = 0, .mask = BIT(0) },
> + { .vin = 2, .csi = RVIN_CSI40, .chan = 0, .mask = BIT(1) },
> +

[PATCH v10 28/30] rcar-vin: enable support for r8a7795

2018-01-29 Thread Niklas Söderlund

Add the SoC specific information for Renesas r8a7795 ES1.x and ES2.0.

Signed-off-by: Niklas Söderlund 
---
 drivers/media/platform/rcar-vin/Kconfig |   2 +-
 drivers/media/platform/rcar-vin/rcar-core.c | 120 
 2 files changed, 121 insertions(+), 1 deletion(-)

diff --git a/drivers/media/platform/rcar-vin/Kconfig 
b/drivers/media/platform/rcar-vin/Kconfig
index af4c98b44d2e22cb..8fa7ee468c63afb9 100644
--- a/drivers/media/platform/rcar-vin/Kconfig
+++ b/drivers/media/platform/rcar-vin/Kconfig
@@ -6,7 +6,7 @@ config VIDEO_RCAR_VIN
select V4L2_FWNODE
---help---
  Support for Renesas R-Car Video Input (VIN) driver.
- Supports R-Car Gen2 SoCs.
+ Supports R-Car Gen2 and Gen3 SoCs.
 
  To compile this driver as a module, choose M here: the
  module will be called rcar-vin.
diff --git a/drivers/media/platform/rcar-vin/rcar-core.c 
b/drivers/media/platform/rcar-vin/rcar-core.c
index 7ceff0de40078580..43d2fa83875817f0 100644
--- a/drivers/media/platform/rcar-vin/rcar-core.c
+++ b/drivers/media/platform/rcar-vin/rcar-core.c
@@ -21,6 +21,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include 
 #include 
@@ -815,6 +816,104 @@ static const struct rvin_info rcar_info_gen2 = {
.max_height = 2048,
 };
 
+static const struct rvin_group_route rcar_info_r8a7795_routes[] = {
+   { .vin = 0, .csi = RVIN_CSI40, .chan = 0, .mask = BIT(0) | BIT(3) },
+   { .vin = 0, .csi = RVIN_CSI20, .chan = 0, .mask = BIT(1) | BIT(4) },
+   { .vin = 0, .csi = RVIN_CSI40, .chan = 1, .mask = BIT(2) },
+   { .vin = 1, .csi = RVIN_CSI20, .chan = 0, .mask = BIT(0) },
+   { .vin = 1, .csi = RVIN_CSI40, .chan = 1, .mask = BIT(1) | BIT(3) },
+   { .vin = 1, .csi = RVIN_CSI40, .chan = 0, .mask = BIT(2) },
+   { .vin = 1, .csi = RVIN_CSI20, .chan = 1, .mask = BIT(4) },
+   { .vin = 2, .csi = RVIN_CSI20, .chan = 1, .mask = BIT(0) },
+   { .vin = 2, .csi = RVIN_CSI40, .chan = 0, .mask = BIT(1) },
+   { .vin = 2, .csi = RVIN_CSI20, .chan = 0, .mask = BIT(2) },
+   { .vin = 2, .csi = RVIN_CSI40, .chan = 2, .mask = BIT(3) },
+   { .vin = 2, .csi = RVIN_CSI20, .chan = 2, .mask = BIT(4) },
+   { .vin = 3, .csi = RVIN_CSI40, .chan = 1, .mask = BIT(0) },
+   { .vin = 3, .csi = RVIN_CSI20, .chan = 1, .mask = BIT(1) | BIT(2) },
+   { .vin = 3, .csi = RVIN_CSI40, .chan = 3, .mask = BIT(3) },
+   { .vin = 3, .csi = RVIN_CSI20, .chan = 3, .mask = BIT(4) },
+   { .vin = 4, .csi = RVIN_CSI41, .chan = 0, .mask = BIT(0) | BIT(3) },
+   { .vin = 4, .csi = RVIN_CSI20, .chan = 0, .mask = BIT(1) | BIT(4) },
+   { .vin = 4, .csi = RVIN_CSI41, .chan = 1, .mask = BIT(2) },
+   { .vin = 5, .csi = RVIN_CSI20, .chan = 0, .mask = BIT(0) },
+   { .vin = 5, .csi = RVIN_CSI41, .chan = 1, .mask = BIT(1) | BIT(3) },
+   { .vin = 5, .csi = RVIN_CSI41, .chan = 0, .mask = BIT(2) },
+   { .vin = 5, .csi = RVIN_CSI20, .chan = 1, .mask = BIT(4) },
+   { .vin = 6, .csi = RVIN_CSI20, .chan = 1, .mask = BIT(0) },
+   { .vin = 6, .csi = RVIN_CSI41, .chan = 0, .mask = BIT(1) },
+   { .vin = 6, .csi = RVIN_CSI20, .chan = 0, .mask = BIT(2) },
+   { .vin = 6, .csi = RVIN_CSI41, .chan = 2, .mask = BIT(3) },
+   { .vin = 6, .csi = RVIN_CSI20, .chan = 2, .mask = BIT(4) },
+   { .vin = 7, .csi = RVIN_CSI41, .chan = 1, .mask = BIT(0) },
+   { .vin = 7, .csi = RVIN_CSI20, .chan = 1, .mask = BIT(1) | BIT(2) },
+   { .vin = 7, .csi = RVIN_CSI41, .chan = 3, .mask = BIT(3) },
+   { .vin = 7, .csi = RVIN_CSI20, .chan = 3, .mask = BIT(4) },
+   { /* Sentinel */ }
+};
+
+static const struct rvin_info rcar_info_r8a7795 = {
+   .model = RCAR_GEN3,
+   .use_mc = true,
+   .max_width = 4096,
+   .max_height = 4096,
+   .routes = rcar_info_r8a7795_routes,
+};
+
+static const struct rvin_group_route rcar_info_r8a7795es1_routes[] = {
+   { .vin = 0, .csi = RVIN_CSI40, .chan = 0, .mask = BIT(0) | BIT(3) },
+   { .vin = 0, .csi = RVIN_CSI20, .chan = 0, .mask = BIT(1) | BIT(4) },
+   { .vin = 0, .csi = RVIN_CSI21, .chan = 0, .mask = BIT(2) | BIT(5) },
+   { .vin = 1, .csi = RVIN_CSI20, .chan = 0, .mask = BIT(0) },
+   { .vin = 1, .csi = RVIN_CSI21, .chan = 0, .mask = BIT(1) },
+   { .vin = 1, .csi = RVIN_CSI40, .chan = 0, .mask = BIT(2) },
+   { .vin = 1, .csi = RVIN_CSI40, .chan = 1, .mask = BIT(3) },
+   { .vin = 1, .csi = RVIN_CSI20, .chan = 1, .mask = BIT(4) },
+   { .vin = 1, .csi = RVIN_CSI21, .chan = 1, .mask = BIT(5) },
+   { .vin = 2, .csi = RVIN_CSI21, .chan = 0, .mask = BIT(0) },
+   { .vin = 2, .csi = RVIN_CSI40, .chan = 0, .mask = BIT(1) },
+   { .vin = 2, .csi = RVIN_CSI20, .chan = 0, .mask = BIT(2) },
+   { .vin = 2, .csi = RVIN_CSI40, .chan = 2, .mask = BIT(3) },
+   { .vin = 2, .csi = RVIN_CSI20, .chan = 2, .mask = BIT(4) },
+   { .vin = 2, .csi = RVIN_CSI21,

Re: [PATCH v10 28/30] rcar-vin: enable support for r8a7795

[PATCH v10 28/30] rcar-vin: enable support for r8a7795

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