RE: [PATCH v2] pinctrl: sh-pfc: Add r8a77470 PFC support

2018-05-04 Thread Biju Das 
Hi Geert,

Thanks for the feedback.

> Subject: Re: [PATCH v2] pinctrl: sh-pfc: Add r8a77470 PFC support
>
> Hi Biju,
>
> On Tue, Apr 24, 2018 at 1:03 PM, Biju Das <biju@bp.renesas.com> wrote:
> > Add PFC support for the R8A77470 SoC including pin groups for some
> > on-chip devices such as SCIF, AVB and MMC.
> >
> > Signed-off-by: Biju Das <biju@bp.renesas.com>
> > Reviewed-by: Fabrizio Castro <fabrizio.cas...@bp.renesas.com>
>
> Thanks for your patch!
>
> > ---
> > V1-->V2
> > * Incoroporated the following review comments
> > * Fixed MOD_SEL to MOD_SEL0
> > * Created seperate pin group for AVB_COL and AVB_CRS
> > * Added the pin group AVB_CAPTURE and AVB_MATCH
> > * Added missing SCIF pin groups
>
> I believe this is v3, not v2?

Yes it is v3,  I have realised this after sending the patch.

> Reviewed-by: Geert Uytterhoeven <geert+rene...@glider.be>
>
> Given the (unfinished) discussion about the AVB pins, I'll apply and queue
> your patch in sh-pfc-for-v4.18 with the AVB pin groups removed.

It is ok for me.

Regards,
Biju



Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, 
Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered 
No. 04586709.

Re: [PATCH v2] pinctrl: sh-pfc: Add r8a77470 PFC support

2018-05-04 Thread Geert Uytterhoeven 
Hi Biju,

On Tue, Apr 24, 2018 at 1:03 PM, Biju Das  wrote:
> Add PFC support for the R8A77470 SoC including pin groups for
> some on-chip devices such as SCIF, AVB and MMC.
>
> Signed-off-by: Biju Das 
> Reviewed-by: Fabrizio Castro 

Thanks for your patch!

> ---
> V1-->V2
> * Incoroporated the following review comments
> * Fixed MOD_SEL to MOD_SEL0
> * Created seperate pin group for AVB_COL and AVB_CRS
> * Added the pin group AVB_CAPTURE and AVB_MATCH
> * Added missing SCIF pin groups

I believe this is v3, not v2?

Reviewed-by: Geert Uytterhoeven 

Given the (unfinished) discussion about the AVB pins, I'll apply and queue
your patch in sh-pfc-for-v4.18 with the AVB pin groups removed.

Gr{oetje,eeting}s,

Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

[PATCH v2] pinctrl: sh-pfc: Add r8a77470 PFC support

2018-04-24 Thread Biju Das 
Add PFC support for the R8A77470 SoC including pin groups for
some on-chip devices such as SCIF, AVB and MMC.

Signed-off-by: Biju Das 
Reviewed-by: Fabrizio Castro 
---
V1-->V2
* Incoroporated the following review comments
* Fixed MOD_SEL to MOD_SEL0
* Created seperate pin group for AVB_COL and AVB_CRS
* Added the pin group AVB_CAPTURE and AVB_MATCH
* Added missing SCIF pin groups

 drivers/pinctrl/sh-pfc/Kconfig|5 +
 drivers/pinctrl/sh-pfc/Makefile   |1 +
 drivers/pinctrl/sh-pfc/core.c |6 +
 drivers/pinctrl/sh-pfc/pfc-r8a77470.c | 2482 +
 drivers/pinctrl/sh-pfc/sh_pfc.h   |1 +
 5 files changed, 2495 insertions(+)
 create mode 100644 drivers/pinctrl/sh-pfc/pfc-r8a77470.c

diff --git a/drivers/pinctrl/sh-pfc/Kconfig b/drivers/pinctrl/sh-pfc/Kconfig
index c11b789..1d9b7e0 100644
--- a/drivers/pinctrl/sh-pfc/Kconfig
+++ b/drivers/pinctrl/sh-pfc/Kconfig
@@ -44,6 +44,11 @@ config PINCTRL_PFC_R8A7745
 depends on ARCH_R8A7745
 select PINCTRL_SH_PFC
 
+config PINCTRL_PFC_R8A77470
+def_bool y
+depends on ARCH_R8A77470
+select PINCTRL_SH_PFC
+
 config PINCTRL_PFC_R8A7778
def_bool y
depends on ARCH_R8A7778
diff --git a/drivers/pinctrl/sh-pfc/Makefile b/drivers/pinctrl/sh-pfc/Makefile
index 463775f..b486fcd 100644
--- a/drivers/pinctrl/sh-pfc/Makefile
+++ b/drivers/pinctrl/sh-pfc/Makefile
@@ -6,6 +6,7 @@ obj-$(CONFIG_PINCTRL_PFC_R8A73A4)   += pfc-r8a73a4.o
 obj-$(CONFIG_PINCTRL_PFC_R8A7740)  += pfc-r8a7740.o
 obj-$(CONFIG_PINCTRL_PFC_R8A7743)  += pfc-r8a7791.o
 obj-$(CONFIG_PINCTRL_PFC_R8A7745)  += pfc-r8a7794.o
+obj-$(CONFIG_PINCTRL_PFC_R8A77470) += pfc-r8a77470.o
 obj-$(CONFIG_PINCTRL_PFC_R8A7778)  += pfc-r8a7778.o
 obj-$(CONFIG_PINCTRL_PFC_R8A7779)  += pfc-r8a7779.o
 obj-$(CONFIG_PINCTRL_PFC_R8A7790)  += pfc-r8a7790.o
diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c
index 74861b7..b069fe3 100644
--- a/drivers/pinctrl/sh-pfc/core.c
+++ b/drivers/pinctrl/sh-pfc/core.c
@@ -503,6 +503,12 @@ static const struct of_device_id sh_pfc_of_table[] = {
.data = _pinmux_info,
},
 #endif
+#ifdef CONFIG_PINCTRL_PFC_R8A77470
+   {
+   .compatible = "renesas,pfc-r8a77470",
+   .data = _pinmux_info,
+   },
+#endif
 #ifdef CONFIG_PINCTRL_PFC_R8A7778
{
.compatible = "renesas,pfc-r8a7778",
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77470.c 
b/drivers/pinctrl/sh-pfc/pfc-r8a77470.c
new file mode 100644
index 000..5742e85
--- /dev/null
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a77470.c
@@ -0,0 +1,2482 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * R8A77470 processor support - PFC hardware block.
+ *
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ */
+
+#include 
+
+#include "sh_pfc.h"
+
+#define CPU_ALL_PORT(fn, sfx)  \
+   PORT_GP_23(0, fn, sfx), \
+   PORT_GP_23(1, fn, sfx), \
+   PORT_GP_32(2, fn, sfx), \
+   PORT_GP_17(3, fn, sfx), \
+   PORT_GP_1(3, 27, fn, sfx),  \
+   PORT_GP_1(3, 28, fn, sfx),  \
+   PORT_GP_1(3, 29, fn, sfx),  \
+   PORT_GP_26(4, fn, sfx), \
+   PORT_GP_32(5, fn, sfx)
+
+enum {
+   PINMUX_RESERVED = 0,
+
+   PINMUX_DATA_BEGIN,
+   GP_ALL(DATA),
+   PINMUX_DATA_END,
+
+   PINMUX_FUNCTION_BEGIN,
+   GP_ALL(FN),
+
+   /* GPSR0 */
+   FN_USB0_PWEN, FN_USB0_OVC, FN_USB1_PWEN, FN_USB1_OVC, FN_CLKOUT,
+   FN_IP0_3_0, FN_IP0_7_4, FN_IP0_11_8, FN_IP0_15_12, FN_IP0_19_16,
+   FN_IP0_23_20, FN_IP0_27_24, FN_IP0_31_28, FN_MMC0_CLK_SDHI1_CLK,
+   FN_MMC0_CMD_SDHI1_CMD, FN_MMC0_D0_SDHI1_D0, FN_MMC0_D1_SDHI1_D1,
+   FN_MMC0_D2_SDHI1_D2, FN_MMC0_D3_SDHI1_D3, FN_IP1_3_0,
+   FN_IP1_7_4, FN_MMC0_D6, FN_MMC0_D7,
+
+   /* GPSR1 */
+   FN_IP1_11_8, FN_IP1_15_12, FN_IP1_19_16, FN_IP1_23_20, FN_IP1_27_24,
+   FN_IP1_31_28, FN_IP2_3_0, FN_IP2_7_4, FN_IP2_11_8, FN_IP2_15_12,
+   FN_IP2_19_16, FN_IP2_23_20, FN_IP2_27_24, FN_IP2_31_28, FN_IP3_3_0,
+   FN_IP3_7_4, FN_IP3_11_8, FN_IP3_15_12, FN_IP3_19_16, FN_IP3_23_20,
+   FN_IP3_27_24, FN_IP3_31_28, FN_IP4_3_0,
+
+   /* GPSR2 */
+   FN_IP4_7_4, FN_IP4_11_8, FN_IP4_15_12, FN_IP4_19_16, FN_IP4_23_20,
+   FN_IP4_27_24, FN_IP4_31_28, FN_IP5_3_0, FN_IP5_7_4, FN_IP5_11_8,
+   FN_IP5_15_12, FN_IP5_19_16, FN_IP5_23_20, FN_IP5_27_24, FN_IP5_31_28,
+   FN_IP6_3_0, FN_IP6_7_4, FN_IP6_11_8, FN_IP6_15_12, FN_IP6_19_16,
+   FN_IP6_23_20, FN_IP6_27_24, FN_IP6_31_28, FN_IP7_3_0, FN_IP7_7_4,
+   FN_IP7_11_8,