Re: [PATCH v2 1/2] arm64: dts: renesas: Add Renesas R8A77990 SoC support

[Simon Horman]

On Wed, Apr 25, 2018 at 02:47:41AM +, Yoshihiro Shimoda wrote:
> Hi, Simon-san,
> 
> > From: Simon Horman, Sent: Tuesday, April 24, 2018 5:37 PM
> > 
> > On Tue, Apr 24, 2018 at 10:26:37AM +0200, Geert Uytterhoeven wrote:
> > > Hi Shimoda-san,
> > >
> > > On Fri, Apr 20, 2018 at 2:28 PM, Yoshihiro Shimoda
> > >  wrote:
> > > > This patch adds basic support for the Renesas R-Car E3 (R8A77990) SoC:
> > > >   - PSCI
> > > >   - CPU (single)
> > > >   - Cache controller
> > > >   - Main clocks and controller
> > > >   - Interrupt controller
> > > >   - Timer
> > > >   - PMU
> > > >   - Reset controller
> > > >   - Product register
> > > >   - System controller
> > > >   - UART for console
> > > >
> > > > Inspried by a patch by Takeshi Kihara in the BSP.
> > > >
> > > > Signed-off-by: Yoshihiro Shimoda 
> > >
> > > Thanks for you patch!
> > 
> > Thanks for your review.
> > 
> > As I've already applied this patch I'd like to ask Shimoda-san
> > to send incremental patches to address the issues you raise below.
> 
> I got it. I'll send incremental patches.

Thanks, much appreciated.

RE: [PATCH v2 1/2] arm64: dts: renesas: Add Renesas R8A77990 SoC support

[Yoshihiro Shimoda]

Hi, Simon-san,

> From: Simon Horman, Sent: Tuesday, April 24, 2018 5:37 PM
> 
> On Tue, Apr 24, 2018 at 10:26:37AM +0200, Geert Uytterhoeven wrote:
> > Hi Shimoda-san,
> >
> > On Fri, Apr 20, 2018 at 2:28 PM, Yoshihiro Shimoda
> >  wrote:
> > > This patch adds basic support for the Renesas R-Car E3 (R8A77990) SoC:
> > >   - PSCI
> > >   - CPU (single)
> > >   - Cache controller
> > >   - Main clocks and controller
> > >   - Interrupt controller
> > >   - Timer
> > >   - PMU
> > >   - Reset controller
> > >   - Product register
> > >   - System controller
> > >   - UART for console
> > >
> > > Inspried by a patch by Takeshi Kihara in the BSP.
> > >
> > > Signed-off-by: Yoshihiro Shimoda 
> >
> > Thanks for you patch!
> 
> Thanks for your review.
> 
> As I've already applied this patch I'd like to ask Shimoda-san
> to send incremental patches to address the issues you raise below.

I got it. I'll send incremental patches.

Best regards,
Yoshihiro Shimoda

> > > --- /dev/null
> > > +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
> > > @@ -0,0 +1,127 @@
> > > +/* SPDX-License-Identifier: GPL-2.0 */
> > > +/*
> > > + * Device Tree Source for the r8a77990 SoC
> > > + *
> > > + * Copyright (C) 2018 Renesas Electronics Corp.
> > > + */
> > > +
> > > +#include 
> > > +#include 
> > > +
> > > +/ {
> > > +   compatible = "renesas,r8a77990";
> > > +   #address-cells = <2>;
> > > +   #size-cells = <2>;
> > > +
> > > +   cpus {
> >
> > > +   L2_CA53: cache-controller@0 {
> > > +   compatible = "cache";
> > > +   reg = <0>;
> >
> > Please no unit-addresses and reg properties for cache controllers.
> >
> > > +   power-domains = < 21>;
> > > +   cache-unified;
> > > +   cache-level = <2>;
> > > +   };
> > > +   };
> >
> > > +   psci {
> > > +   compatible = "arm,psci-0.2";
> >
> > "arm,psci-1.0", "arm,psci-0.2"?
> >
> > > +   method = "smc";
> > > +   };
> > > +
> > > +   soc: soc {
> >
> > > +   rst: reset-controller@e616 {
> > > +   compatible = "renesas,r8a77990-rst";
> > > +   reg = <0 0xe616 0 0x0200>;
> > > +   };
> > > +
> > > +   sysc: system-controller@e618 {
> > > +   compatible = "renesas,r8a77990-sysc";
> > > +   reg = <0 0xe618 0 0x0400>;
> > > +   #power-domain-cells = <1>;
> > > +   };
> > > +
> > > +   scif2: serial@e6e88000 {
> > > +   compatible = "renesas,scif-r8a77990",
> > > +"renesas,rcar-gen3-scif", 
> > > "renesas,scif";
> > > +   reg = <0 0xe6e88000 0 64>;
> > > +   interrupts = ;
> > > +   clocks = < CPG_MOD 310>;
> > > +   clock-names = "fck";
> >
> > I assume you plan to add the other clocks later? That's fine for me.
> >
> > > +   power-domains = < 32>;
> > > +   resets = < 310>;
> > > +   status = "disabled";
> > > +   };
> >
> > Gr{oetje,eeting}s,
> >
> > Geert
> >
> > --
> > Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- 
> > ge...@linux-m68k.org
> >
> > In personal conversations with technical people, I call myself a hacker. But
> > when I'm talking to journalists I just say "programmer" or something like 
> > that.
> > -- Linus Torvalds
> >

Re: [PATCH v2 1/2] arm64: dts: renesas: Add Renesas R8A77990 SoC support

[Simon Horman]

On Tue, Apr 24, 2018 at 10:26:37AM +0200, Geert Uytterhoeven wrote:
> Hi Shimoda-san,
> 
> On Fri, Apr 20, 2018 at 2:28 PM, Yoshihiro Shimoda
>  wrote:
> > This patch adds basic support for the Renesas R-Car E3 (R8A77990) SoC:
> >   - PSCI
> >   - CPU (single)
> >   - Cache controller
> >   - Main clocks and controller
> >   - Interrupt controller
> >   - Timer
> >   - PMU
> >   - Reset controller
> >   - Product register
> >   - System controller
> >   - UART for console
> >
> > Inspried by a patch by Takeshi Kihara in the BSP.
> >
> > Signed-off-by: Yoshihiro Shimoda 
> 
> Thanks for you patch!

Thanks for your review.

As I've already applied this patch I'd like to ask Shimoda-san
to send incremental patches to address the issues you raise below.

> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
> > @@ -0,0 +1,127 @@
> > +/* SPDX-License-Identifier: GPL-2.0 */
> > +/*
> > + * Device Tree Source for the r8a77990 SoC
> > + *
> > + * Copyright (C) 2018 Renesas Electronics Corp.
> > + */
> > +
> > +#include 
> > +#include 
> > +
> > +/ {
> > +   compatible = "renesas,r8a77990";
> > +   #address-cells = <2>;
> > +   #size-cells = <2>;
> > +
> > +   cpus {
> 
> > +   L2_CA53: cache-controller@0 {
> > +   compatible = "cache";
> > +   reg = <0>;
> 
> Please no unit-addresses and reg properties for cache controllers.
> 
> > +   power-domains = < 21>;
> > +   cache-unified;
> > +   cache-level = <2>;
> > +   };
> > +   };
> 
> > +   psci {
> > +   compatible = "arm,psci-0.2";
> 
> "arm,psci-1.0", "arm,psci-0.2"?
> 
> > +   method = "smc";
> > +   };
> > +
> > +   soc: soc {
> 
> > +   rst: reset-controller@e616 {
> > +   compatible = "renesas,r8a77990-rst";
> > +   reg = <0 0xe616 0 0x0200>;
> > +   };
> > +
> > +   sysc: system-controller@e618 {
> > +   compatible = "renesas,r8a77990-sysc";
> > +   reg = <0 0xe618 0 0x0400>;
> > +   #power-domain-cells = <1>;
> > +   };
> > +
> > +   scif2: serial@e6e88000 {
> > +   compatible = "renesas,scif-r8a77990",
> > +"renesas,rcar-gen3-scif", 
> > "renesas,scif";
> > +   reg = <0 0xe6e88000 0 64>;
> > +   interrupts = ;
> > +   clocks = < CPG_MOD 310>;
> > +   clock-names = "fck";
> 
> I assume you plan to add the other clocks later? That's fine for me.
> 
> > +   power-domains = < 32>;
> > +   resets = < 310>;
> > +   status = "disabled";
> > +   };
> 
> Gr{oetje,eeting}s,
> 
> Geert
> 
> -- 
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- 
> ge...@linux-m68k.org
> 
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like 
> that.
> -- Linus Torvalds
> 

Re: [PATCH v2 1/2] arm64: dts: renesas: Add Renesas R8A77990 SoC support

[Geert Uytterhoeven]

Hi Shimoda-san,

On Fri, Apr 20, 2018 at 2:28 PM, Yoshihiro Shimoda
 wrote:
> This patch adds basic support for the Renesas R-Car E3 (R8A77990) SoC:
>   - PSCI
>   - CPU (single)
>   - Cache controller
>   - Main clocks and controller
>   - Interrupt controller
>   - Timer
>   - PMU
>   - Reset controller
>   - Product register
>   - System controller
>   - UART for console
>
> Inspried by a patch by Takeshi Kihara in the BSP.
>
> Signed-off-by: Yoshihiro Shimoda 

Thanks for you patch!

> --- /dev/null
> +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
> @@ -0,0 +1,127 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Device Tree Source for the r8a77990 SoC
> + *
> + * Copyright (C) 2018 Renesas Electronics Corp.
> + */
> +
> +#include 
> +#include 
> +
> +/ {
> +   compatible = "renesas,r8a77990";
> +   #address-cells = <2>;
> +   #size-cells = <2>;
> +
> +   cpus {

> +   L2_CA53: cache-controller@0 {
> +   compatible = "cache";
> +   reg = <0>;

Please no unit-addresses and reg properties for cache controllers.

> +   power-domains = < 21>;
> +   cache-unified;
> +   cache-level = <2>;
> +   };
> +   };

> +   psci {
> +   compatible = "arm,psci-0.2";

"arm,psci-1.0", "arm,psci-0.2"?

> +   method = "smc";
> +   };
> +
> +   soc: soc {

> +   rst: reset-controller@e616 {
> +   compatible = "renesas,r8a77990-rst";
> +   reg = <0 0xe616 0 0x0200>;
> +   };
> +
> +   sysc: system-controller@e618 {
> +   compatible = "renesas,r8a77990-sysc";
> +   reg = <0 0xe618 0 0x0400>;
> +   #power-domain-cells = <1>;
> +   };
> +
> +   scif2: serial@e6e88000 {
> +   compatible = "renesas,scif-r8a77990",
> +"renesas,rcar-gen3-scif", "renesas,scif";
> +   reg = <0 0xe6e88000 0 64>;
> +   interrupts = ;
> +   clocks = < CPG_MOD 310>;
> +   clock-names = "fck";

I assume you plan to add the other clocks later? That's fine for me.

> +   power-domains = < 32>;
> +   resets = < 310>;
> +   status = "disabled";
> +   };

Gr{oetje,eeting}s,

Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

[PATCH v2 1/2] arm64: dts: renesas: Add Renesas R8A77990 SoC support

[Yoshihiro Shimoda]

This patch adds basic support for the Renesas R-Car E3 (R8A77990) SoC:
  - PSCI
  - CPU (single)
  - Cache controller
  - Main clocks and controller
  - Interrupt controller
  - Timer
  - PMU
  - Reset controller
  - Product register
  - System controller
  - UART for console

Inspried by a patch by Takeshi Kihara in the BSP.

Signed-off-by: Yoshihiro Shimoda 
---
 arch/arm64/boot/dts/renesas/r8a77990.dtsi | 127 ++
 1 file changed, 127 insertions(+)
 create mode 100644 arch/arm64/boot/dts/renesas/r8a77990.dtsi

diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi 
b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
new file mode 100644
index 000..3a19b9e
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
@@ -0,0 +1,127 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Device Tree Source for the r8a77990 SoC
+ *
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ */
+
+#include 
+#include 
+
+/ {
+   compatible = "renesas,r8a77990";
+   #address-cells = <2>;
+   #size-cells = <2>;
+
+   cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   /* 1 core only at this point */
+   a53_0: cpu@0 {
+   compatible = "arm,cortex-a53", "arm,armv8";
+   reg = <0x0>;
+   device_type = "cpu";
+   power-domains = < 5>;
+   next-level-cache = <_CA53>;
+   enable-method = "psci";
+   };
+
+   L2_CA53: cache-controller@0 {
+   compatible = "cache";
+   reg = <0>;
+   power-domains = < 21>;
+   cache-unified;
+   cache-level = <2>;
+   };
+   };
+
+   extal_clk: extal {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   /* This value must be overridden by the board */
+   clock-frequency = <0>;
+   };
+
+   pmu_a53 {
+   compatible = "arm,cortex-a53-pmu";
+   interrupts-extended = < GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+   interrupt-affinity = <_0>;
+   };
+
+   psci {
+   compatible = "arm,psci-0.2";
+   method = "smc";
+   };
+
+   soc: soc {
+   compatible = "simple-bus";
+   interrupt-parent = <>;
+   #address-cells = <2>;
+   #size-cells = <2>;
+   ranges;
+
+   cpg: clock-controller@e615 {
+   compatible = "renesas,r8a77990-cpg-mssr";
+   reg = <0 0xe615 0 0x1000>;
+   clocks = <_clk>;
+   clock-names = "extal";
+   #clock-cells = <2>;
+   #power-domain-cells = <0>;
+   #reset-cells = <1>;
+   };
+
+   rst: reset-controller@e616 {
+   compatible = "renesas,r8a77990-rst";
+   reg = <0 0xe616 0 0x0200>;
+   };
+
+   sysc: system-controller@e618 {
+   compatible = "renesas,r8a77990-sysc";
+   reg = <0 0xe618 0 0x0400>;
+   #power-domain-cells = <1>;
+   };
+
+   scif2: serial@e6e88000 {
+   compatible = "renesas,scif-r8a77990",
+"renesas,rcar-gen3-scif", "renesas,scif";
+   reg = <0 0xe6e88000 0 64>;
+   interrupts = ;
+   clocks = < CPG_MOD 310>;
+   clock-names = "fck";
+   power-domains = < 32>;
+   resets = < 310>;
+   status = "disabled";
+   };
+
+   gic: interrupt-controller@f101 {
+   compatible = "arm,gic-400";
+   #interrupt-cells = <3>;
+   #address-cells = <0>;
+   interrupt-controller;
+   reg = <0x0 0xf101 0 0x1000>,
+ <0x0 0xf102 0 0x2>,
+ <0x0 0xf104 0 0x2>,
+ <0x0 0xf106 0 0x2>;
+   interrupts = ;
+   clocks = < CPG_MOD 408>;
+   clock-names = "clk";
+   power-domains = < 32>;
+   resets = < 408>;
+   };
+
+   prr: chipid@fff00044 {
+   compatible = "renesas,prr";
+   reg = <0 0xfff00044 0 4>;
+   };
+   };
+
+   timer {
+   compatible = "arm,armv8-timer";
+   interrupts-extended = < GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) 
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