Re: [PATCH v2 14/19] ARM64: dts: r8a77965: Add SCIF device nodes

[Simon Horman]

On Tue, Feb 20, 2018 at 04:12:16PM +0100, Jacopo Mondi wrote:
> Add SCIF[0-5] device nodes for M3-N (r8a77965) SoC.
> 
> Signed-off-by: Jacopo Mondi 
> Reviewed-by: Geert Uytterhoeven 

Thanks, applied with prefix updated to:

arm64: dts: renesas: r8a77965:

[PATCH v2 14/19] ARM64: dts: r8a77965: Add SCIF device nodes

[Jacopo Mondi]

Add SCIF[0-5] device nodes for M3-N (r8a77965) SoC.

Signed-off-by: Jacopo Mondi 
Reviewed-by: Geert Uytterhoeven 

---
v1 -> v2:
- Replace clock and power areas definition with raw numbers
- Fix compatible strings s/r8a7796/r8a77965/
---
 arch/arm64/boot/dts/renesas/r8a77965.dtsi | 85 ---
 1 file changed, 79 insertions(+), 6 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi 
b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
index b83dafc..3cb1a33 100644
--- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
@@ -335,27 +335,100 @@
};
 
scif0: serial@e6e6 {
-   /* placeholder */
+   compatible = "renesas,scif-r8a77965",
+"renesas,rcar-gen3-scif", "renesas,scif";
+   reg = <0 0xe6e6 0 64>;
+   interrupts = ;
+   clocks = < CPG_MOD 207>,
+< CPG_CORE 20>,
+<_clk>;
+   clock-names = "fck", "brg_int", "scif_clk";
+   dmas = < 0x51>, < 0x50>,
+  < 0x51>, < 0x50>;
+   dma-names = "tx", "rx", "tx", "rx";
+   power-domains = < 32>;
+   resets = < 207>;
+   status = "disabled";
};
 
scif1: serial@e6e68000 {
-   /* placeholder */
+   compatible = "renesas,scif-r8a77965",
+"renesas,rcar-gen3-scif", "renesas,scif";
+   reg = <0 0xe6e68000 0 64>;
+   interrupts = ;
+   clocks = < CPG_MOD 206>,
+< CPG_CORE 20>,
+<_clk>;
+   clock-names = "fck", "brg_int", "scif_clk";
+   dmas = < 0x53>, < 0x52>,
+  < 0x53>, < 0x52>;
+   dma-names = "tx", "rx", "tx", "rx";
+   power-domains = < 32>;
+   resets = < 206>;
+   status = "disabled";
};
 
scif2: serial@e6e88000 {
-   /* placeholder */
+   compatible = "renesas,scif-r8a77965",
+"renesas,rcar-gen3-scif", "renesas,scif";
+   reg = <0 0xe6e88000 0 64>;
+   interrupts = ;
+   clocks = < CPG_MOD 310>,
+< CPG_CORE 20>,
+<_clk>;
+   clock-names = "fck", "brg_int", "scif_clk";
+   power-domains = < 32>;
+   resets = < 310>;
+   status = "disabled";
};
 
scif3: serial@e6c5 {
-   /* placeholder */
+   compatible = "renesas,scif-r8a77965",
+"renesas,rcar-gen3-scif", "renesas,scif";
+   reg = <0 0xe6c5 0 64>;
+   interrupts = ;
+   clocks = < CPG_MOD 204>,
+< CPG_CORE 20>,
+<_clk>;
+   clock-names = "fck", "brg_int", "scif_clk";
+   dmas = < 0x57>, < 0x56>;
+   dma-names = "tx", "rx";
+   power-domains = < 32>;
+   resets = < 204>;
+   status = "disabled";
};
 
scif4: serial@e6c4 {
-   /* placeholder */
+   compatible = "renesas,scif-r8a77965",
+"renesas,rcar-gen3-scif", "renesas,scif";
+   reg = <0 0xe6c4 0 64>;
+   interrupts = ;
+   clocks = < CPG_MOD 203>,
+< CPG_CORE 20>,
+<_clk>;
+   clock-names = "fck", "brg_int", "scif_clk";
+   dmas = < 0x59>, < 0x58>;
+   dma-names = "tx", "rx";
+   power-domains = < 32>;
+   resets = < 203>;
+   status = "disabled";
};
 
scif5: serial@e6f3 {
-   /* placeholder */
+   compatible = "renesas,scif-r8a77965",
+"renesas,rcar-gen3-scif", "renesas,scif";
+   reg = <0 0xe6f3 0 64>;
+   interrupts = ;
+   clocks = < CPG_MOD 202>,
+< CPG_CORE 20>,
+