Hi Daniel, Magnus,
On Thu, Aug 10, 2017 at 12:56 PM, Daniel Lezcano
wrote:
> On 10/08/2017 11:01, Geert Uytterhoeven wrote:
>> On Tue, Jul 11, 2017 at 1:56 PM, Simon Horman wrote:
>>> On Thu, Nov 24, 2016 at 11:58:43AM +0100, Simon Horman wrote:
On Fri, Aug 04, 2017 at 12:32:53PM +0900, Harunobu Kurokawa wrote:
> When no PCIe card is inserted, there is a memory leak as
> pci_free_resource_list is not called before returning.
>
> v2:
> separate the patch to two files.
>
> Harunobu Kurokawa (1):
> PCI: rcar-pcie: Fix memory leak when
Hi Marek,
You forgot to CC Lee (added ;-)
On Mon, Jul 17, 2017 at 10:45 PM, Marek Vasut wrote:
> Add DT bindings for the ROHM BD9571MWV-M PMIC. This PMIC has
> the following features:
> - multiple voltage monitors for 1V8, 2V5, 3V3 voltage rail
> - one voltage regulator
Hi Andrew, Niklas,
On Sun, Jul 30, 2017 at 9:51 PM, Niklas Söderlund
wrote:
> On 2017-07-30 19:07:38 +0200, Andrew Lunn wrote:
>> > @@ -2041,6 +2073,11 @@ static int ravb_probe(struct platform_device *pdev)
>> >
>> > priv->chip_id = chip_id;
>> >
>> > + /*
Hi Niklas,
On Sun, Jul 30, 2017 at 10:56 PM, Niklas Söderlund
wrote:
> This is a RFC for how I imagine the final DT for the video capture nodes
> will look. Since the DT file layout changed recently I wanted to post a
> RFC before I include these in my
On Wed, Jul 26, 2017 at 1:23 PM, Yoshihiro Shimoda
wrote:
> From: Hiromitsu Yamasaki
>
> This patch adds USB3.0-IF0 clock for R8A7796 SoC.
>
> Signed-off-by: Hiromitsu Yamasaki
>
Add support for r8a7743/5 SoC.Renesas RZ/G1[ME] (R8A7743/5) SDHI
is identical to the R-Car Gen2 family.
Signed-off-by: Biju Das
---
This patch is compiled and tested against mmc/next.
drivers/mmc/host/renesas_sdhi_sys_dmac.c | 2 ++
1 file changed, 2 insertions(+)
Define the iWave RainboW-G20D-Qseven board dependent part of the
SDHI1 device node.
Signed-off-by: Biju Das
---
arch/arm/boot/dts/r8a7743-iwg20d-q7.dts | 48 +
1 file changed, 48 insertions(+)
diff --git
This series aims to add SDHI support for r8a7743 SoC.
This series has been compiled and tested against renesas-dev tag
renesas-devel-20170814-v4.13-rc5.
There is no compile time dependencies.It has run time dependency on
[PATCH ] mmc: renesas_sdhi: Add r8a7743/5 support.
https
Enable the SDHI0 controller on iWave RZG1M Qseven SOM.
Signed-off-by: Biju Das
---
arch/arm/boot/dts/r8a7743-iwg20m.dtsi | 17 +
1 file changed, 17 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7743-iwg20m.dtsi
b/arch/arm/boot/dts/r8a7743-iwg20m.dtsi
Add the SDHI controllers to the r8a7743 device tree.
Signed-off-by: Biju Das
---
arch/arm/boot/dts/r8a7743.dtsi | 42 ++
1 file changed, 42 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7743.dtsi
Hi Simon,
2017-08-04 15:26 GMT+02:00 Simon Horman :
> From: Dien Pham
>
> Current, OPP tables are defined temporary,
> they are being evaluated and adjust in future.
>
> Based in part on work by Hien Dang.
>
> Signed-off-by: Dien Pham
On Fri, Jun 30, 2017 at 10:10 AM, Geert Uytterhoeven
wrote:
> On Thu, May 11, 2017 at 10:03 AM, Geert Uytterhoeven
> wrote:
>> Magnus reported that on sh7722/Migo-R, pinctrl registration fails with:
>>
>> sh-pfc pfc-sh7722: pin 0 already
Hello!
On 08/13/2017 02:12 PM, Arvind Yadav wrote:
platform_device_id are not supposed to change at runtime. All functions
working with platform_device_id provided by
work with const platform_device_id. So mark the non-const structs as
const.
Signed-off-by: Arvind Yadav
Hi Simon,
On Wed, Aug 9, 2017 at 10:21 AM, Simon Horman
wrote:
> commit d10bbd156926 ("gpio: rcar: add gen[123] fallback compatibility
> strings") deprecated the generic compat string, renesas,gpio-rcar. After
> further discussion this appears not to have been
Add support for r8a7743/5 SoC. Renesas RZ/G1[ME] (R8A7743/5) SDHI
is identical to the R-Car Gen2 family.
Signed-off-by: Biju Das
---
This patch is compiled and tested againt linux next tag
next-20170811. This patch depend on the driver change
[PATCH ] mmc: renesas_sdhi:
On Thu, Aug 10, 2017 at 10:06 AM, Simon Horman wrote:
> On Wed, Aug 09, 2017 at 10:21:06AM +0200, Simon Horman wrote:
>> commit d10bbd156926 ("gpio: rcar: add gen[123] fallback compatibility
>> strings") deprecated the generic compat string, renesas,gpio-rcar. After
>> further
Hi Simon,
On Wed, Aug 2, 2017 at 2:48 PM, Simon Horman wrote:
> Provide a whitelist for Gen3 SoC ES versions for both the SYS DMAC and
> internal DMAC variants of the SDHI driver. This is to allow drivers to
> only initialise for Gen3 SoC ES versions for which they
The entities provide a single .configure operation which configures the
object into the target display list, based on the vsp1_entity_params
selection.
This restricts us to a single function prototype for both static
configuration (the pre-stream INIT stage) and the dynamic runtime stages
for
The display list originally allocated a body of 256 entries to store all
of the register lists required for each frame.
This has now been separated into fragments for constant stream setup, and
runtime updates.
Empirical testing shows that the body0 now uses a maximum of 41
registers for each
Extend the display list body with a reference count, allowing bodies to
be kept as long as a reference is maintained. This provides the ability
to keep a cached copy of bodies which will not change, so that they can
be re-applied to multiple display lists.
Signed-off-by: Kieran Bingham
Currently the entities store their configurations into a display list.
Adapt this such that the code can be configured into a body fragment
directly, allowing greater flexibility and control of the content.
All users of vsp1_dl_list_write() are removed in this process, thus it
too is removed.
A
We are now able to configure a pipeline directly into a local display
list body. Take advantage of this fact, and create a cacheable body to
store the configuration of the pipeline in the video object.
vsp1_video_pipeline_run() is now the last user of the pipe->dl object.
Convert this function to
Each display list currently allocates an area of DMA memory to store register
settings for the VSP1 to process. Each of these allocations adds pressure to
the IPMMU TLB entries.
We can reduce the pressure by pre-allocating larger areas and dividing the area
across multiple bodies represented as a
Each display list allocates a body to store register values in a dma
accessible buffer from a dma_alloc_wc() allocation. Each of these
results in an entry in the TLB, and a large number of display list
allocations adds pressure to this resource.
Reduce TLB pressure on the IPMMUs by allocating
Adapt the dl->body0 object to use an object from the fragment pool.
This greatly reduces the pressure on the TLB for IPMMU use cases, as
all of the lists use a single allocation for the main body.
The CLU and LUT objects pre-allocate a pool containing two bodies,
allowing a userspace update
The fragment write function relies on the code never asking it to
write more than the entries available in the list.
Currently with each list body containing 256 entries, this is fine,
but we can reduce this number greatly saving memory.
In preparation of this - add a level of protection to
Hi Chris,
On Mon, Aug 14, 2017 at 5:15 PM, Chris Paterson
wrote:
>> From: geert.uytterhoe...@gmail.com [mailto:geert.uytterhoe...@gmail.com]
>> On Behalf Of Geert Uytterhoeven
>> Sent: 14 August 2017 15:22
>>
>> On Mon, Aug 14, 2017 at 1:19 PM, Biju Das
> Is this supposed to have any impact on the issue on Magnus' r8a7794/alt, where
> tuning failed before?
Nope, I'd be very surprised if it does. I wanted to look at this issue
with my next free time slot.
signature.asc
Description: PGP signature
> From: geert.uytterhoe...@gmail.com [mailto:geert.uytterhoe...@gmail.com]
> On Behalf Of Geert Uytterhoeven
> Sent: 14 August 2017 15:22
>
> On Mon, Aug 14, 2017 at 1:19 PM, Biju Das wrote:
> > Add support for r8a7743/5 SoC.Renesas RZ/G1[ME] (R8A7743/5) SDHI is
> >
Hello Geert,
> From: geert.uytterhoe...@gmail.com [mailto:geert.uytterhoe...@gmail.com]
> On Behalf Of Geert Uytterhoeven
>
> Hi Chris,
>
> On Mon, Aug 14, 2017 at 5:15 PM, Chris Paterson
> wrote:
> >> From: geert.uytterhoe...@gmail.com
> >>
On Wed, Jul 26, 2017 at 11:54:36PM +0200, Wolfram Sang wrote:
> As mentioned in a response to a previous patch, clock handling for Renesas
> R-Car is done via RuntimePM. Patch 1 implements that consequently. Patch 2
> is a cleanup then possible and patch 3 is a trivial copyright update.
>
> This
On Sun, Jul 30, 2017 at 3:07 PM, Hans Verkuil wrote:
> From: Hans Verkuil
Probably the one-line summary should be
ARM: dts: koelsch: Add CEC clock for HDMI transmitter
> The adv7511 on the Koelsch board has a 12 MHz fixed clock
> for the CEC
Hi Simon,
On Mon, Aug 14, 2017 at 07:10:23AM +0200, Simon Horman wrote:
> On Tue, Aug 08, 2017 at 08:54:45PM +0200, Wolfram Sang wrote:
> >
> > > As it is an "RFT" I'm happy to apply it if you repost
> > > it or otherwise indicate that is what you would like to happen.
> >
> > As discussed in a
On Mon, Aug 14, 2017 at 08:32:30AM -0700, Guenter Roeck wrote:
> On Wed, Jul 26, 2017 at 11:54:36PM +0200, Wolfram Sang wrote:
> > As mentioned in a response to a previous patch, clock handling for Renesas
> > R-Car is done via RuntimePM. Patch 1 implements that consequently. Patch 2
> > is a
Hi Simon,
On Tue, Aug 8, 2017 at 10:39 AM, Simon Horman
wrote:
> Use newly added R-Car GPIO Gen1 fallback compat string
> in place of now deprecated non-generation specific
> R-Car GPIO fallback compat string in DT of r8a7778 SoC.
>
> This should have no run-time
On Tue, Aug 8, 2017 at 10:39 AM, Simon Horman
wrote:
> Use newly added R-Car GPIO Gen1 fallback compat string
> in place of now deprecated non-generation specific
> R-Car GPIO fallback compat string in DT of r8a7779 SoC.
>
> This should have no run-time effect as the
On Tue, Aug 8, 2017 at 10:39 AM, Simon Horman
wrote:
> Use newly added R-Car GPIO Gen2 fallback compat string
> in place of now deprecated non-generation specific
> R-Car GPIO fallback compat string in the DT of the r8a7790 SoC.
>
> This should have no run-time effect
On Tue, Aug 8, 2017 at 10:39 AM, Simon Horman
wrote:
> Use newly added R-Car GPIO Gen3 fallback compat string
> in place of now deprecated non-generation specific
> R-Car GPIO fallback compat string in the DT of the r8a7796 SoC.
>
> This should have no run-time effect
On Tue, Aug 8, 2017 at 10:39 AM, Simon Horman
wrote:
> Use newly added R-Car GPIO Gen3 fallback compat string
> in place of now deprecated non-generation specific
> R-Car GPIO fallback compat string in the DT of the r8a7795 SoC.
>
> This should have no run-time effect
On Mon, Aug 14, 2017 at 1:19 PM, Biju Das wrote:
> Add support for r8a7743/5 SoC.Renesas RZ/G1[ME] (R8A7743/5) SDHI
> is identical to the R-Car Gen2 family.
>
> Signed-off-by: Biju Das
> ---
> This patch is compiled and tested against mmc/next.
>
Hi Wolfram,
On Wed, Aug 9, 2017 at 9:00 PM, Wolfram Sang
wrote:
> There is one SDHI instance on Gen2 which does not have the CBSY bit.
> So, turn CBSY usage into an extra flag and set it accordingly. This has
> the additional advantage that we can also set it
Hi Viresh,
On Mon, Aug 7, 2017 at 5:37 AM, Viresh Kumar wrote:
> On 04-08-17, 15:18, Simon Horman wrote:
>> From: Khiem Nguyen
>>
>> After the commit "a399dc9fc50 cpufreq: shmobile: Use generic platdev
>> driver", will use
On Tue, Aug 8, 2017 at 10:39 AM, Simon Horman
wrote:
> Use newly added R-Car GPIO Gen2 fallback compat string
> in place of now deprecated non-generation specific
> R-Car GPIO fallback compat string in the DT of the r8a7792 SoC.
>
> This should have no run-time effect
On Tue, Aug 8, 2017 at 10:39 AM, Simon Horman
wrote:
> Use newly added R-Car GPIO Gen2 fallback compat string
> in place of now deprecated non-generation specific
> R-Car GPIO fallback compat string in the DT of the r8a7793 SoC.
>
> This should have no run-time effect
On Wed, Aug 9, 2017 at 10:26 AM, Simon Horman
wrote:
> Use newly added R-Car SATA Gen2 fallback compat string
> in the DT of the r8a7790 SoC.
>
> This should have no run-time effect as the driver matches against
> the per-SoC compat string before the fallback compat
On Wed, Aug 9, 2017 at 10:26 AM, Simon Horman
wrote:
> Use newly added R-Car SATA Gen2 fallback compat string
> in the DT of the r8a7791 SoC.
>
> This should have no run-time effect as the driver matches against
> the per-SoC compat string before the fallback compat
On Sat, Aug 12, 2017 at 8:09 AM, Bhumika Goyal wrote:
> Make the structure const as it is only passed to the function
> devm_regmap_add_irq_chip having the corresponding argument as const.
> Done using Coccinelle.
>
> Signed-off-by: Bhumika Goyal
Patch
On Tue, Aug 8, 2017 at 3:04 PM, Biju Das wrote:
> Define the iWave RainboW-G20D-Qseven board dependent part of the
> RTC device node.
>
> Signed-off-by: Biju Das
> @@ -54,3 +59,16 @@
> micrel,led-mode = <1>;
> };
> };
>
On Tue, Aug 8, 2017 at 10:39 AM, Simon Horman
wrote:
> Use newly added R-Car GPIO Gen2 fallback compat string
> in place of now deprecated non-generation specific
> R-Car GPIO fallback compat string in the DT of the r8a7743 SoC.
>
> This should have no run-time effect
On Tue, Aug 8, 2017 at 10:39 AM, Simon Horman
wrote:
> Use newly added R-Car GPIO Gen2 fallback compat string
> in place of now deprecated non-generation specific
> R-Car GPIO fallback compat string in the DT of the r8a7791 SoC.
>
> This should have no run-time effect
On Wed, Aug 9, 2017 at 10:26 AM, Simon Horman
wrote:
> Use newly added R-Car SATA Gen3 fallback compat string
> in the DT of the r8a7795 SoC.
>
> This should have no run-time effect as the driver matches against
> the per-SoC compat string before the fallback compat
On Thu, Aug 10, 2017 at 3:49 PM, Chris Paterson
wrote:
>> From: Wolfram Sang [mailto:w...@the-dreams.de]
>> Sent: 10 August 2017 12:24
>>
>>
>> > > >+i2c6: i2c@e60b {
>> > >
>> > >I'd use iic0 as the label.
Sergei: I assume you meant "iic3"?
> -Original Message-
> From: geert.uytterhoe...@gmail.com [mailto:geert.uytterhoe...@gmail.com]
> On Behalf Of Geert Uytterhoeven
> Sent: 14 August 2017 15:12
> To: Biju Das
> Cc: Rob Herring ; Mark Rutland
> ; Simon
From: Kieran Bingham
Hi Geert,
Please consider pulling the following changes into renesas-drivers.
This series is based upon a merge of my previous pa-improvements/v4 and
airlied-drm/drm-next to base on top of all pending VSP1 changes.
The following changes
* Ard Biesheuvel [170811 12:37]:
> On 11 August 2017 at 16:13, Tony Lindgren wrote:
> > * Ard Biesheuvel [170805 13:54]:
> >> Replace the open coded PC relative offset calculations with a pair
> >> of adr_l invocations.
>
On 14 August 2017 at 17:19, Tony Lindgren wrote:
> * Ard Biesheuvel [170811 12:37]:
>> On 11 August 2017 at 16:13, Tony Lindgren wrote:
>> > * Ard Biesheuvel [170805 13:54]:
>> >> Replace the open coded
On Mon, Aug 14, 2017 at 05:47:28PM +0200, Wolfram Sang wrote:
> On Mon, Aug 14, 2017 at 08:32:30AM -0700, Guenter Roeck wrote:
> > On Wed, Jul 26, 2017 at 11:54:36PM +0200, Wolfram Sang wrote:
> > > As mentioned in a response to a previous patch, clock handling for Renesas
> > > R-Car is done via
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